EP0651914A4 - Structure for use in producing semiconductor devices with buried contacts and method for its preparation. - Google Patents

Structure for use in producing semiconductor devices with buried contacts and method for its preparation.

Info

Publication number
EP0651914A4
EP0651914A4 EP94917430A EP94917430A EP0651914A4 EP 0651914 A4 EP0651914 A4 EP 0651914A4 EP 94917430 A EP94917430 A EP 94917430A EP 94917430 A EP94917430 A EP 94917430A EP 0651914 A4 EP0651914 A4 EP 0651914A4
Authority
EP
European Patent Office
Prior art keywords
trench
wafer
trenches
major surface
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94917430A
Other languages
German (de)
French (fr)
Other versions
EP0651914A1 (en
Inventor
Srinivasamohan Narayanan
John H Wohlgemuth
Steven P Roncin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BP Solar International LLC
Original Assignee
BP Corp North America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BP Corp North America Inc filed Critical BP Corp North America Inc
Publication of EP0651914A1 publication Critical patent/EP0651914A1/en
Publication of EP0651914A4 publication Critical patent/EP0651914A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to structures for use in producing semiconductor devices with buried contacts and methods for producing these semiconductor devices, and, more particularly, to an improved structure and method for producing at least one or a plurality of semiconductor devices, particularly improved solar cells for converting incident light into electricity.
  • Electrode is understood to mean a portion of the semiconductor device that produces a desired electronic function; for example, in the case of a photovoltaic or solar cell, a region which is capable of converting incident light into electrical energy.
  • the region may have conductive layers or elements to conduct electrical energy from the region.
  • a type of buried contact in a transistor device is shown in Figs. 5 and 6 of U.S. Patent No. 3,163,916.
  • a type of buried contact in a colar cell is shown in Figures 1 and 2 of U.S. Patent No. 4,726,850 and a method for forming buried contacts in a solar cell is described in U.S. Patent No. 4,748,130.
  • Another object of the present invention is to provide an improved structure for use in providing at least one semiconductor device having at least one conductive buried contact in which the device can be readily and inexpensively isolated electronically from the remainder of the structure.
  • Another object of the invention is to provide improved photovoltaic devices having conductive buried contacts extending inwardly of the surface of the semiconductor body of the devices, in which the efficiency of the devices are maintained during isolation of the devices from each other during production.
  • Still another object of the present invention is to provide an improved method for producing photovoltaic devices from a semiconductor wafer in which the efficiency of the devices are maintained during isolation of the devices from each other during their production.
  • an improved structure which is useful in producing at least one and preferably a plurality of semiconductor devices having buried contacts.
  • the structure of the present invention comprises a semiconductor body having a major surface and at least one trench, and preferably a plurality of trenches, formed in the body with each trench extending from the major surface into the body to a predetermined depth with the bottom of each of the trenches being covered by a layer of insulating material.
  • the at least one trench, and in the preferred arrangement each of the plurality of trenches, is arranged in a predetermined position wherein each trench defines at least one border of a semiconductor device to be obtained from the semiconductor body.
  • the structure also includes at least one conductive buried contact, and preferably a plurality of conductive buried contacts.
  • Each buried contact is positioned in a groove formed in the major surface of the body, the groove extending inwardly from the major surface to a depth less than the predetermined depth of the trench or trenches and containing conductive material.
  • the body contains a plurality of grooves containing conductive material, with at least one conductive groove being positioned within each of the device areas defined by the trench or trenches.
  • the structure of the present invention thus has a trench or a plurality of trenches whose bottoms contain only insulating material, and wherein the groove or grooves containing conductive material are preferably present in the body extending between trenches, with the trenches providing means for aiding electronic isolation, and if desired separation, of the body and the conductive buried contacts into at least one and preferably at least two or more semiconductor devices.
  • the structure also includes a diffused layer extending from the major surface of the body and if the trench or trenches are formed in the body prior to the formation of the diffused layer, the diffused layer will extend inwardly from the bottom of the trench or trenches.
  • the diffused layer may be formed prior to the formation of the trench or trenches and in such case, a diffused layer will not be present at and will not extend inwardly from the bottom of the trench or trenches.
  • trench or trenches serve as pre-isolation trench or trenches for the cells, and isolation of individual cells is accomplished without cell performance degradation.
  • isolation is effected by cutting through the insulating layer and the diffusion layer at the bottom of the pre-isolation trench or selected trenches, rather than cutting through metallized conductive buried contacts as in the related art heretofore described.
  • the present invention includes an improved method for the production of at least one semiconductor device having a body of semiconductor material and at least one conductive buried contact extending inwardly from one major surface of the body.
  • the improved method also provides for the production of a plurality of semiconductor devices, each having a body of semiconductor material and having at least one conductive buried contact extending inwardly from one major surface of the body.
  • the improved method comprises preparing a wafer of semiconductor material having at least one major surface, and as the initial steps thereafter, forming a diffused layer extending beneath the one major surface and cutting at least one trench, and preferably a plurality of trenches, in the wafer.
  • the diffused layer serves as electronically active regions in the semiconductor device or devices to be obtained. If the diffused layer is formed before the trench or trenches are cut, then the latter is cut to a predetermined depth greater than the depth to which the diffused layer extends.
  • the cutting of the trench or trenches can be performed prior to the formation of the diffused layer, and in such case, the diffused layer may also extend inwardly at least from the bottom of the trench or trenches. In either case, each of the trenches are cut so as to extend inwardly from the one major surface to a predetermined depth, and each of the trenches are positioned to define at least one border of a -device to be obtained from the semiconductor wafer.
  • the method further comprises covering at least the bottom of the said trench, or the plurality of trenches, with a layer of insulating material, and, further, forming at least one groove or preferably a plurality of grooves (hereafter "the grooves") in the major surface of the wafer extending inwardly from the major surface to a depth less than the predetermined depth to which the trench or trenches are cut, and coating, for example by deposition, the recessed portions of the grooves with conductive material such as metal.
  • the grooves a plurality of grooves
  • the coating of the grooves with conductive material may be performed, for example, by depositing metal on selected portions of the wafer and in the grooves by removing any insulating material that may be present, (for example, by etching the material from the selected portions) and depositing metal, such as nickel, on the exposed semiconductor material at the major surface and in the grooves by methods known in the art.
  • the method may optionally include the coating of other layers of materials, for example by forming masks and by the selective depositing of materials on the major surface, on the conductive material in the grooves, or on subsequent layers by methods also known in the art.
  • the cutting of each trench, and the covering of at least the bottom thereof with a layer of insulating material, which prevents the subsequent coating of metal on the bottom of the trench defines the at least one border of the device or solar cell obtained and isolates the at least one device or solar cell from an edge thereof.
  • the method of the invention also includes, when the at least one trench is cut before the formation of the diffused layer, a subsequent step of isolating the wafer into one or a plurality of semiconductor devices by cutting the wafer along the bottom of the insulated trench or trenches, respectively, at least to a depth greater than the depth to which the diffused layer extends from the bottom of the trench, thus defining a border of the device and isolating the device from an edge thereof. If it is desired to separate the device from the wafer, or the devices from the wafer and each other, the wafer can be cut through the bottom of the trench or selected trenches either from the major surface downwardly or from the bottom of the wafer toward the major surface.
  • the trench or trenches are free of conductive material, and therefore the trenches define the border and isolate the edge of the semiconductor device if the diffused layer is not present at the bottom of the trenches, or if the diffused layer is present at the bottom of the trenches, then upon cutting the structure along the bottom of the trenches at least to a depth greater than the depth to which the diffused layer extends, to separate or isolate the semiconductor devices from each other.
  • the edges of the devices thus obtained are free of conductive material extending perpendicularly at the edge beyond the areas or layers on which conductive material was intentionally deposited.
  • the edges of the separated devices frequently included conductive material extending across the region that is cut, causing deterioration in the performance of the device and often shorting of the device.
  • the forming of the grooves by cutting, rather than by use of a laser is advantageous in forming improved semiconductor devices. Where a laser is used, although the groove need not extend to the edge of the device, the laser must melt the silicon or other material of the wafer causing the groove to be wider than desired.
  • a saw particularly a dicing saw, and more preferably a diamond based dicing saw, whose use is the preferred method of forming the grooves, creates a deeper, narrower groove, which is preferred in ,_the production of semiconductor devices, particularly solar cells.
  • forming grooves by using a laser is relatively slow, and as silicon, for example, is known as a good heat conductor, during the use of a laser the wafer tends to conduct heat away from the area being melted.
  • Cutting with a saw, particularly a dicing saw cuts the semiconductor material of the wafer faster than with a laser.
  • FIG. 1 is a flow chart showing schematically an embodiment of the method for preparing a photovoltaic device in accordance with the present invention.
  • FIG. 2 is a series of cross-sectional views of a semiconductor wafer as it is processed through the steps described in FIG. 1.
  • FIG. 3 is a schematic cross-sectional plan view of one embodiment of a photovoltaic structure made in accordance with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT
  • a silicon wafer 10 of desired size for example a circular disc approximately 4 inches in diameter and 10 mils in thickness or a polycrystalline wafer 11.4 cm by
  • trenches 14 are cut into the wafer from the top surface 12, which is a major surface of the wafer, to a depth of from about 50 to about 70 microns deep using a diamond dicing saw. It has been found to be convenient for the trenches to be approximately 40-100 microns wide, depending on the width of the saw blade.
  • the trenches are cut in a pattern so that they form the outline of the sections which will define the separated cells. Trenches 14 will serve as pre-isolation trenches for the separation or isolation of the individual buried contact solar cells.
  • Wafer 10 is then etched, for example by being placed in a boiling solution of sodium hydroxide, to remove any saw damage due to cutting of the top surface 12 or of the trenches 14.
  • Wafer 10 is next treated to diffusion, for example in this embodiment, the wafer is treated with phosphorus from a solid diffusion source.
  • the wafers and the solid sources are edge stacked in quartz carriers.
  • the quartz carrier is then loaded into a furnace at around 750°C.
  • the wafers and solid sources are heated to 840°C for approximately 20 minutes in a gas flow of 6 liters per minute of nitrogen.
  • a layer 16 of insulating material in the present embodiment a passivating silicon oxide layer, is applied, for example, by oxidation of the surface 12 of the silicon wafer in the manner known in the art.
  • insulating materials including oxides of materials different from the silicon of the wafer and nitrides including silicon nitride _,can be utilized.
  • insulating material is also formed or deposited at the bottom of trenches 14, as indicated by reference number 18, and it is preferred that the formation of layer 16 continue for a sufficient period until the bottom of trenches 14 are covered with insulating material.
  • Grooves 20 are cut through insulating layer 16 and surface 12 and into wafer 10, for example, with a laser or with a saw.
  • grooves 20 are cut with a saw, and most preferably with a dicing saw, although use of a saw usually will require cutting along the entire length or chords of the surface 12 of the wafer from one end or side to the other, while cutting with a laser permits the cutting of grooves 20 less than along the entire length.
  • the use of a saw is preferred for many of the same reasons described above with respect to the cutting of trenches 14.
  • Grooves 20 are cut to a depth of less than the depth of the trenches 14, and preferably, to a depth of approximately 30 to 40 microns. Although grooves 20 are shown in FIGs.
  • grooves 20 can be cut at any desired angle with respect to trenches 14. If desired, trenches 14 could be cut to a depth in the range of 70-100 microns if a greater depth of grooves 20 is desired, for example in the range of 50 to 70 microns, while maintaining the trenches 14 at a greater depth than grooves 20; i.e., trenches 14 and grooves 20 cannot both be at or about 70 microns in this structure.
  • the wafer is etched under milder conditions than the etching of trenches 14 as noted above, for example, with a potassium hydroxide solution to prepare grooves 20 for metal deposition.
  • the grooves 20 are then subjected to a further, deeper diffusion of the type indicated above to prepare the grooves 20 to receive and adhere the metal upon deposition.
  • a layer 22 of metal is thereafter coated on the bottom surface of wafer 10 and into the grooves 20.
  • aluminum is deposited, for example by evaporation, onto the back or bottom (the surface opposite to top surface 12) of wafer 10 in the manner known to the art, although other known techniques could be used.
  • a coating of aluminum of a thickness of 1 to 2 microns is satisfactory.
  • the aluminum coating is sintered, for example by heating to a temperature of approximately 980 * C for up to 18 hours, forming a back surface field on the rear of the device.
  • first nickel and then copper are deposited by plating or other deposition methods known to the art, to complete the back metallization layer 22 and to fill the grooves 20.
  • the plating of nickel is cured by heating to approximately 300 * C in nitrogen before applying the copper.
  • conductive material i.e. aluminum, nickel and copper in this embodiment
  • insulating material e.g., silicon oxide in this embodiment
  • the wafer 10 is separated into individual solar cells by cutting the wafer through the trenches 14, starting with the bottoms of trenches 14 and continuing through the semiconductor body and through layer 22 or starting at the back and cutting through layer 22, continuing through the semiconductor body and then finally reaching the bottoms of the trenches 14.
  • a saw is used rather than a laser for many of the reasons discussed above, and particularly as a saw does not melt the material and generate heat to the same extent as does a laser.
  • a diamond saw blade is utilized to enable cutting to a narrow width, thus reducing wastage, and with the generation of a minimum amount of heat. In this manner, the wafer is separated into a plurality of cells or devices having top edges which are substantially free of conductive material in unwanted areas, i.e. free of metal, except at the desired contact areas.
  • solar cells were prepared from the same silicon wafer batch prepared as indicated above, but in the first two indicated samples the cutting of trenches 14 were omitted. The resulting cells were measured for efficiency of converting sun light (solar energy) into electrical energy using AM 1.5 illumination at 100 mW/cm 2 .

Abstract

An improved structure and method for use in producing semiconductor devices with buried contacts and particularly photovoltaic devices, such as solar cells, that have conductive material (22) in grooves (20) extending inwardly of one major surface (12) of the body (10), the structure having a plurality of trenches (14) formed in the body to a predetermined depth greater than the depth of the conductive grooves (20), which trenches aid in isolating and defining the edges of semiconductor devices or solar cells, and provide means for aiding in the separation of separate semiconductor devices or solar cells from the structure by cutting the structure through the bottom of selected trenches (14).

Description

STRUCTURE FOR USE IN PRODUCING
SEMICONDUCTOR DEVICES WITH BURIED CONTACTS AND
METHOD FOR ITS PREPARATION
BACKGROUND OF THE INVENTION
lj. Field of the Invention
The present invention relates to structures for use in producing semiconductor devices with buried contacts and methods for producing these semiconductor devices, and, more particularly, to an improved structure and method for producing at least one or a plurality of semiconductor devices, particularly improved solar cells for converting incident light into electricity.
2. Description of Related Art
In the manufacture of semiconductor devices, it is common to form a large area semiconductor structure or wafer, to treat the wafer to fabricate electronically active regions, to apply conductive layers and insulating layers, and to cut or break the wafer into separate semiconductor devices or chips. "Electronically active region" is understood to mean a portion of the semiconductor device that produces a desired electronic function; for example, in the case of a photovoltaic or solar cell, a region which is capable of converting incident light into electrical energy. The region may have conductive layers or elements to conduct electrical energy from the region. In some devices, and in particular in some solar cells, it is desirable to have one or more conductive elements extend inwardly from portions of the surface of the semiconductor body of the device, which is also known as having buried contacts. A type of buried contact in a transistor device is shown in Figs. 5 and 6 of U.S. Patent No. 3,163,916. A type of buried contact in a colar cell is shown in Figures 1 and 2 of U.S. Patent No. 4,726,850 and a method for forming buried contacts in a solar cell is described in U.S. Patent No. 4,748,130.
It has also been proposed in U.S. Patent No. 4,097,310, to form a solar cell on a wafer of silicon and to saw the wafer at and through a junction on the surface of the wafer at which electrons are generated when the surface is exposed to light, using a dicing saw having a diamond blade. This proposal requires sawing through the junction as well as the wafer.
One particular method of producing a plurality of separate semiconductor devices is proposed in U.S. Patent No. 4,355,457. As there described, a plurality of semiconductor regions, each having at least one PN junction, are formed on a wafer, following which two sets of relatively wide U-shaped channels are cut in the wafer by sawing or by use of a laser, each set being generally perpendicular to the other. The channels are etched to smooth the channel, and the resulting structure is separated into the plurality of devices by breaking the wafer along the center of the channels. Thus, while the proposed method may facilitate the breaking of the wafer, the method is disadvantageous in that the method requires cutting through the wafer after all of the other processes have been completed. If the device has continuous buried contacts, the act of cutting through the channels will result in damage to the metallization in the buried contacts, resulting in less than optimum isolation, i.e. electronic isolation of the device and therefore poor device performance.
SUMMARY OF THE INVENTION
Hence, it is one object of the present invention to provide an improved method for inexpensively producing semiconductor devices which does not require the cutting of conductive elements or materials, and avoids the deterioration in the efficiency of such devices normally occurring in such devices as a result of the cutting operation. It is still another object of the present invention to provide an improved structure for use in producing semiconductor devices having conductive portions extending inwardly of the surface of the semiconductor body, such conductive portions being also referred to as conductive buried contacts, as used herein, in which the devices can be readily and inexpensively isolated from the structure without deterioration of the efficiency of the devices.
Another object of the present invention is to provide an improved structure for use in providing at least one semiconductor device having at least one conductive buried contact in which the device can be readily and inexpensively isolated electronically from the remainder of the structure. Another object of the invention is to provide improved photovoltaic devices having conductive buried contacts extending inwardly of the surface of the semiconductor body of the devices, in which the efficiency of the devices are maintained during isolation of the devices from each other during production.
Still another object of the present invention is to provide an improved method for producing photovoltaic devices from a semiconductor wafer in which the efficiency of the devices are maintained during isolation of the devices from each other during their production.
These and other objects and advantages of the present invention will be apparent from the following description.
In accordance with the present invention, an improved structure is provided which is useful in producing at least one and preferably a plurality of semiconductor devices having buried contacts. The structure of the present invention comprises a semiconductor body having a major surface and at least one trench, and preferably a plurality of trenches, formed in the body with each trench extending from the major surface into the body to a predetermined depth with the bottom of each of the trenches being covered by a layer of insulating material. The at least one trench, and in the preferred arrangement each of the plurality of trenches, is arranged in a predetermined position wherein each trench defines at least one border of a semiconductor device to be obtained from the semiconductor body.
The structure also includes at least one conductive buried contact, and preferably a plurality of conductive buried contacts. Each buried contact is positioned in a groove formed in the major surface of the body, the groove extending inwardly from the major surface to a depth less than the predetermined depth of the trench or trenches and containing conductive material. Preferably, the body contains a plurality of grooves containing conductive material, with at least one conductive groove being positioned within each of the device areas defined by the trench or trenches. The structure of the present invention thus has a trench or a plurality of trenches whose bottoms contain only insulating material, and wherein the groove or grooves containing conductive material are preferably present in the body extending between trenches, with the trenches providing means for aiding electronic isolation, and if desired separation, of the body and the conductive buried contacts into at least one and preferably at least two or more semiconductor devices.
The structure also includes a diffused layer extending from the major surface of the body and if the trench or trenches are formed in the body prior to the formation of the diffused layer, the diffused layer will extend inwardly from the bottom of the trench or trenches. The diffused layer may be formed prior to the formation of the trench or trenches and in such case, a diffused layer will not be present at and will not extend inwardly from the bottom of the trench or trenches. Where one or more buried contact solar cells are to be produced from the structure, such trench or trenches serve as pre-isolation trench or trenches for the cells, and isolation of individual cells is accomplished without cell performance degradation. If the trench has been cut prior to the formation of the diffused layer, isolation is effected by cutting through the insulating layer and the diffusion layer at the bottom of the pre-isolation trench or selected trenches, rather than cutting through metallized conductive buried contacts as in the related art heretofore described.
The present invention includes an improved method for the production of at least one semiconductor device having a body of semiconductor material and at least one conductive buried contact extending inwardly from one major surface of the body. The improved method also provides for the production of a plurality of semiconductor devices, each having a body of semiconductor material and having at least one conductive buried contact extending inwardly from one major surface of the body.
The improved method comprises preparing a wafer of semiconductor material having at least one major surface, and as the initial steps thereafter, forming a diffused layer extending beneath the one major surface and cutting at least one trench, and preferably a plurality of trenches, in the wafer. The diffused layer serves as electronically active regions in the semiconductor device or devices to be obtained. If the diffused layer is formed before the trench or trenches are cut, then the latter is cut to a predetermined depth greater than the depth to which the diffused layer extends. Alternatively, the cutting of the trench or trenches can be performed prior to the formation of the diffused layer, and in such case, the diffused layer may also extend inwardly at least from the bottom of the trench or trenches. In either case, each of the trenches are cut so as to extend inwardly from the one major surface to a predetermined depth, and each of the trenches are positioned to define at least one border of a -device to be obtained from the semiconductor wafer.
The method further comprises covering at least the bottom of the said trench, or the plurality of trenches, with a layer of insulating material, and, further, forming at least one groove or preferably a plurality of grooves (hereafter "the grooves") in the major surface of the wafer extending inwardly from the major surface to a depth less than the predetermined depth to which the trench or trenches are cut, and coating, for example by deposition, the recessed portions of the grooves with conductive material such as metal. The coating of the grooves with conductive material may be performed, for example, by depositing metal on selected portions of the wafer and in the grooves by removing any insulating material that may be present, (for example, by etching the material from the selected portions) and depositing metal, such as nickel, on the exposed semiconductor material at the major surface and in the grooves by methods known in the art. The method may optionally include the coating of other layers of materials, for example by forming masks and by the selective depositing of materials on the major surface, on the conductive material in the grooves, or on subsequent layers by methods also known in the art.
If the diffused layer was formed as the first step after the preparation of the wafer, then the cutting of each trench, and the covering of at least the bottom thereof with a layer of insulating material, which prevents the subsequent coating of metal on the bottom of the trench, defines the at least one border of the device or solar cell obtained and isolates the at least one device or solar cell from an edge thereof.
The method of the invention also includes, when the at least one trench is cut before the formation of the diffused layer, a subsequent step of isolating the wafer into one or a plurality of semiconductor devices by cutting the wafer along the bottom of the insulated trench or trenches, respectively, at least to a depth greater than the depth to which the diffused layer extends from the bottom of the trench, thus defining a border of the device and isolating the device from an edge thereof. If it is desired to separate the device from the wafer, or the devices from the wafer and each other, the wafer can be cut through the bottom of the trench or selected trenches either from the major surface downwardly or from the bottom of the wafer toward the major surface.
In the improved structure of the present invention, the trench or trenches (hereafter "the trenches") are free of conductive material, and therefore the trenches define the border and isolate the edge of the semiconductor device if the diffused layer is not present at the bottom of the trenches, or if the diffused layer is present at the bottom of the trenches, then upon cutting the structure along the bottom of the trenches at least to a depth greater than the depth to which the diffused layer extends, to separate or isolate the semiconductor devices from each other. The edges of the devices thus obtained are free of conductive material extending perpendicularly at the edge beyond the areas or layers on which conductive material was intentionally deposited. In a wafer structure without the trenches as defined in the present invention, the edges of the separated devices frequently included conductive material extending across the region that is cut, causing deterioration in the performance of the device and often shorting of the device. In the method of the present invention, the forming of the grooves by cutting, rather than by use of a laser, is advantageous in forming improved semiconductor devices. Where a laser is used, although the groove need not extend to the edge of the device, the laser must melt the silicon or other material of the wafer causing the groove to be wider than desired. A saw, particularly a dicing saw, and more preferably a diamond based dicing saw, whose use is the preferred method of forming the grooves, creates a deeper, narrower groove, which is preferred in ,_the production of semiconductor devices, particularly solar cells. Further, forming grooves by using a laser is relatively slow, and as silicon, for example, is known as a good heat conductor, during the use of a laser the wafer tends to conduct heat away from the area being melted. Cutting with a saw, particularly a dicing saw, cuts the semiconductor material of the wafer faster than with a laser. Moreover, it is convenient and less expensive to add multiple saw blades to a cutting or milling machine to form the parallel grooves, than to attempt to employ multiple laser beam devices.
The present invention will be more fully understood from the accompanying drawings which are to be read in conjunction with the description of the preferred embodiment, both showing and describing for illustration, a solar cell structure and a method for its preparation, for use in producing a plurality of individual buried contact solar cells, the trenches serving as pre-isolation trenches to facilitate the cutting of the individual cells from the structure without cell performance degradation. However, it should be understood that this invention is applicable for the production of other semiconductor devices as well as for solar cells.
BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a flow chart showing schematically an embodiment of the method for preparing a photovoltaic device in accordance with the present invention. FIG. 2 is a series of cross-sectional views of a semiconductor wafer as it is processed through the steps described in FIG. 1.
FIG. 3 is a schematic cross-sectional plan view of one embodiment of a photovoltaic structure made in accordance with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT
In the preferred embodiment of the method of the
^.present invention as illustrated in FIG. 1, and with reference to the structure of the present invention shown in FIG. 3, a silicon wafer 10 of desired size, for example a circular disc approximately 4 inches in diameter and 10 mils in thickness or a polycrystalline wafer 11.4 cm by
11.4 cm square is obtained. In accordance with the present embodiment of the invention, trenches 14 are cut into the wafer from the top surface 12, which is a major surface of the wafer, to a depth of from about 50 to about 70 microns deep using a diamond dicing saw. It has been found to be convenient for the trenches to be approximately 40-100 microns wide, depending on the width of the saw blade. The trenches are cut in a pattern so that they form the outline of the sections which will define the separated cells. Trenches 14 will serve as pre-isolation trenches for the separation or isolation of the individual buried contact solar cells. Wafer 10 is then etched, for example by being placed in a boiling solution of sodium hydroxide, to remove any saw damage due to cutting of the top surface 12 or of the trenches 14.
Wafer 10 is next treated to diffusion, for example in this embodiment, the wafer is treated with phosphorus from a solid diffusion source. To effect such treatment, the wafers and the solid sources are edge stacked in quartz carriers. The quartz carrier is then loaded into a furnace at around 750°C. The wafers and solid sources are heated to 840°C for approximately 20 minutes in a gas flow of 6 liters per minute of nitrogen.
After diffusion of the wafer in which top surface 12 has been diffused with a phosphorus junction that extends inwardly of the surface approximately 3000 A, a layer 16 of insulating material, in the present embodiment a passivating silicon oxide layer, is applied, for example, by oxidation of the surface 12 of the silicon wafer in the manner known in the art. However, other insulating materials, including oxides of materials different from the silicon of the wafer and nitrides including silicon nitride _,,can be utilized. In the formation of insulating layer 16, insulating material is also formed or deposited at the bottom of trenches 14, as indicated by reference number 18, and it is preferred that the formation of layer 16 continue for a sufficient period until the bottom of trenches 14 are covered with insulating material.
Grooves 20 are cut through insulating layer 16 and surface 12 and into wafer 10, for example, with a laser or with a saw. Preferably, grooves 20 are cut with a saw, and most preferably with a dicing saw, although use of a saw usually will require cutting along the entire length or chords of the surface 12 of the wafer from one end or side to the other, while cutting with a laser permits the cutting of grooves 20 less than along the entire length. However, the use of a saw is preferred for many of the same reasons described above with respect to the cutting of trenches 14. Grooves 20 are cut to a depth of less than the depth of the trenches 14, and preferably, to a depth of approximately 30 to 40 microns. Although grooves 20 are shown in FIGs. 2 and 3 as having been cut parallel to one set of the trenches 14 for the sake of illustration, grooves 20 can be cut at any desired angle with respect to trenches 14. If desired, trenches 14 could be cut to a depth in the range of 70-100 microns if a greater depth of grooves 20 is desired, for example in the range of 50 to 70 microns, while maintaining the trenches 14 at a greater depth than grooves 20; i.e., trenches 14 and grooves 20 cannot both be at or about 70 microns in this structure.
The wafer is etched under milder conditions than the etching of trenches 14 as noted above, for example, with a potassium hydroxide solution to prepare grooves 20 for metal deposition. The grooves 20 are then subjected to a further, deeper diffusion of the type indicated above to prepare the grooves 20 to receive and adhere the metal upon deposition. A layer 22 of metal is thereafter coated on the bottom surface of wafer 10 and into the grooves 20. In , this embodiment, aluminum is deposited, for example by evaporation, onto the back or bottom (the surface opposite to top surface 12) of wafer 10 in the manner known to the art, although other known techniques could be used. A coating of aluminum of a thickness of 1 to 2 microns is satisfactory. The aluminum coating is sintered, for example by heating to a temperature of approximately 980*C for up to 18 hours, forming a back surface field on the rear of the device. To the sintered aluminum coating on the back of the wafer and to the grooves 20, first nickel and then copper are deposited by plating or other deposition methods known to the art, to complete the back metallization layer 22 and to fill the grooves 20. The plating of nickel is cured by heating to approximately 300*C in nitrogen before applying the copper.
It has been found that conductive material, i.e. aluminum, nickel and copper in this embodiment, is not deposited in the trenches 14, due to the presence of insulating material, e.g., silicon oxide in this embodiment, covering the bottoms of trenches 14.
The wafer 10 is separated into individual solar cells by cutting the wafer through the trenches 14, starting with the bottoms of trenches 14 and continuing through the semiconductor body and through layer 22 or starting at the back and cutting through layer 22, continuing through the semiconductor body and then finally reaching the bottoms of the trenches 14. Preferably, a saw is used rather than a laser for many of the reasons discussed above, and particularly as a saw does not melt the material and generate heat to the same extent as does a laser. Preferably a diamond saw blade is utilized to enable cutting to a narrow width, thus reducing wastage, and with the generation of a minimum amount of heat. In this manner, the wafer is separated into a plurality of cells or devices having top edges which are substantially free of conductive material in unwanted areas, i.e. free of metal, except at the desired contact areas.
As an example of the improved performance attained by using the structure and method of the present invention, solar cells were prepared from the same silicon wafer batch prepared as indicated above, but in the first two indicated samples the cutting of trenches 14 were omitted. The resulting cells were measured for efficiency of converting sun light (solar energy) into electrical energy using AM 1.5 illumination at 100 mW/cm2.
Efficiency of Converting Solar Energy To Electrical Energy
Sample * Efficiency
Without Isolation Trenches Cutting From Top 11. .5%
Cutting From Bottom 13. .0%
With Isolation Trenches Cutting From Top 14. .2% Cutting From Bottom 14. .7%
While a particular embodiment of the semiconductor structure and method of the invention has been shown and described, it will be appreciated by those skilled in the art that changes and modifications may be made thereto without departing from the invention in its broader aspects and as set forth in the following claims.

Claims

WE CLAIM; 1. An improved structure for use in producing from said structure at least one semiconductor device having a major surface and at least one conductive buried contact extending inwardly from the one major surface, comprising: a. a semiconductor body having a major surface; b. said, body having at least one trench, said trench being in a predetermined position defining at least one border of a device to be obtained from the semiconductor body, said trench extending from said major surface into said body to a depth greater than the depth of the at least one conductive buried contact in said semiconductor device and extending inwardly from said major surface; c. said body having a diffused layer extending inwardly at least from said major surface; d. said trench in said body having the bottom thereof covered by a layer of insulating material; e. wherein said trench defines the at least one border of the at least one semiconductor device obtained therefrom and isolates the at least one device from an edge thereof.
2. The improved structure of Claim 1 wherein said diffused layer also extends inwardly from at least the bottom of said at least one trench, said trench providing means for aiding the subsequent cutting of said body along at least the bottom of said trench to at least a depth ^greater than the depth to which said diffused layer extends from the bottom of said trench, to define the at least one border of the at least one semiconductor device obtained therefrom and to isolate the at least one device from an edge thereof.
3. The improved structure of Claim 1, wherein the semiconductor body is a silicon wafer and the layer of insulating material covering the bottom of the trench is silicon oxide formed from the semiconductor body.
4. The improved structure of Claim 2 for producing from said structure at least two semiconductor devices each having at least one conductive buried contact extending inwardly from one major surface, wherein said at least one trench is positioned to define at least one border of each of the at least two semiconductor devices to be obtained from the semiconductor body and said at least one trench provides means for aiding isolation of said body wherein said body may be cut along said at least one trench to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trench, to define the at least one border of each of the two semiconductive devices and to isolate the at least two semiconductor devices from an edge therefor. 5. The improved structure of Claim 2 for use in producing from said structure a plurality of semiconductor devices each having at least one conductive buried contact extending inwardly from one major surface, said structure body having a plurality of trenches, each of said trenches being positioned to define at least one border of at least one of the semiconductor devices to be obtained from the semiconductor body and each of said trenches extending from said major surface into said body to a depth greater than the depth of the at least one conductive buried contact, each of said trenches having the bottoms thereof covered by a layer of insulating material, and said trenches providing means for aiding isolation of said semiconductor devices wherein said body may be cut along selected of said trenches to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trenches, to define the at least one border of at least one of the semiconductive devices to be obtained and to isolate the at least one semiconductor device from an edge therefrom.
6. The structure of Claim 5, wherein the semiconductor body is a silicon wafer and the layer of insulating material covering the bottoms of said plurality of trenches is silicon oxide formed from the semiconductor body. 7. An improved photovoltaic device having at least one conductive buried contact extending inwardly from one major surface for use in producing at least one solar cell for converting incident radiant energy to electrical energy comprising: a. a semiconductor body having a major surface; b. said body having at least one trench, said trench being in a predetermined position defining at least one border of the at least one solar cell to be obtained from the semiconductor body, said trench extending from said major surface into said body to a depth greater than the depth of the at least one conductive buried contact in said body extending inwardly from said major surface; c. said body having a diffused layer extending r inwardly at least from said major surface; d. said trench in said body having the bottom thereof covered by a layer of insulating material; e. wherein said trench defines at least one border of the at least one solar cell obtained therefrom and isolates the at least one solar cell from an edge thereof.
8. The structure of Claim 7, wherein the semiconductor body is a silicon wafer and the layer of insulating material covering the bottom of the trench is silicon oxide formed from the semiconductor body.
9. The improved structure of Claim 7 wherein said diffused layer also extends inwardly from at least the bottom of said at least one trench, said trench providing means for aiding the subsequent cutting of said body along "at least the bottom of said trench to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trench, to define the at least one border of the at least one solar cell obtained therefrom and to isolate the at least one solar cell from an edge thereof.
10. The photovoltaic device of Claim 9 for use in producing from said device at least two solar cells each having at least one conductive buried contact extending inwardly from one major surface, wherein said at least one trench is positioned to define at least one border of each of the at least two solar cells to be obtained from the device and said at least one trench provides means for aiding isolation of said device wherein said body may be cut along said at least one trench to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trench, to define at least one border of each of the two solar cells and to isolate the at least two solar cells from an edge thereof.
11. The photovoltaic device of Claim 9 for use in producing from said device a plurality of solar cells each having at least one conductive buried contact extending inwardly from one major surface, said device having a plurality of trenches, each of said trenches being positioned to define at least one border of at least one of the solar cells to be obtained from the device and each of said trenches extending from said major surface into said body to a depth greater than the depth of the at least one conductive buried contact, each of said trenches having the bottoms thereof covered by a layer of insulating material, and said trenches providing means for aiding isolation of said solar cells wherein said device may be cut along selected of said trenches to a depth greater than the depth to which said diffused layer extends from the bottom of said trenches, to define the at least one border of at least one of the solar cells to be obtained and to isolate the at least one solar cell from an edge thereof.
12. The structure of Claim 11, wherein the semiconductor body is a silicon wafer and the layer of insulating material covering the bottoms of said plurality of trenches is silicon oxide formed from the semiconductor body.
13. An improved method for the production of at least one semiconductor device having a body of semiconductor material and having at least one conductive buried contact extending inwardly from one major surface of the body, comprising: preparing a wafer of semiconductor material, said wafer having at least one major surface of greater area than the device to be produced; forming a diffused layer extending inwardly at least from the at least one major surface; """"' cutting at least one trench in said wafer, said trench extending inwardly from said major surface to a predetermined depth greater than the depth to which the diffused layer extends, and said at least one trench being positioned to define at least one border of a device to be obtained from the semiconductor wafer; covering at least the bottom of said trench with a layer of insulating material; forming at least one groove in said major surface of said wafer extending inwardly from said major surface to a depth less than said predetermined depth of the trench; and coating said groove with conductive material; whereby said trench defines at least one border of the at least one semiconductor device obtained and isolates the at least one device from the edge thereof.
14. The improved method of Claim 13 wherein the step of cutting at least one trench in said wafer is performed prior to the forming of a diffused layer extending inwardly at least from the at least one major surface and wherein said diffused layer also extends inwardly from the bottom of said at least one trench, whereby said at least one trench provides means for aiding subsequent cutting of said wafer along at least the bottom of said trench to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trench, to define at least one border of the at least one semiconductor device obtained therefrom and to isolate the at least one device from an edge thereof.
15. The improved method of claim 14, wherein the at least one semiconductor device is separated from said wafer by cutting the wafer through the bottom of said trench.
16. The improved method of claim 15, wherein the cutting of said wafer to obtain the semiconductor device is performed by sawing said wafer through the surface opposite the said one major surface and the bottom of said trench.
17. The improved method of claim 15, wherein the cutting of said wafer to obtain the semiconductor device is performed by sawing said wafer through said trench from the top of the trench adjacent said major surface through the bottom of said trench and through the wafer.
18. The improved method of claim 13 for the production of a plurality of semiconductor devices having a body of semiconductor material and having at least one conductive buried contact extending inwardly from one major surface of the body, including: cutting a plurality of trenches in said wafer, each of said trenches extending inwardly from said major surface to a predetermined depth greater than the depth of the diffused layer, and each of said trenches being positioned to define at least one border of at least one of the devices to be obtained from the semiconductor wafer; covering at least the bottoms of said plurality of trenches with a layer of insulating material; said at least one groove being positioned with respect to said trenches so that at least a portion of said groove is positioned within the borders of at least one of the semiconductor devices to be obtained from said wafer; whereby each of said trenches defines at least one border of the at least one semiconductor device obtained and isolates the at least one device from an edge thereof.
19. The improved method of Claim 18 wherein the step of cutting the plurality of trenches in said wafer is performed prior to the forming of the diffused layer extending inwardly at least from the at least one major surface and wherein said diffused layer extends inwardly from the bottom of said plurality of trenches, whereby said plurality of trenches provides means for aiding subsequent cutting of said wafer along at least the bottom of said trenches to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trenches, to define at least one border of the at least one semiconductor device obtained therefrom and to isolate the at least one device from the edge thereof. 20. The improved method of claim 19, wherein the plurality of semiconductor devices are separated from said wafer by cutting the wafer through the bottoms of selected of said trenches.
21. The improved method of claim 20, wherein the cutting of said wafer into a plurality of semiconductor devices is performed by sawing said wafer through the surface opposite the said one major surface and the bottom of said selected trenches.
22. The improved method of claim 20, wherein the cutting of said wafer into a plurality of semiconductor devices is performed by sawing said wafer through said selected trenches from the top of the trenches adjacent said major surface through the bottom of said trenches and through the wafer.
23. An improved method for the production of at least one solar cell having at least one conductive buried contact extending inwardly from one major surface for converting incident radiant energy to electrical energy, comprising: preparing a wafer of semiconductor material, said wafer having at least one major surface; forming a diffused layer extending inwardly at least from the one major surface; cutting at least one trench in said wafer, said trench extending inwardly from said major surface to a predetermined depth greater that the depth to which the diffused layer extends, and being positioned to define at least one border of a solar cell to be obtained from the semiconductor wafer; covering at least the bottom of said trench with a layer of insulating material; forming at least one groove in said major surface of said wafer extending inwardly from said major surface to a depth less than said predetermined depth of the said trench; and coating said groove with conductive material; whereby said trench defines at least one border of the at least one solar cell obtained and isolates the at least one solar cell from an edge thereof.
24. The improved method of Claim 23 wherein the step of cutting at least one trench in said wafer is performed prior to the forming of the diffused layer extending inwardly at least from the at least one major surface and wherein said dif used layer extends inwardly from the bottom of said at least one trench, whereby said at least one trench provides means for aiding subsequent cutting of said wafer along at least the bottom of said trench to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trench, whereby the border of the at least one solar cell obtained from said wafer is defined by said at least one trench and said trench isolates the at least one solar cell from an edge thereof.
25. The improved method of claim 24, wherein the at least one solar cell device is separated from said wafer by cutting the wafer through the bottom of said trench.
26. The improved method of claim 23 for the production of a plurality of solar cells having at least one conductive buried contact extending inwardly from one major surface for converting incident radiant energy to electrical energy, including: cutting a plurality of trenches in said wafer, each of said trenches extending inwardly from said major surface to a predetermined depth greater than the depth to which the diffused layer extends, and each trench being positioned to define at least one border of at least one of the solar cells to be obtained from the semiconductor wafer; covering at least the bottoms of said plurality of trenches with a layer of insulating material; and said at least one groove being positioned with respect to said trenches so that at least a portion of said groove is positioned within the borders of at least one of the solar cells to be obtained from said wafer; whereby each of said trenches defines at least one border of the solar cells obtained and isolates the solar cells from an edge thereof.
27. The improved method of Claim 26 wherein the step of cutting the plurality of trenches in said wafer is performed prior to the forming of the diffused layer extending inwardly at least from the at least one major surface and wherein said diffused layer extends inwardly from the bottom of said plurality of trenches, whereby said plurality of trenches provides means for aiding subsequent cutting of said wafer along at least the bottom of said trenches to at least a depth greater than the depth to which said diffused layer extends from the bottom of said trenches, wherein each of said trenches defines at least one border of at least one solar cell obtained and isolates the at least one solar cell from an edge thereof.
28. The improved method of claim 27, wherein the plurality of solar cells are separated from said wafer by cutting the wafer through the bottoms of selected of said trenches.
29. The improved method of claim 28, wherein the cutting of said wafer into a plurality of separate solar cells is performed by sawing said wafer through the surface opposite the said one major surface and the bottom of selected trenches. 30. The improved method of claim 28, wherein the cutting of said wafer into a plurality of separate solar cells is performed by sawing said wafer through said trenches from the top of the trenches adjacent said major surface through the bottom of said selected trenches and through the wafer.
EP94917430A 1993-05-20 1994-05-20 Structure for use in producing semiconductor devices with buried contacts and method for its preparation. Withdrawn EP0651914A4 (en)

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US6084175A (en) * 1993-05-20 2000-07-04 Amoco/Enron Solar Front contact trenches for polycrystalline photovoltaic devices and semi-conductor devices with buried contacts
AU729342B2 (en) * 1995-11-14 2001-02-01 Bp Solar International Inc. Front contact trenches for polycrystalline photovoltaic devices and semi-conductor devices with buried contacts
AUPN736195A0 (en) * 1995-12-29 1996-01-25 Pacific Solar Pty Limited Improved laser grooving method
CN100576578C (en) * 2006-04-20 2009-12-30 无锡尚德太阳能电力有限公司 The method and the electrochemical depositer thereof that prepare solar cel electrode

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