EP0606231A1

EP0606231A1 - Combination liquid crystal display driver and varactor voltage power supply

Info

Publication number: EP0606231A1
Application number: EP92917702A
Authority: EP
Inventors: Walter Lee Davis
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1991-09-30
Filing date: 1992-04-27
Publication date: 1994-07-20
Also published as: WO1993007598A1; EP0606231A4; JPH06511365A

Abstract

Un récepteur d'appel sélectif (100), pouvant recevoir une source d'énergie (101) comprenant une première tension d'alimentation (506), produit une seconde tension d'alimentation (507) à partir de la source de puissance, et une troisième tension d'alimentation (508) à partir de la seconde tension. La seconde tension d'alimentation (507) est utilisée pour alimenter au moins un dispositif d'affichage de données (209), et la troisième tension (508) est utilisée pour alimenter au moins un élément déterminant la fréquence (204).A selective call receiver (100) capable of receiving an energy source (101) comprising a first supply voltage (506), produces a second supply voltage (507) from the power source, and a third supply voltage (508) from the second voltage. The second supply voltage (507) is used to supply at least one data display device (209), and the third voltage (508) is used to supply at least one frequency determining element (204).

Description

COMBINATION LIQUID CRYSTAL DISPLAY DRIVER AND VARACTOR VOLTAGE POWER SUPPLY

Field of the Invention

This invention relates in general to electronic devices having an information display and more particularly to a selective call receiver having an information display and a varactor tuned frequency element.

Background of the Invention

Radio communication systems typically use a receiver (e.g., a selective call receiver or "pager") that has at least one unique call address. These radios receive and decode an address, then typically alert the user to the presence of incoming information and operate to present this information. Radio communication systems are an excellent vehicle for delivering voice, numeric, alphanumeric or coded information to a user.

Contemporary information receivers employ an information display system comprising a liquid crystal display (LCD) that is driven by waveforms generated by a LCD multiplexer. The multiplexer processes information received or generated by the radio and presents this information on the LCD as textural or graphical symbols. This information, in the case of a selective call receiver, will typically represent a received message such as a telephone number or possibly a short alphanumeric message. Presently, the size constraints imposed by miniaturization of the typical selective call receiver prohibit using a voltage source (e.g., battery) that can directly furnish the voltage levels necessary to operate a LCD. Small, multi-cell batteries that could furnish the necessary voltage don't meet the conflicting requirement of a low internal resistance as necessitated by the use of high-current alerting devices such as a vibrator in the pager. This leaves a designer no choice but to use a single power cell and one or more voltage multipliers if they are to have sufficient energy density, a low internal resistance at high terminal currents, supply the power requirements of a CMOS microprocessor decoder and a LCD. An additional factor that must be considered in producing a commercially viable product for the selective call receiver market is that the power cell must be readily available. This narrows the choice to batteries that are available in supermarkets or drug stores, such as AA or AAA alkaline cells. Since a typical AA or AAA cell is rated at 1.4 volts DC, and a typical LCD requires at least 3 volts DC, a voltage multiplier must be used to generate the higher voltage.

Contemporary low current voltage multipliers used in portable electronic devices use a capacitive voltage doubler. As with all DC to DC voltage converters, a clock signal is required to drive a switch (or switches) that controls the charging and discharging of switched capacitor elements in a manner such that the voltage on an output storage capacitor is increased to a desired value. In most cases, the clock signal is generated using a low cost, free running RC (resistor-capacitor) oscillator. These systems work fine in applications (e.g., calculators, computers) where low power emissions of spurious frequency harmonics are of little or no concern. However, when a DC to DC voltage converter having a free running oscillator is placed in the vicinity of a receiver, a phenomena known as desense occurs. Desense is when the radio receiver is "de¬ sensitized" (degrades in sensitivity) due to an interfering signal that causes the desired signal to be distorted to the point where it can no longer be successfully recovered. In most cases, the RC oscillator used in a DC to DC converter is chosen to generate a signal having a duty cycle of roughly 50% at a non-critical frequency. Because of these criteria, these RC oscillators tend to vary widely in frequency with respect to their operating conditions and component variations. This is an undesirable condition for use in a radio receiver. Recently, trends in the portable radio industry have been to use synthesized local oscillator injection signals as opposed to the classical single crystal or channel element generated signals. This approach has merit because of the lower cost and improved reliability of products incorporating a single, low cost frequency reference element. The preferred method of implementing a frequency synthesizer in these products requires one or more varactor diodes and a corresponding number of controllable bias voltage supplies.

The varactor diode is a special diode that undergoes a predictable change in capacitance as a reverse voltage bias applied thereto is changed. Using this property, a voltage controlled oscillator (VCO) can be fabricated with the varactor acting as the reactive frequency control element. An alternative use of varactor diodes could be to construct a voltage tuned filter that tracks the programmed local oscillator frequency, thereby tuning a narrow band antenna matching circuit and preselector for optimal performance. The problem with using a conventional varactor tuning arrangement in a contemporary selective call receiver is that the voltage required to operate a varactor diode is much greater than the cell voltage of the radio. In fact, since a typical selective call receiver has a power cell voltage of only 1.4 volts DC and presently there are no varactor diodes that exhibit an appreciable change in capacitance over this voltage range, operation of a conventional voltage controlled varactor diode tuning circuit is impossible. Further, contemporary paging receivers commonly use a CMOS microcomputer as a signal decoder, and the supply voltage for the microcomputer has also been used to supply the bias voltages for any varactor diodes. However, advances in semiconductor fabrication technology as applied to CMOS devices, and particularly to CMOS microcomputers, now allow power supply voltages as low as two volts. Consequently, the overall power requirements of a microcomputer based radio system have dropped, but this decrease in supply voltage makes effective operation of varactor diodes impossible. Because of the constraints discussed, a novel method and apparatus must be found that can meet the power supply requirements of the various elements in a paging receiver while retaining the benefits of being small in size and lowering the overall power consumption.

Summary of the Invention

Briefly, according to the invention, there is provided a selective call receiver capable of receiving an energy source having a first supply voltage. The selective call receiver comprises first means for generating a second supply voltage from the energy source and second means for generating a third supply voltage from the second supply voltage. The second supply voltage is used to power at least an information display,- and the third supply voltage is used to power at least one frequency determining elemen .

Brief Description of the Drawings

FIG. 1 is a block diagram of a prior art selective call receiver.

FIG. 2 is a block diagram of a varactor tuned selective call receiver using a liquid crystal display voltage supply as a varactor bias source in accordance with a first embodiment of the present invention. FIG. 3 is an illustration of a prior art liquid crystal display supply voltage generator.

FIG. 4 is a block diagram of a frequency controlled liquid crystal display supply voltage generator in accordance with a second embodiment of the present invention.

FIG. 5 is an illustration of a frequency controlled liquid crystal display supply voltage generator in accordance with the first embodiment of the present invention.

Description of a Preferred Embodiment

Referring to FIG. 1, a battery 101 powered selective call receiver 100 operates to receive a signal via an antenna 102. A receiver 103 couples a received signal to a demodulator 104, which recovers any information present using conventional techniques. The recovered information is coupled to a controller 105 that interprets and decodes the recovered information. In the preferred embodiment, the controller 105 may comprise a microprocessor having a signal processor (decoder) implemented in both hardware and software.

In a manner that is well known in the art, the recovered information is checked by the decoder, which implements the signal processor that correlates a recovered address with a predetermined address stored in the selective call receiver's 100 non-volatile memory or code plug 107. The non-volatile memory 107 typically has a plurality of registers for storing a plurality of configuration words that characterize the operation of the selective call receiver. In determining the selection of the selective call receiver, a correlation is performed between a predetermined address associated with the selective call receiver and a received address. When the addresses correlate, the controller 105 couples message information to the message memory 106. In accordance with the recovered information, and settings associated with the user controls 109, the selective call receiver includes a presentation means, such as a display 110, that presents at least a portion of the message information, and signals the user via an audible or tactile alert 111 that a message has been received. The user may view the information presented on the display 110 by activating the appropriate controls 109. The support circuit 108 preferably comprises a conventional signal multiplexing integrated circuit, a voltage regulator and control mechanism, a current regulator and control mechanism, environmental sensing circuitry such as for light or temperature conditions, audio power amplifier circuitry, control interface circuitry, and display illumination circuitry. These elements are arranged in a known manner to provide the information display receiver as requested by the customer. Referring to FIG. 2, the block diagram shows a varactor tuned selective call receiver using a liquid crystal display voltage supply as a varactor bias source in accordance with a first embodiment of the present invention. As discussed in reference to FIG. 1, the selective call receiver 200 operates to receive a signal on a receiving frequency via an antenna 201. In this embodiment, the antenna 201 is matched to a radio frequency (RF) amplifier 202 via a reactive matching network 203. The reactive matching network 203 is actively tuned to the receiving frequency by a frequency determining element (varactor diode) 204 that has a capacitance value determined at least in part by the bias voltage supplied by the D/A bias generator 205. By changing the bias presented to the varactor diode 204 in response to varactor frequency control information, the frequency response of the matching network 203 is adjusted for optimal performance of the RF receiver. In an exemplary implementation of the present invention, the bias required for a desired matching network 203 frequency response may be pre-programmed, as predetermined varactor frequency control information, in a non-volatile memory component or code plug (not shown) associated with a micro-computer 206.

The receiver 207 is controlled by and exchanges information with the micro-computer 206. When a message is received and decoded by the micro-computer 206, it operates to present the message by coupling information to a display driver logic section 208 that encodes the information into displayable symbols such as characters or numbers. The message is then presented on the display 209. In this embodiment, the display 209 is preferably a liquid crystal display (LCD) having a plurality of display elements, each being separately addressable via the display driver logic 5 section 208. Conventional LCD's of this type typically require a supply voltage of approximately 3.1 volts. Alternatively, the display section could have been implemented using a display technology such as light emitting diodes, an electroluminescent display panel, or

10 possibly even a cathode ray tube. Note that the LCD supply voltage generator 210 supplies power (a second voltage 211) to both the LCD 209 and a programmable bias generator 205. The power (third voltage 212) for the varactor diode 204 is generated by the programmable bias generator 205.

15 Furthermore, the micro-computer 206 couples a divider control signal 213 to the LCD supply voltage generator-210 for controlling a clock signal (not shown) having a fundamental frequency, the clock signal being used to operate a voltage multiplier (not shown) associated with

20 the LCD supply voltage generator 210. This allows the micro-computer 206 to alter the fundamental frequency of the clock signal in order to prevent interference caused by spurious radiated or conducted electromagnetic emissions associated with the clock signal.

25 Referring to FIG. 3, the illustration shows a prior art liquid crystal display supply voltage generator. The supply voltage generator shown here approximately doubles the voltage (first voltage) of the battery 301. A resistor- capacitor (RC) oscillator 302 having a nominal operating

1 _,„ _^ approximately . ,r—— generates a clock signal

30 frequency of ^ ^J 2πYRC _f coupled to a capacitive voltage doubler. One of the problems experienced with this prior art arrangement is that the resistor and capacitor values change over time because of component aging. Moreover, the frequency 35 stability performance of this topology over temperature requires that the resistor and capacitor have equal and opposite or zero (not practical) temperature coefficients to maintain an exact frequency of oscillation. Other factors such as the initial part tolerances on real parts effect frequency performance by offsetting the nominal frequency of oscillation. These factors contribute to the overall uncertainty of the frequency of oscillation of the (RC) oscillator 302. If the nominal frequency of oscillation in this configuration happens to fall on a frequency, that when conducted or radiated into a component of the receiver, mixes with another signal producing an on- channel response, or by itself is a sub-multiple or exact frequency to which the receiver is responsive, the receiver will exhibit a phenomena known as "self-quieting." Self- quieting occurs when an undesired on-channel response is produced by one or more signal sources located in the receiver system. The response can be caused by first order effects (e.g., a signal falling at the receiver's carrier frequency) or by higher order effects due to mixing in components residing in the receiver's amplification and filtering paths. Another problem that may occur is receiver desense. If one takes into account all unwanted signal sources within the receiver's environment, an unwanted response to these is known in the art as "desense." Desense is when the radio receiver is "de¬ sensitized" (degrades in sensitivity) due to an interfering signal that causes the desired signal to be distorted to the point where it can no longer be successfully recovered.

To operate the voltage multiplier 300, the clock signal 312 is coupled from the output of the RC oscillator 302 to inverter 303 and transistors 304, 305, and 306 (switching means) . When the clock signal 312 is high

(logic 1) , transistors 305 and 306 are off, and transistors

304 and 307 are on. This allows charge to flow from the battery 301 through transistor 307 to charge capacitor 308 up to a first voltage approximately equal to the potential of the battery 301. When the clock signal 312 goes low

(logic 0),- transistors 304 and 307 turn off and transistors

305 and 306 turn on, thereby connecting the previously charged capacitor 308 in series with the battery 301 and coupling the resulting charge and potential of approximately two times the battery voltage to capacitor 309 for storage as a second voltage. This cycle is repeated continuously during operation of the voltage generator, thereby supplying a doubled voltage to operate the LCD and its related components. Once the second voltage is present, the LCD driver logic 310 can operate the LCD display to present information.

Referring to FIG. 4, the block diagram shows a frequency controlled liquid crystal display supply voltage generator in accordance with a second embodiment of the present invention. The frequency controlled LCD supply voltage generator 400 comprises a reference clock 404 having a reference frequency, a programmable divider 403 that generates a clock signal 406 having a fundamental frequency, and a voltage multiplier 405. A micro-computer 401 accesses predetermined fundamental frequency control information from a non-volatile memory device 402 (e.g., a code plug) and generates a divider control signal 407 that is coupled from the micro-computer 401 to the programmable divider. The predetermined fundamental frequency control information is determined such that a response will not be generated on a receiving frequency of the selective call receiver due to the fundamental frequency, a harmonic of the fundamental frequency, or any mixing products thereof. The receiving frequency in this case is to be interpreted as any frequency that the selective call receiver is responsive to. The programmable divider 403 produces the clock signal 410 from the reference clock 404 by dividing the reference clock signal 406. The clock signal 410 is then coupled to the voltage multiplier 405 to allow generation of the second supply voltage 408 from the first supply voltage 409.

To illustrate a possible method for selecting the fundamental frequency, the following example is presented. An exemplary selective call receiver uses the reference clock 404 with a reference frequency fi of 32,768 Hz. The programmable divider 403 creates a clock signal from the reference clock, the clock signal having a fundamental frequency ±₂ of 16,384 Hz. The selective call receiver has a carrier frequency fc of 153.5 MHz with a first intermediate f equency IFI of 17.9 MHz and a second intermediate frequency fi_F2 of 455 KHz. This exemplary selective call receiver is responsive to signals that fall within a band approximately ±2 KHz from the carrier and intermediate frequencies. The exemplary receiver uses low- side injection for its first mixer, yielding a first oscillator fundamental frequency fo of 45.2 MHz and a first mixer injection frequency fin_jl of 135.6 MHz. The second mixer utilizes high side injection yielding a second mixer injection frequency f±n_j2 of 18.355 MHz. A set of equations representing the possible responses for this exemplary receiver can be expressed as:

flFl = ±Nlfl ±N₂f₂ ±N₃fθ ± ₄finj2

f_IF2 = ±Nifi ± ₂f2 ±N3 θ ±N finj2

where Ni, N₂, N3, and N₄ are integers with a range of 0, 1, 2, 3, ... , infinity that are independently iterated through all possible permutations and combinations. By inspection, one of ordinary skill in the art can determine that in order to prevent an on-channel response, the variable oscillator frequency f₂ must be chosen such that the solution to either equation does not fall within ±2 KHz of either the first or second intermediate frequencies. The ±2 KHz window of response used here is dependant on the receiver's bandwidth and could be wider or narrower depending on the receiving system's topology. Moreover, the situation illustrated covers only a dual-conversion receiver having two additional signal sources. This concept can be extended to any receiver configuration and any number of signal sources.

Referring to FIG. 5, the illustration shows a frequency controlled liquid crystal display supply voltage generator and varactor voltage power supply in accordance with the first embodiment of the present invention. As in FIG. 3, a battery 500 supplies power for a capacitive voltage multiplier 300. The capacitive voltage multiplier 300 operates identically to the voltage multiplier discussed in reference to FIG. 3. In this embodiment, a frequency divider 501 produces a clock signal from a reference clock signal in response to a divider control signal. The micro-computer (not shown) determines the frequency of the clock signal by retrieving predetermined fundamental frequency control information from a non¬ volatile memory device (not shown) and generating the divider control signal 505 that programs the frequency divider. The first voltage 506 (or battery voltage) is in this embodiment is multiplied to a second voltage 507 for ^' powering the LCD driver logic 502 and the LCD display 503. A third supply voltage 508 is then generated from the second voltage 507 by a conventional digital to analog converter 504 in response to a voltage control signal 509 coupled from the micro-computer (not shown) .and determined by varactor frequency control information. The varactor frequency control information itself may be predetermined (e.g., pre-programmed in a memory device) or generated using hardware or software means such as is well known in the art of electronic filters and synthesizers. The third supply voltage 508 is selected by the voltage control signal 509 coupled from the micro-computer, and can be used to program the center frequency of a voltage controlled oscillator, filter, or the like.

The examples shown in FIG. 3 and FIG. 5 use a doubler circuit for illustration purposes only. One of ordinary skill in the art will recognize that an infinite number of voltage multiplier topologies can be used to implement the instant invention. It can also be recognized that the clock signal and oscillator frequencies were selected for illustrative purposes only, and other frequencies can be used.

Claims

1. A selective call receiver capable of receiving an energy source having a first supply voltage, comprising: first means for generating a second supply voltage from the energy source, the second supply voltage being used to power at least an information display; and second means for generating a third supply voltage from the second supply voltage, the third supply voltage being used to power at least one frequency determining element.

2. The selective call receiver according to claim 1 wherein the first means comprises: a voltage multiplier.

3. The selective call receiver according to claim 2 wherein the voltage multiplier comprises: means for generating a clock signal having a fundamental frequency; and switching means responsive to the clock signal for coupling the first supply voltage to a charge storage element that sustains the second supply voltage.

4. The selective call receiver according to claim 3 wherein the charge storage element is a capacitor.

5. The selective call receiver according to claim 3 wherein the means for generating a clock signal comprises: a reference clock for generating a reference clock signal; and a divider for producing the clock signal from the reference clock signal by dividing the reference clock signal in response to a divider control signal. 6. The selective call receiver according to claim 5 wherein the means for generating a clock signal further comprises: controller means for generating the divider control signal in response to predetermined fundamental frequency control information from a memory coupled to the controller means, the predetermined fundamental frequency control

10. The method according to claim 9 wherein step (a) comprises the steps of: generating a clock signal having a fundamental frequency; and coupling the first supply voltage to a charge storage element in response to the clock signal.

11. The method according to claim 10 further comprising the step of: generating the divider control signal in response to predetermined fundamental frequency control information from a memory, the predetermined fundamental frequency control information being determined such that a response will not be generated on a receiving frequency of the selective call receiver due to the fundamental frequency, a harmonic of the fundamental frequency, or any mixing products thereof.

12. The method according to claim 11 further comprising the step of: producing the clock signal from a reference clock signal by dividing the reference clock signal in response to the divider control signal.

13. The method according to claim 9 wherein step (b) comprises the step of: generating a voltage control signal in response to predetermined varactor frequency control information.

14. The method according to claim 13 further comprising the step of: selecting the third supply voltage in response to the voltage control signal.