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Data processing system having units competing for access to shared resources and arbitration unit responsive to the status of the shared resources

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Publication number
EP0581335B1
EP0581335B1 EP19930116232 EP93116232A EP0581335B1 EP 0581335 B1 EP0581335 B1 EP 0581335B1 EP 19930116232 EP19930116232 EP 19930116232 EP 93116232 A EP93116232 A EP 93116232A EP 0581335 B1 EP0581335 B1 EP 0581335B1
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Prior art keywords
bus
local
block
system
unit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP19930116232
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German (de)
French (fr)
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EP0581335A2 (en )
EP0581335A3 (en )
Inventor
Carlo Bagnoli
Tommaso Majo
Guido Perrella
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Bull HN Information Systems Italia SpA
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Bull HN Information Systems Italia SpA
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/161Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • G06F15/167Interprocessor communication using a common memory, e.g. mailbox

Description

The present invention is a divisional of EP-A-0387644 and relates to a data processing system where a plurality of requesting units or "masters" compete for access to shared resources through a communication bus by means of access request signals sent to an arbitration unit and identifying a resource as requested to perform an operation.

The arbitration unit then grants access to the one of the requesting units having higher priority, among the competing ones, taking in account the status of the requested resource which must be available to perform the requested operation.

Us-A-4,669,079 discloses a method and apparatus for bus arbitration in a data processing system which uses the same concept but requires that each resource give information, with a signal sent to the arbitration unit, about its busy/free state, e.g. about its availability to perform some operation.

Moreover the arbitration unit must receive a bus busy signal asserted by the requesting unit which has obtained access to the bus.

Differently fron this approach and according to the present invention, at least some of the grant signals generated by the arbitration unit have both the meaning of grant signal and the meaning of bus busy state and are used by the same arbitration unit generating them as a condition for a subsequent arbitration, so that the bus busy signal is not required.

Moreover the busy/free state of at least some of the resources is determined by the arbitration unit based on previously granted access and does not require the cheching of their status through signals received from such resources.

The resulting advantages in terms of simplification and performances are readily apparent to the persons skilled in the art.

The features and the advantages of the present invention will appear more clearly, as a preferred but not necessary environment, from the following description of a multiprocessor system having distributed shared resources, as disclosed in EP-A-0387644, from which the present invention has been divided, and from the enclosed drawings where:

  • Figure 1 is a block diagram of a multiprocessor system in accordance with the present invention.
  • Figure 2 is a block diagram of an interface block between processor and local bus for the system of Fig. 1.
  • Figure 3 is a block diagram of an interface block between local bus and local memory in the system of Fig. 1.
  • Figure 4 is a block diagram of an interface block for having access to system bus from local bus in the system of Fig. 1.
  • Figure 5 is a block diagram of a bypass block for having access to local bus from system bus in the system of Fig. 1.
  • Figure 6 is a block diagram of an arbitration unit for arbitrating access to local bus in the system of Fig. 1.
Figure 1 shows in block diagram a multiprocessor system in accordance with the present invention; it is defined in claim 1 of the appended claims.

The system comprises a plurality (for instance four) of central processing units or CPU 1,...4.

The units are identical to each other in the architectural details which are shown with reference to CPU 1 only.

The several CPUs communicate with each other through a system bus (SB) 5.

In addition to the several CPUs, shared memories and input/output controllers, not shown, may be connected to the system bus 5.

A timing unit 6 provides timing signals required for operation of the system.

CPU1 comprises a processing unit 7 or microprocessor MP1, a local memory 8 (LM1) and an interface and arbitration unit 10 (INT & ARB) of the system bus.

Units 7,8,10 communicate to each other through a local bus 11.

More precisely, MP1 7 communicates with the local bus 11 through a control and isolation block 12 and the interface unit 10 communicates with the local bus 11 through a buffer output unit 9 or SBOUT and through an input block 40 or SBIN.

Access to local bus 11 from the several units is controlled by a control and arbitration block 13 or ARBT.

The interface unit 10 enables to connect system bus 5 to local bus 11, through block 40 when the request of access to local bus comes from the system bus, through block 9 when the requests of access to system bus comes from the local bus.

Interface unit 10 arbitrates control over the system bus together with the corresponding interface units of the other CPUs.

The units connected to the local bus are of two kinds: "masters", which can request and obtain access to the local bus, and "slaves" which are selected or referenced on master request.

Typically unit MP1 and the system bus as seen through unit 10 and block 40 are "master" units.

Local memory 8, and system bus, as seen through blocks 9 and 10 are "slave" units.

However, for the purpose of getting access to local bus, memory 8 and system bus may take the "master" role for performing the reply phase or reconnect operation required by read operations.

With the above summarized architecture any deadlock problem is avoided.

In fact, if MP1 obtains access to the local bus (by arbitration unit 13) block 12 is enabled and MP1 may perform an information transfer by selecting either local memory 8 or block 9.

In the second alternative block 9 acts as a buffer for transfer requests which select some resource external to CPU1, for instance local memory LM4 of CPU4, through system bus 5.

In this case, block 9 transfers to unit 10 a system bus access request.

If the access request is for a write operation through the system bus the address where to write, the datum to be written and the related write command are loaded in buffer 9.

In this way processor MP1 and block 12 may release the local bus.

It is a task of block 9 to start the interface unit 10 which provides to obtain, through a suitable arbitration protocol, the system bus so as to execute the write operation so posted.

If the access request is for a read operation through system bus, the address where to read and the related read command are loaded in buffer 9.

Block 12 may release the local bus while processor 7 waits for the requested data.

It is a task of block 9 to start interface unit 10 which provides to obtain, with the required arbitration, the system bus to perform the read operation already posted.

In both cases, if the interface unit 10 has been meanwhile selected, through signals present on the system bus, as a receiving unit, to write a datum present on system bus in local memory 8 of CPU1, or to read in the same local memory a datum to be transferred on the system bus, unit 10 temporarily neglects the request pending in buffer 9 and may start block SBIN 40.

The information related to the access cycle requested by system bus SB is stored in block 40.

Block 40, in turn, may request and obtain access to local bus 11 from arbiter 13 and therefore it may complete the access to local memory 8.

Once the information has been stored or the read request has been posted, the local bus 11 is released.

In case of write operation the system bus 5 is released too, whilst in case of read request it is released only once the requested information has been read out and transferred on SB5.

The release is performed by the interface unit of the CPU acting as "agent".

Once SB5 has been released, interface unit 10 may request access to system bus 5 with an arbitration protocol.

When access is granted, it may perform the transfer on the bus of the read/write message pending in buffer 9.

Once the operation has been performed, if a write, the system bus SB5 is released. In case of a read, the read out data is transferred through SB5 and interface unit 10 to block 9 which requests access to local bus.

Arbitrator 13, taking in account the established priorities and for a predetermined time interval, sends an access granting signal to block 9.

The same signal, received by block 12, which has stored therein a condition of wait for data received from system bus, enables block 12 to detect that the data is available.

Block 12 signals the event to processor 7 which can receive the data.

The communication process is therefore concluded without deadlock.

It may be noted that, whilst for read operations performed by a CPU in the local memory of another CPU, a process is used which consists in the "posting" of th read command, followed by a reconnect phase for receiving the read data, in case of a write operation the used process consists in the "posting" phase only. However it would be possible to use the posting and reconnect process even in case of a write, to give the agent processor a means for receiving error signals (data transfer error, unexisting or protected memory location selection) in the course of the same write operation.

It is clear that during the time in which processor MP1 is disconnected from local bus and the transfer process on the system bus is still active or pending in block 9, the local bus may be used for other purposes, not only for deadlock prevention. For instance, once a write has been posted, processor MP1 may proceed by performing other operations which require the use of the local bus such as access to local memory or to local resources, not shown, without need to wait for conclusion of the operation on the system bus.

If the posted operation is a read, MP1, waiting for the data, cannot have access to the local bus for other purposes, but other "masters" not shown, for instance a direct memory access unit DMA, can have access to local bus for references to local "slave" unit other than block 9 (in case block 9 too may be referenced for a write posting).

It is therefore clear that the overall operative speed of the system may be increased because the use of the local bus is no more constrained by operations running on the system bus.

It is further clear that even if not required for resolution of deadlock but of advantage for a more efficient use of the local bus, the local memory may be provided with a buffer similar to block 12, so that read operations requested to local memory can be performed with a process of selection (or posting) and reconnection.

For this reason, in local memory 8 of Fig. 1 an interface block 8A is shown which is intended to have this function.

Generalization of the communication concept between master and slave, based on the posting and reconnect process, makes possible the execution of the two phases in very short time intervals of local bus occupation, if the buffers of the destination resources are available.

A further advantage in the efficient use of the local bus is therefore achieved by providing local bus arbitrator which grants access to a requestor non only by resolving conflicts among competing masters, in compliance with predetermined priorities, but also in dependance of the availability of the destination units to perform the particular type of requested operation.

In a preferred embodiment of the system of Fig. 1 the several processors, such as MP1 may consist in the integrated circuit 68030 of the US firm MOTOROLA. The "user manual" of such product, published in 1987, provides all the information required for the use and operation understanding of the component.

The interface unit 10 is preferably an integrated circuit component MPC "message passing coprocessor" manufactured by the firm INTEL and described in the manual "MPC user manual" published in 1986.

This component enables to handle the communication protocol and to arbitrate access requests to a system bus known as MULTIBUS II defined by the international standard "High Performance Synchronous 32 bit BUS Standard" published by IEEE on 29.05.1987.

This document is referenced for detailed information relating to the communication protocol and features of such bus.

Figure 2 shows in block diagram a preferred embodiment of interface block 12, which, in the previously described contexts is particularly simple, and essentially consists in a set of transmitter/receivers or "tranceivers" 14, a set of tristate gates 15 and a combinatorial network or decoder 16.

On the upper side of block 12 there are shown the leads/signals which interface with MP1.

On the lower side of block 12 the signals/leads used by the local bus are shown.

The bidirectional data path DBUS of MP1 is connected to a data channel LBD of local bus through the set of "transceivers" 14.

The address channel ABUS of MP1 is connected to an address channel LBA of local bus 11 through the set of gates 15.

Block 12 receives further from MP1 a signal AS which, when asserted, validates addresses, data and commands issued by MP1, and a signal R/W which defines, with its logical level, the nature of the operation requested bu MP1, as a write (R/W deasserted) or read (R/W asserted).

Block 12 sends to MP1 a signal STERM having a predetermined phase relationship as to a clock signal CK used for timing the MP1 operation.

When asserted STERM indicates that the operation requested by MP1 may be completed.

In case of a read it further indicates that the requested data are or will be available within the next occurrence of the CK clock.

Block 12 receives, from the arbitration unit 13 and through the local bus, a signal ENCPU which enables it to have access to the local bus.

It further receives two signals ENRLM and ENRSB respectively indicating that local memory or system bus are enabled to reconnect themselves to the local bus for providing a read out data to the requesting "master" unit.

Through the local bus, three other signals are received by block 12: LMBSY, LMRPG (issued by block 8A) and SBBSY (issued by block 9).

When asserted, signals LMBSY and SBBSY indicates that the related blocks are busy and cannot accept any new request.

Signal LMRPG asserted indicates that although block 8A has started a read operation (that is it has transferred commands and addresses), the read operation is still pending.

The following signals are put by block 12 on local bus 11 for distribution to the several units 8A,13,9:

  • LBR/W (equivalent for R/W) which defines the requested operation as a read or a write. LBR/W is controlled by one of the gates in set 15.
  • MPLM which selects the local memory as a "slave" or destination unit.
  • MPSB which selects the system bus (through block 9) as a slave referenced by the command.

Decoding network 16 combines the several signals in input to block 12 to generate the output signals and internal signals for controlling the gates 14 and 15.

The timing of the produced signals depends on the timing of the signals received from outside.

More than any detailed circuit description, the operation and the implementation of block 12 is better described by the following logical equations, where the letter N preceding the name of the signals indicates, here and in the following, the symbol of logical inversion or negation. MPLM=An.AS.ENCPU.NLMBSY.NR/W + An.AS.ENCPU.R/W.NLMRPG.NLMBSY

This equation substantially indicates that signal MPLM, which from local bus controls the selection of the local memory, is asserted if a bit An (or more bits) of an address references the local memory as a destination unit for the command, if such bit An is validated by AS, if processor MP is enabled to get access to the local bus by arbitrator 13 (ENCPU asserted) and if the local memory is not already busy (LMBSY deasserted in case of write and LMRPG deasserted in case of read).

The distinct treatment of the read and write commands is explained considering that a write command from MP1 may be "posted" in the local memory interface 8A even if the local memory is running a read operation previously requested by another master.

Once the write command has been posted, the processor MP is free to proceed with the execution of other operation.

On the contrary, in case of a read command, the processor MP must any how wait for the read out data. Therefore it is preferable to postpone the read command untill it can be effectively executed.

Moreover, overlapping of local memory read commands issued by differing requesting units is prevented, which would make difficult the identification of the units to which the data is directed when it becomes available.

MPLM is deasserted when the command is accepted by the local memory interface unit 8A.

At that time unit 8A is set busy and LMBSY becomes asserted.

MPLM enables the tranceivers 14 and the gates 15 towards the local bus.

In similar manner, but without distinction between read and write operations, the command which selects block 9 for having access to the system bus and for enabling tranceivers 12 and gates 15 towards the local bus, is expressed by the following equation: MPSB=Am.AS.ENCPU.NSBBSY where Am is a bit (or more bits) of an address which references the system bus as a destination space (external space) for the command.

Signal STERM in case of a write operation is expressed by the following equation: STERM=MPLM.NR/W+MPSB.NR/W or preferably and only for reason of operative speed by: STERM=An.ENCPU.NLMBSY.NR/W + Am.ENCPU.NSBBSY.NR/W

In case of a read operation: STERM=R/W.An.AS.ENRLM.POST + R/W.Am.AS.ENRSB.POST where POST is signal internal to block 12.
POST is generated according to the following equation: POST=MPLM.R/W + MPSB.R/W + POST.NAS

In other words, based on the address output by MP, the block 12, once having sent the read command (POST asserted), detects if the reconnection performed by arbiter 13 is intended for itself or for another destination unit.

The transceivers 14 may be enabled to receive data from local bus and towards MP by command R/W asserted.

Figure 3 shows in block diagram the interface block 8A of local memory.

Block 8A comprises a memory input data register 17, a memory output data register 18, having tristate outputs, an address and command register 19 and a finite states logic 20.

The signals exchanged with the local bus are shown on the lower side of block 8A.

They are LBD (data), LBA (addresses), LBR/W (read/write command), MPLM (selection comand generated by processor MP1), SBLM (selection command generated by block 40 for access to local memory from system bus, LMBSY (output signal to indicate that block 8A is already busy), LMRPG (output signal indicating that a read operation is pending), LMRQ (output signal indicating that local memory requires a reconnection to local bus) and ENRLM (command which enable reconnection of local memory and which is generated by arbitration unit 13).

The signals exchanged between block 8A and local memory are shown on the upper side of block 8A.

They typically are: DI/O (input/output data) AD (addresses), MR/W (read/write command)

DRDY (data ready signal), MST (memory start signal), MBSY (memory cycle running and memory busy signal).

Block 8A receives further a periodic timing signal CK from unit 6 (figure 1).

The loading of registers 17,19 is performed by the following command: LD=CK.MPLM + CK.SBLM

MPLM and SBLM are asserted if block 8A is ready to receive commands, that is if LMBSY is deasserted, and if the related master has received access to local bus.

Register 18 is loaded, owing to command DRDY, with the data read out from memory.

The outputs of register 18 are enabled by ENRLM.

Signal LMBSY is given by the following equation: LMBSY= MPLM.CK + SBLM.CK + LMBSY.N(MST.CK)

In other words LMBSY is asserted when the read/write command is loaded and is self sustaining until the joint presence of CK and MST removes self sustainance.

The memory start signal MST is given by: MST = LMBSY.NMBSY

It is asserted (if an operation has been posted in block 8A and therefore LMBSY is asserted) as soon as the memory becomes free

Signal LMRPG is given by the following equation: LMRPG= MPLM.CK.LBR/W + SBLM.CK.LBR/W + LMRPG.NENRLM

In other words it is asserted when a read command is sent to block 8A and is self sustaining until block 8A is enabled to reconnect to local bus by signal ENRLM asserted.

LMRQ is given by the following self explaining equation: LMRQ= DRDY + LMRQ.NENRLM

Figure 4 shows in schematics the interface and arbitration unit 10, block 9 and the interconnections of the two units between each other and with the local bus on one side and the system bus on the other.

Block 9 exchanges with local bus 11 data LBD, receives addresses LBA and signal LBR/W.

It further receives selection command MPSB from block 12, reconnection signal ENRSB from arbitrator 13 and forwards signals SBRQ (to arbitrator 13 for reconnection to local bus) and SBBSY (both to arbitrator 13 and to block 12.

It receives further timing signal CK from unit 6 (Fig. 1).

Block 9 exchanges with unit 10 the following signals: data (DSBUS), addresses (ASBUS) a signal MEMSEL (which characterizes the operation to be performed), two distinct commands for starting a read operation (R) or write operation (W).

Block 9 receives from unit 10 a signal WAIT (indicating that the requested operation is running) and a signal REFADDR which enables an address register to transfer the address stored therein to the system bus.

WAIT signal is deasserted immediately before data availability on the system bus.

The above mentioned signals are the only one required in the case, considered here, that unit 10 consists in coprocessor MPC of the INTEL firm.

Unit 10 comprises, in addition to coprocessor MPC 21 a set of control gates 22 which connect the coprocessor to the system bus. They are controlled by the coprocessor.

Coprocessor 21 comprises two registers 23,24 for latching the data (DS BUS) exchanged with block 9 and, once triggered by assertion of MEMSEL signal, manages in autonomous way the arbitration of the system bus and its communication protocol.

Block 9 essentially comprises a set of tranceivers 27 for isolation of local data bus LBD from system data bus DSBUS, a register 25 for latching an address and a finite state logic 26 for generating control signals as a function of the signals received as input.

The control signals satisfy the following equations: MEMSEL = MPSB W = NLBR/W.MPSB.CK + W.SBBSY R = LBR/W.MPSB.CK + R.SBBSY SBBSY = MPSB.CK + SBBSY.NREFADDR + SBBSY.WAIT SBRPG = R.REFADDR + SBRPG.NENRSB SBRQ = SBRPG.NWAIT

These equations are imposed by the timing requirements of the MPC coprocessor.

MEMSEL must be asserted before the R or W command.

R or W command must remain asserted at least until deassertion of WAIT signal. The last is asserted with a certain delay as to when MEMSEL is received by coprocessor.

Therefore two self sustainance terms for SBBSY are required.

SBRPG is an internal auxiliary signal used for generation of SBRQ.

Gates 27 are enabled for transfer towards MPC21 by a signal EN1=MPSB and for transfer towards local bus by signal EN2=ENRSB.

Register 25 is loaded by a command LD=MPSB.CK and its outputs are enabled by signal REFADDR which is generated by MPC21 with a timing required by the interface protocol of the system bus.

Figure 5 shows in block diagram the interface unit 10, the block 40 (SBIN) and the interconnections of the two units each to the other and with the local bus on one side and the system bus on the other.

As already said the interface unit 10 comprises the coprocessor 21 and the set of transceivers 22.

Through these transceivers, the system bus, or better the leads of the system bus intended for transferring data, addresses, commands, are connected to both block 10 and block 40.

They provide a path 28 for by passing inteface unit 10.

Block 40 essentially comprises a buffer register 29 for storing addresses and commands received from bypass 28, and address and command register 30, cascaded to the first one, a data register 31 for data which from bypass 28 must be directed to the local bus, a data register 32 for data with from the local bus must be directed to the bypass 28 and a finite state logic 33 for generation of control signals as a function of the signals received from local bus and unit 10.

It is known that coprocessor 21 continuously monitors the signals present on the system bus and is able to distinguish among the several phases of arbitration, command, data transfer, occurring on the system bus.

It is further capable of detecting address fields which make reference to it as interface of a destination space.

When this happens, coprocessor MPC asserts a selection signal SEL towards block 40.

SEL remains asserted until the "handshaking" procedure on the system bus is completed, that is until certains signals on the system bus, which are referenced in the MULTIBUS specification as BSC2,BSC2,BSC4, are asserted.

Coprocessor 21 receives a signal COM from block 40.

COM indicates that block 40 is ready to complete the requested operation.

The following information is exchanged between block 40 and local bus:

  • Data LBI in output from register 31 or input to register 32,
  • Addresses in output from register 30 towards local bus,
  • Control signals LBR/W, SBINLM, SBR/W towards local bus and control signals ENSB, ENRLM from local bus.

Block 40 further receives a periodical timing signal CK1 (in addition to CK) from unit 6. CK1 is a timing signal which is used for timing the operation of the system bus.

Register 29 may be considered as a "freezing" register for keeping track of a transient status which occurs on the system bus, that is the command phase.

During the command phase, characterized by the assertion o a signal BSCO on the system bus, addresses and commands are present on the system bus.

The load command for register 29 is therefore LD3=BSCO.CK1 and the information latched in register 29 is held untill a new assertion of BSCO.

Register 30,31 are loaded by a control signal LD4 given by the following equation. LD4= SEL.NBSY.NSEL1

In other words if coprocessor 21 recognizes an address present on the system bus as an owned destination space, it asserts SEL.

This occurs when the address is no more present on the system bus, the information to be written being instead present in case of a write operation.

Therefore on assertion of SEL register 30 is loaded with the address and commands already stored in register 29 and register 31 is loaded with the data which may be present on the system bus.

The load operation is performed only if the two internal signals BSY and SEL1 are deasserted.

BSY indicates that register 30 and 31 are busy and is defined by the equation: BSY = LD4 + BSY.ENSB.CK

BSY is asserted with LD4 and is self sustained until command ENSB connection command to local bus, synchronized with the local bus clock, is received by unit 40.

SEL1 is an auxiliary signal defined by the following equation: SEL1 = ENSB + SEL1.N(NSEL.CK1) SEL1 is asserted when the command ENSB for connection of block 40 to local bus is received.

SEL1 self sustains until the occurrence of the first clock CK1 of system bus, next following deassertion of SEL signal.

In the equation which defines LD4, the term NSEL1 guarantees that after the first loading of registers 30,31 their state is not changed until signal SEL is effectively deasserted, even if signal BSY is deasserted.

Signal SBINLM by which block 40 requests access to local bus is defined by equation: SBINLM=BSY

Signal SBR/W is given by SBR/W=BSC6, where BSC6 is a control signal appearing on system bus in the command phase and latched in register 29.

When asserted, BSC6 identifies the requested operation as a write.

Signal SBR/W is used in block 40 to "remember" when the requested operation is for a read and therefore data read out from local memory have to be received in the reconnect phase.

SBR/W is further sent to arbitrator 13, which prevents block 40 from having access to local memory if a read operation is pending.

Signal COM is defined by the following equation: COM= SBINLM.NSBR/W + ENRLM.SBR/W.SEL1 + COM.SEL1

It is asserted with the access request to local bus in case of a write and wit the command for reconnection of local memory (detected as of pertinence if SEL1 is asserted) in case of a read.

COM is self sustaining until SEL1 is deasserted.

In case of a write operation COM signals to coprocessor MPC that the interface protocol may be concluded.

In case of a read operation COM signals that the read out data is available.

Coprocessor MPC controls gates 22 for the transfer of the read out data, from register 32 (where it has been loaded by a command LD5 = ENRLM.SBR/W.CK) to the system bus, through the bypass 28.

It further provides to complete the interface protocol on the system bus.

The outputs of register 32 are enabled by a control signal SEL.BSC6.

The outputs of registers 30,31 are enabled by signal ENSB.

Figure 6 shows the signals in input to and output from arbitration unit 13.

Arbitration unit 13 may be implemented in several ways: a preferred embodiment with PLA (Programmable Logic Array) is for instance described in the EP-A-0274648.

Even in this case, more than a circuital embodiment, the operation and implementation of arbitrator 13 is better described by the logical equations which define the output signals as a function of the input signals.

Basically arbitrator 13 receives local bus access requests from the several units, samples the several requests concurrently present at the occurrence of a clock signal CK and depending on the priority assigned to each requesting unit, it generates a signal which grants access to the more prioritary unit.
A preferred priority order in servicing access requests is for instance (with decreasing priority):

  • Local Memory request for reconnection (in order to provide the read out data)
  • Block 9 (system bus) for reconnection
  • Block 40 for access to local memory from system bus
  • Block 12 (that is MP1) for access to local memory or system bus.
Having MP1 the lowest priority, access to local bus is granted to MP1 "by default", that is missing any request of higher priority and if the local bus is available signal ENCPU is always generated.

To prevent arbitrator 13 from removing the local bus access right granted to MP1 when MP1 is performing some operation on the local bus, block 12 signals, by means of MPLM,MPSB, that an operation is currently in execution.

An original feature of arbitrator 13 is that the units requesting access to the local bus identify the type of requested resource and the operation to be performed.

Thus for instance, system bus interface block 40 indicates that the requested resource is the local memory (SBINLM). In addition it indicates if the operation is a read one or a write one (SBR/W).

The arbitrator 13 grants access to local bus not only as a function of the assigned priorities, but also as a function of the requested resource status.

In other words, if the destination resource is busy and cannot perform the particular kind of requested operation, the access request is masked and a lower priority request, which however designates an available resource, is enabled to prevail.

Because of the mechanism of "posted write" and read operation performed with command posting and subsequent reconnect, if the destination resource is available, each phase of local bus allocation to a requesting unit requires two only cycles of the timing signal (the cycle which precedes the clock signal CK by which the operation is posted in a destination register and the immediately following cycle).

Therefore the local bus is efficiently used.

Several access operation to available resources may be performed in the time required to a resource for becoming available and the local bus is not kept busy by a more prioritary unit waiting for the becoming available of a destination unit.

The same rule is followed by block 12 as beneficiary of local bus access by default.

Even if local bus is available (ENCPU asserted) block 12 before asserting MPSB or MPLM checks that the destination unit is available (SBBSY or LMBSY deasserted).

In case of a read request to local memory, it further checks that a read operation is not already running (LMRPG deasserted).

Having pointed out the previous concepts the following logical equations which describe the operation of arbitration unit 13 are self explanatory: ENRLM = LMRQ.CK.NMPSB.NMPLM.NENRSB.NENSB + ENRLM.N(NLMRQ.CK) ENRSB= SBRQ.CK.NMLMRQ.NMPLM.NMPSB.NENRLM.NENSB + ENRSB.N(NSBRQ.CK) ENSB= SBINLM.CK.NLMRQ.NSBRQ.NMPSB.NMPLM.NENRSB.NENRLM.NLMBSY.NSBR/W + + ENSB.N(NSBINLM.CK) (in case of write) ENSB= SBINLM.CK.NLMRQ.NSBRQ.NMPSB.NMPLM.NENRSB.NENRLM.NLMRPG.SBR/W.NLMBSY + + ENSB.N(NSBINLM.CK)(in case of read) ENCPU=NENRLM.NENRSB.NSBLM

As already said the several logic functions described by the previous equations may be performed by logical networks implemented with components available on the market, such as AND,OR,INVERTERS, or preferably by means of programmable array logics (PAL) or gate array logics.

By way of example in figure 6 there is shown a logical network for generation of signal ENSB.
Two AND gates 34,35 having inverting and non inverting inputs receive the several signals which describe the status of the local bus and the status of the several units connected thereto.

The AND gates 34,35 output signals ENSB1, ENSB2 respectively in case of write or read operation.

The output of gates 34,35 are connected to the input of OR gate 36 which outputs signal ENSB.

Self sustaining of signal ENSB in output from gate 36 is obtained by connecting the output of gate 36 to an input of an AND gate 38, having a second input connected to the output of a NAND gate 37.

Signals NSBINLM and CK are input to NAND 37.

The output of AND gate 38 is connected to an input of gate 36.

It will be noted that three categories of signals are input to gates 34,35:

  • local bus access request signals competing among them: SBINLM,LMRQ,SBRQ. These signals are arbitrated in conventional manner. SBINLM has lower priority than LMRQ and SBRQ: in order for SBINLM to assert ENSB, LMRQ and SBRQ must be deasserted.
  • signals which indicate the status of the local bus as busy (MPSB,MPLM,ENRSB,ENRLM). They all must be deasserted if the lcoal bus has to be granted to any unit.
  • signals which indicate the busy status of the destination resources (LMBSY,LMRPG) which must be deasserted if the local bus has to be granted for access to such destination resources.
It will be noted that while MPSB and MPLM are generated in conventional way by the master MP1 requesting access to the local bus, the signals ENRSB and ENRLM are generated by the arbitrator 13 and have both the meaning of grant signal and of local bus busy signal.

They remain asserted for the whole time interval (two clock cycles in the described embodiment) required to perform over the local bus the information transfer from the requesting unit to the destination unit.

In fact they are deasserted, synchronously with the clock signal CK, only on deassertion of the related access request signals SBRQ,LMRQ respectively.

It will be further noted that the access request (SBINLM) in addition to requesting the local bus, designates the destination unit (local memory) and is further characterized by an accompanying indicator signal (SBR/W) indicating the kind of operation to be performed, hence the resources required for its execution.

In the shown example the designation of the destination unit is implied in signal SBINLM because unit 40 may designate the local memory only.

However, as it is the case for processor MP, unit 40 may be conceived to request access to several resources by using a plurality of access request signals or a single local bus access request signal accompanied by resource designation signals.

Based on the already listed logical equations it is straigth forward to design logical networks for generation of the signals ENRLM, ENRSB,ENCPU.

These networks are represented by block 39.

It may be noted that generation of signals ENRLM, ENRSB does not require the checking, by the arbitrator 13, of the destination unit status (which will be obviously waiting for the read out data, hence available to receive it).

It is the arbitrator 13, which based on a previosly granted access, as a consequence of which either signal LMRQ or signal SBRQ is asserted, identifies as implied, the availability of the destination unit.

As to ENCPU, this signal is generated by default.

Therefore the status of the destination unit does not have to be considered. On the contrary, the status of the destination unit is condition for effective local bus access and generation of signals MPLM and MPSB by block 12.

However nothing precludes from providing central units CPU where the processors MP obtains access to local bus by an arbitration unit on the basis of specific bus access requests and specific bus grant answers which may be generated, not only in compliance with the established priority and the local bus availability, but also in dependence of the effective availability of the destination resource.

It is further clear that whilst reference has been made to CPUs where the "masters" are limited to the processor 7 and the input interface block with the system bus (10,40), the CPUs may comprise a greater number of "master" units such as for instance a direct memory access unit (DMA) or peripheral controllers.

The same consideration is true for the passive or "slave" units: Register banks and other resources may be contemplated in addition to local memory 8 and output interface block with the system bus (10,9).

Claims (4)

  1. Data processing system in which a plurality of requesting units (7,12,10,40) or "masters" compete for access to a common communication bus (11) through which they can select one among a plurality of receiving units (8,9,10) or "slaves" for requesting said selected unit to perform a predetermined operation by means of communication bus access request signals sent to an arbitration unit (13), said arbitration unit (13) granting access to the more prioritary master, among the competing ones, conditional to the availability of said selected unit to perform said predetermined operation requested by said bus access request signal,
    characterised in that said arbitration unit (13) comprises:
    circuit means (34,35,39) for asserting an access grant signal (ENSB,ENRLM,ENRSB) granting to one of said masters access to said common communication bus, on the basis of said one master priority as to the other requesting masters priority and conditional to the availability of the selected slave to perform said predetermined operation and to the non-busy state of said bus as indicated by the deasserted state of access grant signals (ENSB,ENRLM,ENRSB), granting bus access to others of said masters.
  2. Data processing system as claimed in claim 1 wherein at least one of said slaves comprises means for generating and inputing to said circuit means (34,35,39) in said arbitration unit, a signal indicating that said one slave is available to perform said predetermined operation.
  3. Data processing system as claimed in claim 1 or claim 2 wherein said means in said at least one slave provide an indication of the availability of said one slave to perform one of a plurality of predetermined operations, said circuit means (34,35) receiving from said masters an indication of the selected slave requested to perform an operation and an indication identifying said operation among said predetermined operations, said circuit means granting to one of said requesting masters access to said common communication bus (11) on the basis of said one master priority as to other requesting masters and conditional to the availability of the selected slave to perform said operation identified among said predetermined operations.
  4. Data processing system as in any of the preceding claims, wherein said circuit means asserting said bus access grant signal identifies the availability of the selected slave to perform said predetermined operation, based on a previously granted access.
EP19930116232 1988-11-18 1989-11-04 Data processing system having units competing for access to shared resources and arbitration unit responsive to the status of the shared resources Expired - Lifetime EP0581335B1 (en)

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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5301337A (en) * 1990-04-06 1994-04-05 Bolt Beranek And Newman Inc. Distributed resource management system using hashing operation to direct resource request from different processors to the processor controlling the requested resource
US5265257A (en) * 1990-06-22 1993-11-23 Digital Equipment Corporation Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines
EP0537899B1 (en) * 1991-09-27 1999-12-15 Sun Microsystems, Inc. Bus arbitration architecture incorporating deadlock detection and masking
US5283870A (en) * 1991-10-04 1994-02-01 Bull Hn Information Systems Inc. Method and apparatus for avoiding processor deadly embrace in a multiprocessor system
US5426739A (en) * 1992-03-16 1995-06-20 Opti, Inc. Local bus - I/O Bus Computer Architecture
US5309568A (en) * 1992-03-16 1994-05-03 Opti, Inc. Local bus design
US5388224A (en) * 1992-04-24 1995-02-07 Digital Equipment Corporation Processor identification mechanism for a multiprocessor system
US5666511A (en) * 1992-10-08 1997-09-09 Fujitsu Limited Deadlock suppressing schemes in a raid system
US5500946A (en) * 1992-11-25 1996-03-19 Texas Instruments Incorporated Integrated dual bus controller
FR2708766B1 (en) * 1993-08-03 1995-09-08 Bull Sa Method for analyzing deadlocks in an operating system.
US5708794A (en) * 1993-08-10 1998-01-13 Dell Usa, L.P. Multi-purpose usage of transaction backoff and bus architecture supporting same
WO1995020191A1 (en) * 1994-01-25 1995-07-27 Apple Computer, Inc. System and method for coordinating access to a bus
US5469435A (en) * 1994-01-25 1995-11-21 Apple Computer, Inc. Bus deadlock avoidance during master split-transactions
GB9405855D0 (en) * 1994-03-24 1994-05-11 Int Computers Ltd Computer system
US5586289A (en) * 1994-04-15 1996-12-17 David Sarnoff Research Center, Inc. Method and apparatus for accessing local storage within a parallel processing computer
US5878240A (en) * 1995-05-11 1999-03-02 Lucent Technologies, Inc. System and method for providing high speed memory access in a multiprocessor, multimemory environment
US5682537A (en) * 1995-08-31 1997-10-28 Unisys Corporation Object lock management system with improved local lock management and global deadlock detection in a parallel data processing system
KR0172310B1 (en) * 1995-12-29 1999-03-30 김주용 Bus unit
US6006255A (en) * 1996-04-05 1999-12-21 International Business Machines Corporation Networked computer system and method of communicating using multiple request packet classes to prevent deadlock
US6085263A (en) * 1997-10-24 2000-07-04 Compaq Computer Corp. Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor
US6108737A (en) * 1997-10-24 2000-08-22 Compaq Computer Corporation Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system
US6055605A (en) * 1997-10-24 2000-04-25 Compaq Computer Corporation Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches
US6286090B1 (en) * 1998-05-26 2001-09-04 Compaq Computer Corporation Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches
US6792513B2 (en) 1999-12-29 2004-09-14 The Johns Hopkins University System, method, and computer program product for high speed backplane messaging
CA2322613A1 (en) 2000-10-06 2002-04-06 Ibm Canada Limited-Ibm Canada Limitee Latch mechanism for concurrent computing environments
US6795878B2 (en) * 2000-12-11 2004-09-21 International Business Machines Corporation Verifying cumulative ordering of memory instructions
GB0118294D0 (en) * 2001-07-27 2001-09-19 Ibm Method and system for deadlock detection and avoidance
US8473634B2 (en) * 2003-10-23 2013-06-25 Microsoft Corporation System and method for name resolution
US7185175B2 (en) * 2004-01-14 2007-02-27 International Business Machines Corporation Configurable bi-directional bus for communicating between autonomous units
US7694023B1 (en) 2006-01-24 2010-04-06 Lockheed Martin Corporation Routing a processor communication
WO2008154360A1 (en) * 2007-06-06 2008-12-18 Hunt Technologies, Llc Arbitration of memory transfers in a dsp system
US8429353B2 (en) * 2008-05-20 2013-04-23 Oracle America, Inc. Distributed home-node hub

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038644A (en) * 1975-11-19 1977-07-26 Ncr Corporation Destination selection apparatus for a bus oriented computer system
NL7907179A (en) * 1979-09-27 1981-03-31 Philips Nv The processor and multiprocessor systems with conditional -interrupteenheid with this signal processor devices.
US4698746A (en) * 1983-05-25 1987-10-06 Ramtek Corporation Multiprocessor communication method and apparatus
US4763249A (en) * 1983-09-22 1988-08-09 Digital Equipment Corporation Bus device for use in a computer system having a synchronous bus
US4807109A (en) * 1983-11-25 1989-02-21 Intel Corporation High speed synchronous/asynchronous local bus and data transfer method
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system
EP0179936B1 (en) * 1984-10-31 1990-01-03 Ibm Deutschland Gmbh Method and apparatus for global bus control
US4760521A (en) * 1985-11-18 1988-07-26 White Consolidated Industries, Inc. Arbitration system using centralized and decentralized arbitrators to access local memories in a multi-processor controlled machine tool
CA1274918A (en) * 1985-11-27 1990-10-02 John G. Theus Bus arbitration controller
US4779089A (en) * 1985-11-27 1988-10-18 Tektronix, Inc. Bus arbitration controller
JPS62243058A (en) * 1986-04-15 1987-10-23 Fanuc Ltd Control method of interruption for multi-processor system
US4851996A (en) * 1986-12-12 1989-07-25 Bull Hn Information Systems Italia, S.P.A. Common resource arbitration circuit having asynchronous access requests and timing signal used as clock input to register and mask signal to priority network
US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
US4866664A (en) * 1987-03-09 1989-09-12 Unisys Corporation Intercomputer communication control apparatus & method
US5068781A (en) * 1987-05-01 1991-11-26 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
US4949239A (en) * 1987-05-01 1990-08-14 Digital Equipment Corporation System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
US4937777A (en) * 1987-10-07 1990-06-26 Allen-Bradley Company, Inc. Programmable controller with multiple task processors
US5038274A (en) * 1987-11-23 1991-08-06 Digital Equipment Corporation Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus

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EP0581335A2 (en) 1994-02-02 application
EP0369264A3 (en) 1990-07-18 application
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EP0369264A2 (en) 1990-05-23 application
US5182808A (en) 1993-01-26 grant
EP0581335A3 (en) 1995-11-08 application
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