EP0524976A1 - Systemes d'affichage video - Google Patents

Systemes d'affichage video

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Publication number
EP0524976A1
EP0524976A1 EP19910907013 EP91907013A EP0524976A1 EP 0524976 A1 EP0524976 A1 EP 0524976A1 EP 19910907013 EP19910907013 EP 19910907013 EP 91907013 A EP91907013 A EP 91907013A EP 0524976 A1 EP0524976 A1 EP 0524976A1
Authority
EP
European Patent Office
Prior art keywords
pixel
faulty
display apparatus
video display
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP19910907013
Other languages
German (de)
English (en)
Inventor
Raymond Gordon Fielding
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rank Brimar Ltd
Original Assignee
Rank Brimar Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rank Brimar Ltd filed Critical Rank Brimar Ltd
Publication of EP0524976A1 publication Critical patent/EP0524976A1/fr
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/002—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to project the image of a two-dimensional display, such as an array of light emitting or modulating elements or a CRT
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/74—Projection arrangements for image reproduction, e.g. using eidophor
    • H04N5/7416—Projection arrangements for image reproduction, e.g. using eidophor involving the use of a spatial light modulator, e.g. a light valve, controlled by a video signal
    • H04N5/7458—Projection arrangements for image reproduction, e.g. using eidophor involving the use of a spatial light modulator, e.g. a light valve, controlled by a video signal the modulator being an array of deformable mirrors, e.g. digital micromirror device [DMD]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H04N9/3179—Video signal processing therefor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/10—Dealing with defective pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present invention relates to video display systems more particularly (but not exclusively) to projection systems, and specifically those which include a spatial light modulator device-
  • Spatial light modulator display devices include so-called active "active matrix” devices, in which an array of light modulating elements, or “light valves", each of which is controllable by a control signal (usually an electrical signal) to controllably reflect or transmit light in accordance with the control signal.
  • a liquid crystal array is one example of an active matrix device; another example is the deformable mirror device (DMD) array developed by Texas Instruments and described in, for example, US4615595 or in "128 x 128 deformable mirror device” IEEE Trans. Electron Devices ED-30, 539 (1983), L J Hornbeck.
  • DMD deformable mirror device
  • a DMD array comprises a plurality of separately addressed electrically deflectable mirrors; if a light beam is directed on the array device, the light reflected in a given direction by the array will depend upon the angle of inclination of each mirror, so that a video image may be superimposed on a reflected beam of light by controlling the mirrors of the array in accordance with the values of a frame of a video signal.
  • a greatly preferred alternative method which gives better contrast, involves controlling the mirror deflection between two positions corresponding to substantially reflective and unreflective states, and controlling the length of time in which the mirror in the reflective state.
  • three separately illuminated active matrix devices may be provided, each controlled by a respective colour signal and illuminated by a respective colour light beam, the modulated colour light beams being recombined for display, for example as disclosed in US4680579 or in our UK patent applications 9101715.2 and 9101714.5 filed on 25 January 1991 (agents ref. 3203301 and 3203401), incorporated herein by reference.
  • One example of a spatial modulator device which is not an active matrix device is the "eidophor" system, in which an oil film is illuminated by a light beam and, simultaneously, scanned by an electron beam controlled by a video signal, which acts to control the reflective state of the oil film.
  • Such active matrix displays include small mechanically moving components and can consequently be fragile; it is known for single pixels of the display to suffer catastrophic failure either during the manufacturing process or during service, so as to be destroyed or deactivated giving zero light output, or only an insignificantly low light output compared with that for which they were designed. Furthermore, in such active matrix displays a pixel or pixels may be electrically shorted to be permanently enabled and hence modulate light when in fact they should not be energised.
  • One type of active matrix display consists of an array of row and column address lines with a semiconductor device or other enabling switch at each node therebetween, the purpose of which is to select and apply data to the corresponding pixel display element according to the applied address signals.
  • the incoming video data is received in serial form from left to right along each display line and then line after line sequentially from the top to the bottom of the display.
  • the received data may then be written to the pixel elements a line at a time or a frame at a time, or in any other convenient format.
  • each complete display frame of data is comprised of two separate fields of data displaced relative to each other both spatially and in time.
  • the complete frame of video data is scanned in a single pass and thus a display frame is the same as a single field of video data. It is possible to utilise this incoming video format directly by writing each item of video data to the corresponding relevant pixel display element as it arrives. Stray capacitance associated with each pixel element is utilised to store this value until the next write time (next frame), some milliseconds later.
  • the incoming video data rate is such that there is insufficient time available to charge each pixel capacitance at the pixel rate time.
  • the incoming video data is first written into a temporary line store and then, at the end of each line when more time is available, the data is transferred en bloc from the line store to the relevant row of pixels.
  • the pixel write time thus available is at least equal to the line retrace time or can be as long as a complete line scan interval.
  • Some forms of active matrix display write the pixel data in a different format to the incoming video data and thus require the temporary storage of a complete field or frame of video data.
  • An illustrative case in point is the matching of a progressively scanned display to an incoming interlaced video data or vice versa.
  • pixel display element fault there are basically two types of pixel display element fault, the first being a pixel element which fails to operate at all or fails to operate at the required light level and the second being a pixel element which remains ON when it should be OFF.
  • a shorted or permanently ON pixel the effect depends on the manner in which the device is addressed.
  • successive lines of video data are applied to the column address lines, and enable signals are applied to the row lines to enable a corresponding row of switches to receive each successive line of video data as discussed in the above-cited Hornbeck paper.
  • Each pixel retains its data for the field time interval.
  • a shorted pixel is permanently connected to the display column drive line (and thus permanently enabled) and will consequently be driven by the video signal applied to every pixel element of the complete column of pixels.
  • the video data for a pixel on any line will be present on the column line for 1/nth of the complete field time interval.
  • a shorted pixel will display the sum of all n individual pixel contributions on that column in succession, that is the sum of each pixel brightness, each for 1/nth of a field period, as opposed to a corresponding working pixel element which displays its own value during a complete field period.
  • the effective brightness of that pixel at any instant will correspond to the average brightness of a column of pixels containing that pixel.
  • the error observed is equal to the actual brightness video sample which should be displayed less this value, i.e:
  • a video display apparatus including a matrix of pixel areas corrects the video signal supplied to visually close pixel areas to oppose the effect of the error due to the faulty ' pixel.
  • the error caused by the faulty pixel is compensated by the application of a correction amount, of opposite sign and related magnitude to the error, to the surrounding display elements.
  • correction signals are applied to display elements which are sufficiently close to the faulty element so that the human eye does not resolve them as separate elements of the display, a surprising reduction in the perception of the faulty pixels by a viewer may be achieved.
  • the first way is to apply a correction signal continuously to all pixels in the display irrespective of whether they are faulty or not.
  • correction of this kind is simple to implement because it does not require any knowledge of the location of the faulty pixel(s), it does give rise to other disadvantages.
  • Continuous correction is accompanied by a loss of resolution. This also results in a reduction in the sharpness of the edges of any displayed objects.
  • This second technique involves selectively applying a correction signal to one or more of the video signal pixel samples which correspond to display pixel elements immediately adjacent the faulty pixel and not to other pixel samples.
  • the maximum compensation for a faulty pixel is achieved by applying the correction signal to all of those pixel samples which correspond to pixel elements immediately adjacent the faulty pixel element, and minimal compensation for a faulty pixel element would be acheived by applying the correction signal to only one of the pixel samples immediately adjacent that corresponding to the faulty pixel.
  • the correction signal For any pixel element not on the corner or edge of the display there will be eight pixel elements adjacent any other pixel in the case of a rectangular pixel arrangement and six in the case of a diamond pixel arrangement. Therefore compensation can be achieved by applying the correction signal to between one and eight pixels adjacent a faulty pixel.
  • This system requires a location map of the faulty pixels .
  • This faulty pixel map can be provided in permanent memory, such as EPROM (Erasable Programmable Read Only Memory) , and/or be generated by an automatic self test routine.
  • EPROM Erasable Programmable Read Only Memory
  • the occurrence of a faulty pixel may be determined by activating each pixel in turn and then monitoring the resultant effect on the display light output.
  • a faulty pixel Once a faulty pixel is detected, its location address is given by the current display address input. The address of the faulty pixel is then stored.
  • the equipment required to determine the location of the faulty pixels may form part of the display device, or may be a separate piece of equipment.
  • the faulty pixel map can then either be provided by the display manufacturer programmed into an EPROM or a similar memory device or can be updated automatically at regular service intervals and stored in electrically alterable solid state or other rapid access memory.
  • the present invention is based on the appreciation that at normal viewing distances, particularly in relation to high resolution video displays such as so-called High Definition TV (HDTV), visual resolution as perceived by the eye of the viewer integrates the resultant bright halo surrounding the faulty pixel into a smooth final display brightness.
  • HDTV High Definition TV
  • a colour projection device may, as shown in US4680579, be provided by three separate spatial modulator devices each controlled by a respective colour video signal and illuminated by a corresponding coloured light beam.
  • correction need only be applied to the data written to the device containing the faulty pixel element.
  • Figure 1A illustrates a portion of an active matrix display showing a number of pixels in a rectangular array
  • Figure IB illustrates a portion of an active matrix display showing a number of pixels in a diamond array
  • Figure 2 is a block circuit diagram of an embodiment of the invention
  • Figure 3 is a flow diagram illustrating schematically the method of operation of a further embodiment of the invention.
  • Figure 4 is a block diagram showing schematically the structure of the embodiment of figure 3;
  • Figure 5 is a flow diagram showing schematically the method of operation of the embodiment of figure 2;
  • Figures 6A and 6B are schematic illustrations of alternative arrangements of a store portion of the apparatus of figure 2;
  • Figure 7 shows schematically a method of deriving the contents of the store shown in figure 6;
  • Figure 8 shows schematically the general arrangement of a projection system including a spatial light modulator device of the active matrix type;
  • Figure 9 shows a portion of figure 8 in greater detail;
  • Figure 10 shows schematically the arrangement of a colour projection system
  • Figure 11 shows schematically a portion of figure 8 in greater detail
  • Figures 12A and 12B respectively show a plan and elevation view of a projection system in use
  • Figure 13A shows schematically a detail of the array device of figure 9.
  • Figure 13B shows an individual mirror element of the device of figure 13A.
  • a projection system comprises a reflective screen (for example a cinema screen) B and a projector A, positioned and aligned relative to the screen so as to generate a focused image on the screen.
  • the projector A comprises a lamp Al, typically rated at several kilowatts for a cinema application, generating a light beam which is directed onto a planar active matrix display device A2 comprising, for example, a DMD array of 512 x 512 individual pixel mirrors.
  • Each mirror of the display device A2 is individually connected to be addressed by an addressing circuit A3 which receives a video signal in any convenient format (for example, a serial raster scanned interlaced field format) and controls each individual mirror in accordance with the corresponding pixel signal value within the video signal.
  • a video signal in any convenient format (for example, a serial raster scanned interlaced field format) and controls each individual mirror in accordance with the corresponding pixel signal value within the video signal.
  • the modulated reflected beam from the active matrix device A2 (or rather, from those pixel mirrors of the device which have been selectively activated by the address circuit A3) is directed to a projector lens system A4 which, in a conventional manner, focuses, magnifies and directs the beam onto the screen B as shown schematically in figure 9.
  • three separate active matrix devices A2a-A2c are provided, one driven by each of three separate colour video signals from the address circuit A3, with separate illumination arrangements Ala-Ale producing beams of the different colours.
  • the arrangement may be disclosed in US4680579, for example.
  • the light reflected from the three devices A2a-A2c is combined (not shown) and supplied to the lens system A4.
  • the projector A In use in an auditorium, the projector A is positioned at a distance from the screen B, which is preferably of arcuate shape, the projector A being positioned on a line passing through the centre of curvature of the arc.
  • the viewing space or auditorium lies between the projector A and the screen B as shown in figure 12a and 12b.
  • one type of display device comprises a plurality of row enable lines A2d and a plurality of column enable lines A2e.
  • the address circuit A3 comprises an input port receiving a digital video signal in an input format (for example, a conventional line scanned interlaced field format), a scan convertor circuit A3a for converting the input video signal format into one suitable for display on the device A2 and an addressing circuit A3b arranged to selectively activate corre- onding pixel mirrors of the device A2 in accordance with a signal from the scan convertor circuit A3a.
  • an input format for example, a conventional line scanned interlaced field format
  • a scan convertor circuit A3a for converting the input video signal format into one suitable for display on the device A2
  • an addressing circuit A3b arranged to selectively activate corre- onding pixel mirrors of the device A2 in accordance with a signal from the scan convertor circuit A3a.
  • the scan convertor circuit receives a composite colour video signal, for example, and generates therefrom three separate colour component video signals supplied to three separate addressing circuits A3b, one for each display device A2.
  • a clock circuit A3c controls the timing of the address circuit A3b; in one preferred mode of operation, as discussed above, the intensity displayed by each pixel mirror is controlled by controlling the time for which that pixel mirror is deflected, and corresponding timing signals are derived from the clock A3c.
  • a semiconductor switch A2f the control terminal of which is connected to, for example, a row enable line A2d.
  • the switch may comprise a field effect transistor, the gate of which is connected to a row enable line A2d.
  • the source of the field effect transistor is connected to one of the column enable lines A2e and the drain to the deflection terminal of a deflectable mirror device, shown generally in figure 13B.
  • each mirror device A2g will, when addressed by a row enable signal, deflect in response to the signal applied to its corresponding column enable line A2e.
  • Each mirror device A2g and switch A2f combination is arranged to latch the display state of the mirror device A2g until the next time the mirror device is addressed, in other words, for a field or frame period.
  • the mirror will respond once each line period rather than once each field or frame period, and will display, in succession, brightness value for every pixel mirror in its column.
  • Figure 1A illustrates a portion of a matrix device A2 with the pixel display elements arranged in a rectangular configuration and shows a faulty pixel element P and its immediately adjacent pixel elements PI to P8 respectively.
  • Figure IB illustrates a portion of a differently arranged matrix device A2 with the pixel display elements arranged in a triangular, or diamond, configuration where similar considerations apply except that there are only six pixel elements PI to P8 surrounding the faulty pixel element P.
  • the brightness signal applied to a pixel display element, P will be made up of that of its own video signal pixel sample plus contributions from samples of immediately adjacent pixel elements.
  • each pixel display element displays its own brightness sample plus a correction contribution from the samples for each of the N pixels immediately surrounding it. This, for every pixel P,
  • A input pixel brightness signal
  • n W weighting factor from surrounding pixel
  • n N number of adjacent pixel elementsn used
  • N ⁇ 8 1/(1+NW) then N ⁇ 8 for a rectangular pixel matrix, fig.la, or N ⁇ 6 for the matrix of fig.lb.
  • An alternative way of viewing this embodiment is to consider a single video signal pixel sample as being shared out or diffused into pixel elements surrounding the central pixel element to which it corresponds.
  • a value of W higher than the value K means that each
  • the change in effective brightness will be determined by the value of K whilst in the case of a shorted pixel, the change in brightness will be less than or equal to K depending on the mean column pixel brightness.
  • the maximum loss in light output from that pixel will be 50% of the pixel brightness whilst its effect on the light output of an adjacent pixel will not exceed 1/2XN of the maximum pixel brightness.
  • a special case occurs where a pixel lies at the edge or in a corner of the frame.
  • Such an edge or corner pixel has only a limited number of neighbours; for example, in the matrix of figure 1A an edge pixel has only five neighbours and a corner pixel has only three.
  • the value of N is different; it is therefore preferable to provide logic to detect when a pixel is an edge pixel or a corner pixel, and preferable correspondingly to apply different values of W .
  • the process comprises, for each pixel sample of an incoming video signal, detecting the values of neighbouring samples on the same and neighbouring lines of the video image, multiplying each sample value by a predetermined weighting factor W , and adding the accumulated sum to
  • the modified pixel value is
  • apparatus for performing such an embodiment comprises an input 20 for receiving a digitised video signal, and a shift register circuit 22A for presenting a two-dimensional window comprising 9 contiguous pixel samples P, P1-P8.
  • the shift register circuit 22 comprises two serially connected first-in first-out stores 22A,22B each of length 1 line of the video signal and a three stage delay line 22C coupled to the output of the second register 22B.
  • the first three stages of the first-in first out registers 22A,22B and three stages of the delay line 22C, are tapped; the taps corresponding to the pixels P1-P8 are connected to a summation unit 24 the output of which is multiplied by a multiplier 26 by the fixed constant W .
  • the tap corresponding to the centre location P of the window is connected to be added to the output of the multiplier 26 at an adder stage 28, and the output of the adder 28 is multiplied by the constant K by a multiplier 30.
  • the digital arithmetic components 24-30 are conveniently provided as a single digital signal processing (DSP) device 32 such as the AT&T DSP32C device or the Texas Instruments TMSC30 device arranged to accept digital input samples and perform high speed arithmetic operations thereon.
  • DSP digital signal processing
  • an analogue equivalent circuit to the embodiment of figure 4 could be provided, in which the video input 20 provides an analogue input sampled at the pixel rate, and the delay lines 22A-22C comprise analogue shift registers such as charge coupled device (CCD) registers or bucket brigade device (BBD) registers.
  • the summation and multiplying units 24,26 may comprise suitable operational amplifier components, as may the addition and multiplication units 28,30, or a DSP could be used if preceded by an analogue to digital convertor.
  • input 10 receives a digital video signal in line scanned format, as before, and supplies the input to a first-in, first-out (FIFO) store circuit 1 capable of holding two complete video lines plus three extra pixels of digital video data as described above.
  • FIFO first-in, first-out
  • the pixel P of figure 1A is indicated together with its surrounding pixels PI to P8.
  • the data values held in the first three pixels of each of the two lines plus the three additional pixels are tapped to provide the brightness values of a two-dimensional window section of the active matrix display as shown in figure 1.
  • This aata at the taps is routed via a weighting network 2 to a digital signal processor (DSP) 3, such as the AT&T DSP32C device or the Texas Instruments TMSC30, or to a dedicated digital arithmetic and logic circuit.
  • DSP digital signal processor
  • the corrected pixel brightness values are computed by the digital signal processor 3 according to the equation (1) referred to above, but in this embodiment, a weighted correction is only added from pixels known to correspond to faulty display elements as discussed below.
  • the resulting corrected pixel values are then passed to a frame store 4 for display.
  • the value of the constant K is set to unity, or close thereto, so that where no neighbouring pixel is faulty, the value of the pixel sample is unchanged.
  • the frame store 4 is provided with the active matrix display since it is required to convert the incoming video data format to that required to drive the display.
  • the output from the digital signal processor 3 can be fed directly to the active matrix display 9.
  • the location of any faulty display pixels is held in a faulty pixel map store unit 5.
  • the unit 5 could employ either standard read-only-memory (ROM) devices or alternatively an erasable programmable read only memory
  • the faulty pixel location information is then used by the digital signal processor 3 to decide whether to include the correction values into the final computed pixel brightness value.
  • a control processor 8 manages the complete system and serves to synchronise the various operations and also the final active matrix display to the incoming video format.
  • the control processor 8 provides the current address signals to the various data stores together with a FIFO clock signal.
  • the control processor 8 accepts the standard line and field synchronising signals provided with the incoming video data to determine the start of line and start of field timing.
  • the control processor 8 then generates new synchronising pulses required by the active matrix display taking into account the FIFO and computational delays.
  • the control processor 8 generates a sequence of successive addresses, one at each step of the pixel clock.
  • a corresponding address at each stage is generated by the control processor and supplied to the address bus of the frame store 4; the address corresponds to that of the centre pixel P of the window within the FIFO store 1, and is consequently not the address of the pixel currently received at the input 10.
  • the corrected pixel value calculated by the DSP 3 is therefore stored at the correct location in the frame store 4.
  • the control processor 8 likewise supplies an address to the fault pixel map store unit 5. This address likewise corresponds to the pixel element P currently in the centre location of the FIFO store 1.
  • each location in the faulty pixel map store unit 5 may comprise 16 bits, arranged as groups of two single bit flags for representing each of the pixel elements P1-P8 which surround the pixel P corresponding to that location; a first bit F acting as
  • a fault exists, whether it is an inactive pixel or an open circuit pixel fault.
  • the 16 bit contents of the location accessed within the faulty pixel map are supplied to the DSP 3, which accordingly determines from the fault flags F whether
  • any of the neighbouring pixel elements to the pixel element P are faulty. If no neighbouring pixel elements are faulty the DSP 3 generates as output the unmodified pixel value P. If any neighbouring pixel n is determined to be faulty the DSP 3 examines the nature of the fault from the type flag T . If the, or each, fault comprises an inoperative pixel element the DSP 3 multiplies the value of the corres ⁇ ponding pixel sample P obtained from the FIFO store 1
  • the fault is indicated to be a short circuit fault
  • a short circuit will generally cause a pixel element of the display device to respond to video samples at element column positions corresponding to its own in each line of the frame (in other words, in all rows at its column position). Its instantaneous value, when averaged over an entire frame, is thus the average of the pixel values within its column.
  • This calculated value represents the brightness which the pixel display element will appear to exhibit to a viewer. From this is subtracted the value A of the sample which
  • apparatus 6,7 for computing an average is straightforward and could comprise, for example, an accumulating adder clocked once each line period, arranged to store a running average (7), to add (6) the present pixel value to its accumulated sum and then perform a bit shift to divide the sum by 2.
  • this "running average" circuit prior to being supplied to the video input 10, the signal could be buffered in a frame store and line averages calculated.
  • the mean value is stored in the mean column value store 7. This store holds the equivalent of one complete column of pixel data, corresponding to one mean value per column, and is circularly clocked with the FIFO store 1 to the appropriate column value to supply the DSP 3.
  • a double buffer storage system is preferred such that whilst one store is accumulating the mean value, the other will output its data to the computational block 3.
  • the arrangement shown in figure 2 is a digital arrangement.
  • this embodiment could also be realised in a sampled analogue arrangement in which the signal processing is carried out using charge coupled devices for the FIFO 1 and analogue multipliers and adders for the signal processing.
  • the store arrangement shown in figure 6A provides convenient addressing, since a location for each pixel sample value contains data on all the neighbouring pixel sample values. However, this results in considerable replication of data since data on -.-hether a given pixel is faulty will be stored in a loca"; jn corresponding to each of its eight neighbour-.. Whilst in many applications this is not a problem, an alternative arrangement of the store .5is shown in figure 6B. In this alternative arrangement, the store 5 comprises a store 5a in which a pair of flags F , described above
  • An address counter 5b coupled to the address lines of the store 5a counts upwards to produce a sequence of addresses so that the two bit word comprising the two flags Fl, Tl for the pixel P being processed by the DSP 3 is put on the data output bus of the store 5a.
  • a circulating shift register 5c having the same structure as the FIFO store 1 or 22 (although each location in the store need only be two bits wide). The taps from the store 5c therefore provide eight two bit words each comprising the two flags F , T required by the DSP 3, and are used
  • the first stage comprises the detection of inoperative pixels.
  • a photosensor is placed in front of the display device.
  • the display device is then illuminated, and each pixel display element is in turn activated.
  • the output of the photosensor 8 is compared with a predetermined threshold, and when it falls below the threshold the corresponding pixel display element is indicated to be inoperative. If the store is arranged as in figure 6A, the corresponding pair of flags F , P are written to the eight neighbour
  • a shorted pixel could be detected electrically, but optical detection is also possible; for instance, without applying a signal to the row lines of the display device, a signal may be applied in turn to each of the column lines of the device. If the photosensor indicates no illumination, no short circuit exists. However, if any column does give rise to illumination without a row line being enabled, a short circuit is present. To locate the row containing the short circuit, each row line in turn may be enabled; when the photosensor output drops somewhat (indicating that only a single pixel is illuminated) the fault is detected and, as before, the corresponding fault and type flags are written to the appropriate locations in the store 5.
  • the display system also includes means for correcting intensity variations of different display areas as disclosed in our application PCT/GB91/

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

Système d'affichage vidéo incluant une matrice active pourvue de pixels pouvant être excités sélectivement, caractérisé par le fait qu'il possède des moyens de compensation visuelle d'un pixel défectueux qui, soit ne s'éclaire pas quand il est sélectionné, soit continue à s'éclairer quand il n'est pas sélectionné, lesdits moyens comprenant un dispositif au moyen duquel la brillance d'au moins l'un des pixels immédiatement contigus au pixel défectueux est ajustée automatiquement de façon qu'un observateur perçoive le pixel défectueux comme ne l'étant pas.
EP19910907013 1990-04-09 1991-04-09 Systemes d'affichage video Ceased EP0524976A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9008032 1990-04-09
GB909008032A GB9008032D0 (en) 1990-04-09 1990-04-09 Video display systems

Publications (1)

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EP0524976A1 true EP0524976A1 (fr) 1993-02-03

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EP19910907013 Ceased EP0524976A1 (fr) 1990-04-09 1991-04-09 Systemes d'affichage video

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EP (1) EP0524976A1 (fr)
JP (1) JPH05506108A (fr)
AU (1) AU7661191A (fr)
GB (1) GB9008032D0 (fr)
WO (1) WO1991015843A2 (fr)

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Also Published As

Publication number Publication date
JPH05506108A (ja) 1993-09-02
AU7661191A (en) 1991-10-30
GB9008032D0 (en) 1990-06-06
WO1991015843A2 (fr) 1991-10-17
WO1991015843A3 (fr) 1991-11-14

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