EP0366036A3 - Memory management in packet data mode systems - Google Patents

Memory management in packet data mode systems Download PDF

Info

Publication number
EP0366036A3
EP0366036A3 EP19890119599 EP89119599A EP0366036A3 EP 0366036 A3 EP0366036 A3 EP 0366036A3 EP 19890119599 EP19890119599 EP 19890119599 EP 89119599 A EP89119599 A EP 89119599A EP 0366036 A3 EP0366036 A3 EP 0366036A3
Authority
EP
European Patent Office
Prior art keywords
packet data
field
signal
data mode
communicating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19890119599
Other languages
German (de)
French (fr)
Other versions
EP0366036B1 (en
EP0366036A2 (en
Inventor
Robert Pieters
Richard Gene Sowell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US07/263,715 priority Critical patent/US5047927A/en
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of EP0366036A2 publication Critical patent/EP0366036A2/en
Publication of EP0366036A3 publication Critical patent/EP0366036A3/en
Application granted granted Critical
Publication of EP0366036B1 publication Critical patent/EP0366036B1/en
Priority to US263715 priority
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

This invention is a memory management system for a packet data mode system which is used in conjunction with a direct memory access controller. The management system is of the type for communicating packet data into and out of memory storage. Each message in a packet data mode system contains a control address field and a data field. The invention includes means for generating a change of field signal and for communicating that signal to the DMA controller. The invention also includes means for generating an end of message signal with means for communicating the end of message signal to the DMA controller. The contrcl address field is stored separately from the data field. This increases the efficiency of the data storage and enhances the density of information packing into the memory storage.
EP19890119599 1988-10-28 1989-10-23 Memory management in packet data mode systems Expired - Lifetime EP0366036B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US07/263,715 US5047927A (en) 1988-10-28 1988-10-28 Memory management in packet data mode systems
US263715 2002-10-04

Publications (3)

Publication Number Publication Date
EP0366036A2 EP0366036A2 (en) 1990-05-02
EP0366036A3 true EP0366036A3 (en) 1991-03-13
EP0366036B1 EP0366036B1 (en) 1996-03-27

Family

ID=23002956

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890119599 Expired - Lifetime EP0366036B1 (en) 1988-10-28 1989-10-23 Memory management in packet data mode systems

Country Status (4)

Country Link
US (1) US5047927A (en)
EP (1) EP0366036B1 (en)
JP (1) JPH02216943A (en)
DE (2) DE68926091D1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5588120A (en) * 1994-10-03 1996-12-24 Sanyo Electric Co., Ltd. Communication control system for transmitting, from one data processing device to another, data of different formats along with an identification of the format and its corresponding DMA controller
DE69132236T2 (en) * 1990-08-22 2000-11-30 Sanyo Electric Co Transmission control system
JP2589205B2 (en) * 1990-08-24 1997-03-12 三洋電機株式会社 Communication control system
WO1993023809A1 (en) * 1992-05-15 1993-11-25 Connective Strategies, Inc. Isdn-based high speed communication system
CA2135681C (en) * 1993-12-30 2000-01-18 Srinivas V. Makam System and method for directly accessing long-term memory devices
US5664223A (en) * 1994-04-05 1997-09-02 International Business Machines Corporation System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
US6145027A (en) * 1997-07-09 2000-11-07 Texas Instruments Incorporated DMA controller with split channel transfer capability and FIFO buffering allowing transmit channel to get ahead of corresponding receive channel by preselected number of elements
US6563799B1 (en) * 1999-01-29 2003-05-13 Avaya Technology Corp. Application module interface for hardware control signals in a private branch exchange (PBX) environment
US20040098519A1 (en) * 2001-03-16 2004-05-20 Hugo Cheung Method and device for providing high data rate for a serial peripheral interface
US6715000B2 (en) * 2001-03-16 2004-03-30 Texas Instruments Incorporated Method and device for providing high data rate for a serial peripheral interface
EP1537484A1 (en) * 2002-08-30 2005-06-08 Koninklijke Philips Electronics N.V. Dynamic memory management
US7576073B2 (en) * 2004-05-28 2009-08-18 UNIVERSITé LAVAL Combined therapy for the treatment of parkinson's disease
US20070168579A1 (en) * 2005-09-20 2007-07-19 Telefonaktiebolaget Lm Ericsson (Publ) DMA transfer and hardware acceleration of PPP frame processing

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0029800A1 (en) * 1979-11-23 1981-06-03 United Technologies Corporation Digital information transfer system (DITS) receiver and method
US4368512A (en) * 1978-06-30 1983-01-11 Motorola, Inc. Advanced data link controller having a plurality of multi-bit status registers
EP0089440A1 (en) * 1982-03-24 1983-09-28 International Business Machines Corporation Method and device for the exchange of information between terminals and a central control unit
EP0125561A2 (en) * 1983-05-13 1984-11-21 International Business Machines Corporation Data-processing system having multi-buffer adapter between a system channel and an input/output bus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317197A (en) * 1978-06-02 1982-02-23 Texas Instruments Incorporated Transparent intelligent network for data and voice
JPH0517584B2 (en) * 1986-07-30 1993-03-09 Tokyo Shibaura Electric Co
JPH01177239A (en) * 1988-01-06 1989-07-13 Nec Corp Packet concentrator and packet switching device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4368512A (en) * 1978-06-30 1983-01-11 Motorola, Inc. Advanced data link controller having a plurality of multi-bit status registers
EP0029800A1 (en) * 1979-11-23 1981-06-03 United Technologies Corporation Digital information transfer system (DITS) receiver and method
EP0089440A1 (en) * 1982-03-24 1983-09-28 International Business Machines Corporation Method and device for the exchange of information between terminals and a central control unit
EP0125561A2 (en) * 1983-05-13 1984-11-21 International Business Machines Corporation Data-processing system having multi-buffer adapter between a system channel and an input/output bus

Also Published As

Publication number Publication date
DE68926091T2 (en) 1996-11-21
US5047927A (en) 1991-09-10
DE68926091D1 (en) 1996-05-02
EP0366036B1 (en) 1996-03-27
EP0366036A2 (en) 1990-05-02
JPH02216943A (en) 1990-08-29

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