EP0237539A1 - Device for controlling an integrated memory matrix imager and control method thereof. - Google Patents

Abstract

This device for controlling a matrix imager comprising a first family of n row conductors (Li) and a second family of m column conductors (Cj) conveying signals suitable for the excitation of an electrooptical display material at the image points (7) forming the integrated memory of the imager (9), comprises a first selection circuit (13) connected to n 'address lines (14) and to the n line conductors (Li) with n <= 2n', m read / write circuits (15) each connected to a column conductor (Cj) and grouped into k packets, each packet comprising at most l read / write circuits, with m, l and k integers such that 1 <= l < = m and 1 <= k <= m, each pie read / write circuit of a packet being connected to the same line of a bidirectional data bus (21) of l lines, with p integer such that 1 <= p <= l, and k processing circuits (17) each connected on the one hand to a packet of read / write circuits (15) and, on the other hand to a second e selection circuit (19) itself connected to k 'address lines (18) with K <= 2k'. Application to liquid crystal display devices.

Description

Device for controlling a matrix imager with integrated memory and its control method

The present invention relates to a device for controlling a matrix imager with integrated memory and its control method.

The invention applies in particular to any matrix imager with active matrix comprising an electro-optical display material of which an optical property such as an opacity, a refractive index, a transparency, an absorption, etc., can be changed with any excitation.

The invention applies particularly well to matrix imagers with liquid crystals without gray level, used for example as converters of electrical information into optical information, for the processing of optical images in real time, for analog display.

In the rest of the text, the example of the liquid crystal will be taken for clarity, it being understood that any other electro-optical material can be considered.

FIG. 1a represents, diagrammatically, a matrix imager with an active matrix, known and FIG. 1b, the control circuit associated with an elementary image point of this imager.

In FIG. 1a are shown first and second insulating walls 1, 3 facing each other, kept apart and sealed by a seal 2 disposed around their periphery. Between these walls 1, 3 is inserted a display material 4 having an optical property.

On the internal face of one of the walls 1 are distributed n parallel row conductors, denoted L _i and m parallel column conductors, denoted C _j , crossed with the row conductors, i and j being integers such as 1 ≤i≤n and 1≤j≤m; the row conductors and the column conductors convey electrical signals suitable for the excitation of the material 4.

At the crossing 11 of each row conductor L _i with each column conductor C _j is located a switch 5 such as a field effect transistor connected to an electrode E _ij and to the conductors L _i and C _j .

Furthermore, the internal face of the other wall 3 is covered with a conductive material serving as a counter electrode 10. This counter electrode is brought to a reference potential.

An image point I _ij is defined in this imager by the region of overlap of an electrode E _ij with the counter electrode 10, the electrode E _ij and the counter electrode 10 respectively forming the two armatures of a capacitor whose display material, in particular liquid crystal, interposed between these frames forms the dielectric.

In the particular case where the display material is a liquid crystal film, to avoid damaging it, the counter-electrode 10 is brought to a reference potential V _R whose value is periodically inverted and the conductors lines and the conductors columns convey electrical signals, for example of rectangular shape.

FIG. 1b represents in a known manner the electrical diagram of a control circuit associated with an image point I _ij , this being represented by a capacitor. Thus, at the crossing of a row conductor L. and a column conductor C _j is associated a field effect transistor 5, connected to one of the armatures of the capacitor corresponding to the electrode E _ij ; the other armature of this capacitor corresponding to the counter-electrode is brought to the reference potential V _R. This capacitor allows the memorization of information to display at image point I _ij .

When an electrical signal is applied to line L _i such that the resulting potential applied to the corresponding transistor 5 is greater than or equal to the threshold voltage of this transistor, the latter is in the on state; it then transmits the electrical signal applied to column C _j , to the electrode E _ij to which it is connected. When the electrical signal applied to line L _i is such that the resulting potential applied to the corresponding transistor 5 is less than the threshold voltage of transistor 5, this transistor is blocked regardless of the signal in column C _j and does not transmit any signal to the electrode E _ij , which will therefore retain its initial charge. It is the same for each elementary image point of the imager.

The column electrical signal transmitted to the electrode E _ij creates an electric field between the armatures of the capacitor constituted by the electrode E _ij and the counter electrode. This field causes a collective orientation of the liquid crystal molecules included between the armatures of the capacitor, when the transmitted signal is higher than a certain voltage, called threshold, corresponding to the minimum value necessary to excite the liquid crystal. By using the collective orientation and the punctual excitation of the liquid crystal molecules, one thus makes appear an image on the whole of the imager.

There are other types of active matrix matrix imagers. Thus, for example, document FR-A-2,553,218 describes another type of matrix imager, with active matrix. On the internal face of one of the walls of this imager are arranged parallel column conductors connected to parallel column electrodes and on the internal face of the other wall of this imager are arranged line conductors lèles connected by transistors to electrodes distributed in a matrix opposite the column electrodes, said transistors being further connected to a reference potential V _R.

An image point of this imager is defined by the area of overlap of an electrode with a column electrode, these two electrodes respectively forming the two plates of a capacitor.

The electrical diagram of the control circuit associated with an image point of such an imager differs from that shown in FIG. 1b by the position of the capacitor. In fact, the capacitor is in this case connected between the column conductor and the transistor, the latter being moreover connected to the corresponding line conductor and to the reference potential V _R.

The signals applied to the line conductors and the column conductors of the matrix imagers, such as those described above, come from a control device.

A control device comprises, in known manner, an image memory external to the imager connected via interfaces to control means such as a computer, an image controller connected to the image memory external, by means of logic circuits, circuits for processing serial video signals connected to the image controller and circuits for processing video signals connected to these processing circuits.

The computer manages the various elements of the control device and transmits the information to be displayed to the external image memory.

The image controller scans the information stored in the external image memory. The processing circuits transmit to the signal processing circuits vi deo, developed from the signals provided by the image controller. These processing circuits make it possible to transcribe the video signals from means such as shift registers, into line signals and into column signals. The latter are transmitted respectively to the line conductors and to the column conductors, so as to obtain a point-by-point display of the imager.

This control device only allows information to be written to the image points of the imager. To refresh information at an image point, it is rewritten by taking the corresponding information from the external image memory and not from the image point itself. The refresh is carried out every 20 milliseconds and therefore the frequency of the video signal which contains the information to be displayed in series must be fast of the order of 5 MHz. Consequently, the control device must be produced in rapid technology, that is to say in monocrystalline silicon, which has the drawbacks of making its manufacture complex and its high manufacturing cost.

There are also control devices whose image memory is integrated into the imager, making it possible to write but also to read and refresh information in image points of the imager.

Such a device is for example described in the document GB-A-2 113 444.

The subject of the invention is a new control device, the image memory of which is integrated into the imager, making it possible in particular to remedy the aforementioned drawbacks and in particular to be achievable in technology both fast and slow.

The control device of the invention applies to all matrix imagers, with matrix active, and in particular to those described above.

More specifically, the invention relates to a device for controlling a matrix imager comprising nm image points arranged in a matrix, a first family of n row conductors and a second family of m column conductors carrying signals suitable for excitation of an electrooptical display material, each image point of the imager, formed of a capacitor whose dielectric consists of the display material, being associated with a line conductor, a column conductor and a switch, each image point constituting an imager point memory in which one can write, read and refresh information, characterized in that this control device comprises m read / write circuits each connected to a column conductor for writing, reading and refreshing information at the image points associated with said column conductor, said read / write circuits being grouped into k packets, each packet uet comprising at most l read / write circuits, with m, l and k integers such as 1≤l≤m and 1≤k≤m, the read / write circuit packets being connected to a bidirectional data bus of l lines, the p ^th read / write circuit of a packet being connected to the p ^th line of said bus, with p integer such that 1 ≤p≤ l, the read, write and refresh operations performed by the circuits read / write being selected from control signals.

In the case where k and l are multiples of m, all the packets preferably have the same number l of read / write circuits (m = lk). Otherwise, all the packets do not have the same number of read / write circuits and in particular one of these packets has a number of read / write circuits lower than that of the other packets. According to a preferred embodiment, the control device comprises processing means comprising k processing circuits each connected to a packet of read / write circuits, the read, write and refresh operations performed by the read circuits / write being selected via the processing circuits receiving the control signals and sending selection signals to the read / write circuits.

Advantageously, the control device comprises a first selection circuit such as a decoder connected at the input to n 'address lines and at the output to the n line conductors with n ≤2 ^n' , for selecting a single line conductor to that time.

Preferably, the control device comprises a second selection circuit such as a decoder connected at the input to k 'address lines and at the output to the k processing circuits with k ≤2 ^k' to select a single packet of conductors. columns by choosing one processing circuit at a time.

According to one embodiment of the device, each line of the bidirectional data bus comprises a single conductor capable of conveying information in two opposite directions.

According to an alternative embodiment of the device, each line of the bidirectional data bus comprises a first and a second conductor capable of conveying information respectively in a first and a second direction, said first and second directions being opposite.

The control device according to the invention does not use an external image memory, which has the consequence of simplifying its production. In addition, the display made in several image points at the same time allows a realization in slow technology, that is to say in amorphous silicon.

According to another preferred embodiment of the control device, the switch is a transistor.

According to one embodiment of the control device, each read / write circuit comprises:

writing means comprising, in the direction of information transfer, a first processing circuit and a first amplifier linked together,

reading means connected in parallel to the writing means, these reading means comprising, in the direction of information transfer, a second amplifier connected both to a storage device and to a second processing circuit, the storage device being further connected to the first processing circuit to allow the refreshment of the information read and stored.

The role of the first processing circuit is to transmit either information from the data bus to the first amplifier, or information from the storage device to the first amplifier, as a function of the selection signals received by this circuit.

The role of the second processing circuit is to transmit the information read to the data bus. Furthermore, this circuit optionally makes it possible to adapt the electrical signal corresponding to the information read to an electrical signal of binary type compatible with the logic levels of the external electronics, disposed at the output of the data bus. This second processing circuit comprises for example a window comparator.

According to a preferred embodiment of the control device, the first processing circuit of each read / write circuit comprises a pre mier transistor connected to the first amplifier, used to transfer information to be written to this first amplifier, and a second transistor connected on the one hand to the first transistor and to the amplifier and, on the other hand, to the storage device, this second transistor used to transfer information read to refresh (in other words to rewrite) to this first amplifier.

According to another preferred embodiment of the control device, the memory device for each read / write circuit comprises a transistor and a capacitor connected together, the transistor being further connected to the second processing circuit and to the second amplifier and, the capacitor being further connected to the first processing circuit.

According to another preferred embodiment of the control device, one of the first and second amplifiers of each read / write circuit is an inverting amplifier used to apply an alternating signal to the image points.

The invention also relates to a device for controlling a matrix imager comprising nm image points arranged in a matrix, a first family of n row conductors and a second family of m column conductors carrying signals suitable for the excitation of a electrooptical display material, each image point of the imager, formed of a capacitor, the dielectric of which consists of the display material being associated with a line conductor, a column conductor and a switch, each image point constituting a memory point of the imager in which one can write, read and refresh information, characterized in that this control device comprises m read / write circuits con each connected to a column conductor to write, read and refresh information at the image points associated with said column conductor, said read / write circuits being connected to a bidirectional data bus, the read, write and refresh operations performed by the read / write circuits being selected from control signals, each read / write circuit comprising:

writing means comprising, in the direction of information transfer, a first processing circuit and a first amplifier linked together,

reading means connected in parallel to the writing means, these reading means comprising, in the direction of information transfer, a second amplifier connected both to a storage device and to a second processing circuit, the storage device being further connected to the first processing circuit to allow the refreshment of the information read and stored.

The first and second processing circuits of each read / write circuit have the same function as those described above; they therefore preferably include the same elements. The same is true for the other elements of the read / write circuit.

According to a preferred embodiment, this control device comprises processing means connected to the read / write circuits, the read, write and refresh operations performed by the read / write circuits being selected by means of the processing means receiving the control signals and sending selection signals to the read / write circuits.

According to another preferred embodiment, the m read / write circuits are grouped into k packets, each packet comprising at most l read / write circuits, with m, l and k integers such as 1≤l≤m and 1≤k≤m, the data bus comprising l lines, the p ^th read / write circuit of a packet being connected to the p ^th line of said bus with p integer such that 1 ≤p≤l. Advantageously, the device according to the invention comprises in this case, processing means comprising k processing circuits each connected to a packet of read / write circuits, the read, write and refresh operations performed by the read / write circuits being selected via the processing circuits receiving the control signals and sending selection signals to the read / write circuits.

Preferably, this control device comprises a first selection circuit connected at the input to n 'address lines and at the output to the n line conductors, with n≤2 ^n' , for selecting only one line conductor at a time.

In addition, this control device advantageously comprises a second selection circuit connected at the input to address lines and at the output to the processing means for selecting at least one column conductor at a time.

When the read / write circuits are grouped into packets, this second selection circuit makes it possible to select one packet of column conductors at a time and, if not, it selects only one column conductor at a time.

The invention also relates to a method for controlling a device according to the invention, characterized in that to read information at an image point of the imager by transmitting it from the image point to data bus via the read / write circuit corresponding to this image point or to write information at this image point by transmitting it in the opposite direction, both the row conductor and the column conductor corresponding to this point are selected image and to read information at an image point of the imager by transmitting it from the image point to the corresponding read / write circuit or to refresh information at this image point by transmitting it in the opposite direction, at least the line conductor is selected corresponding to this image point, these read, write and refresh operations being selected from the control signals.

Other characteristics and advantages of the invention will emerge more clearly from the description which follows, given purely by way of non-limiting illustration.

The description is made with reference to Figures 1a to 5 attached in which:

FIGS. 1a and 1b, already described, show diagrammatically, respectively, a matrix imager with active matrix of known type and the electrical diagram of the control circuit of an image point of this imager,

FIG. 2 represents a block diagram of an example of a control device according to the invention of a matrix imager,

- Figure 3 shows an example of a read / write circuit according to the invention of an image point of the imager, said circuit being associated with the control circuit of this image point, Figure 4a represents an example timing diagram of signals applied to a row conductor and to a column conductor and the resulting signal applied at the corresponding image point, during a writing operation according to the invention, FIG. 4b represents a timing diagram of example signals applied to a row conductor, to a column conductor and at the corresponding image point, during an operation of reading according to the invention, and

- Figure 5 shows an example of a processing circuit of the control device according to the invention.

FIG. 2 shows a matrix imager 9 comprising nm elementary image points. Each image point is associated with a line conductor L _i , with a column conductor C _j , with i and j integers such as 1 ≤i ≤n and 1 ≤j≤m, and with a switch such as a transistor with effect of field.

This imager is for example of the same type as those described above.

In FIG. 2, each assembly constituted by an image point and the switch associated with this image point bears the reference 7. Furthermore, for simplicity, the reference potential V _R has not been shown.

The control device shown in FIG. 2 comprises a first selection circuit 13 such as a decoder connected to n 'address lines 14 and to the n line conductors, denoted L _i , with n ≤2 ^n' . The m column conductors, denoted C _j , are grouped for example into k packets of l column conductors each, each column conductor C. being connected to a read / write circuit 15. The m column conductors and their corresponding read / write circuits 15 are grouped into k packets of l column conductors and l circuits 15, by means of processing means comprising processing circuits 17, one processing circuit 17 per packet of the column conductors and of the read / write circuits 15. There is therefore k processing circuits 17 in this control device.

Each read / write circuit 15 of a packet is connected to the processing circuit 17 corresponding to this packet by a bus 12. Furthermore, each read / write circuit 15 of a packet is connected to a line of a bus 21 of bidirectional data of l lines, the p ^th read / write circuit of a packet being connected to the p ^th line of bus 21, with p integer such that 1 ≤p ≤ l. Each read / write circuit is connected to the corresponding line of the bus 21, by a bidirectional conductor 16 or by two conductors capable of conveying information in opposite directions from one another. In the rest of the text, we will take the particular example of a bidirectional conductor 16.

Each line of the bidirectional bus 21 comprises a single conductor capable of conveying information in two opposite directions or else a first and a second conductor capable of conveying information respectively in a first and a second direction, the first and second directions being opposite.

Each processing circuit 17 is further connected to control means (not shown) such as a computer by a bus 20 and to a second selection circuit 19 such as a decoder. This second selection circuit 19 is connected at the input to k 'address lines 18 and at the output to the k processing circuits by the conductors 18', with k ≤2 ^{k '} .

The first and second selection circuits 13 and 19 are produced from logic gates according to known principles. These circuits are for example of the same type as those described in the document DEA-3 101 987. On the other hand, examples of processing and read / write circuits 15 will be described in more detail, with reference to FIGS. 3 to 5.

Each image point I _ij of the imager, represented smelled by a capacitor, has the capacity to memorize information. All of these capacitors constitute an image memory integrated into the imager, in which information can be written, read and refreshed.

Each refresh operation of the information at the image points of the imager is preceded by an operation of reading this information at these image points. These read and refresh operations can be carried out simultaneously on all the image points of a line of points corresponding to a selected line conductor. During these read and refresh operations, the information is conveyed from the image points to the corresponding read / write circuits and vice versa.

The read operations at the image points of the imager making it possible to transmit information from the image points to the data bus 21 via the corresponding read / write circuits and the write operations at the image points of the imager making it possible to transmitting information from the data bus 21 to the image points via the corresponding read / write circuits can be carried out independently. Furthermore, these read or write operations can only be carried out at the same time in a limited number of image points corresponding to the image points associated with both a selected column conductor packet and a selected row conductor. It is understood that the read operations making it possible to transmit information from the image points to the bus 21 can be followed by operations for refreshing this information at these image points, since this information is transmitted via the circuits of readind, writing. Thus, when a line conductor L _i and a packet of l column conductors C _j , C _{j + 1} , ... C _{j + l} are selected, the information contained in all the image points corresponding to the line conductor L _i can be read, the information read being transferred to the read / write circuits. The information read at the ima.ges points I _ij , I _{i j + 1} , ... I _{i j + l} associated with both the row conductor and the selected column conductors can be transferred to bus 21 and information from this bus can be written at these image points, in other words, the information from the p ^th image point can be transmitted to the p ^th data line 'of the bus 21 with p integer such that 1 ≤P≤ l and the information to be written, carried by the p ^th bus data line can be transmitted to the p ^th column conductor of the selected packet and displayed in this p ^th image point. On the other hand, the information read at the other image points associated with the selected row conductor and the unselected column conductors can be rewritten in these image points.

By periodically selecting each line conductor, it is possible to periodically read and refresh the information contained at the image points of the imager by transmitting the information from the image points to the corresponding read / write circuits, and vice versa; moreover, in the case where column conductors are selected, it is possible to read or write information at the image points corresponding to both the line conductors and the selected column conductors, by transmitting the information from the image points to the data bus or the reverse, through the read / write circuits.

The following description provides a better understanding of the operation of such a device.

To select a line conductor L _i , send, from control means such as a cal culateur (not shown), electrical signals on the n 'address lines 14 at the input of the selection circuit 13. A zero signal corresponds to the binary element "0" and a non-zero signal to the binary element "1 ". The selection circuit 13 will therefore select from the n 'parallel signals of the n' address lines 14, a single line conductor L. from among the n line conductors which are connected to it. The selection circuit 13 therefore sends to the selected line conductor L _i an electrical signal such that the resulting potential applied to the transistors 5 connected to this conductor is greater than or equal to the threshold voltage of the transistors 5, and to the other line conductors an electrical signal such that the resulting potential applied to the transistors connected to these conductors is less than this threshold voltage. All the transistors 5 connected to the conductor lig.ne L _i selected, will therefore be in the on state, while the other transistors 5 associated with the other line conductors will be blocked.

Likewise, to select a packet of l column conductors C _j , ... C _{j + l} , we send from the control means to the input of the selection circuit 19, k 'parallel signals via the k address lines 18. The selection circuit 19 will then select a processing circuit 17 from among the k processing circuits 17 of the device which are connected to it.

Each processing circuit 17 prepares read, write or refresh selection signals, as a function of the signals from the selection circuit 19 and the control signals (read / write / refresh) from the control means and conveyed by the bus 20. These selection signals are then sent to the read / write circuits 15 which are connected to it by the buses 12. FIG. 3 shows in detail an example of a read / write circuit 15 connected to a control circuit of the same type as that described in FIG. 1b, it being understood, as we have seen previously, that any other control circuit an active matrix matrix imager can be used.

A read / write circuit 15 comprises, in the direction of transfer of information, coming from a line of the data bus 21, from the conductor 16 to the corresponding column conductor C _j , during a write operation, a first processing circuit 25 connected to an amplifier 27. Similarly, a read / write circuit comprises in parallel, in the direction of information transfer from a column conductor C _j to the corresponding conductor 16, during a read operation, an inverting amplifier 29 connected to a second processing circuit 33 and a storage device 31 connected to both the inverting amplifier 29 and to the second processing circuit 33. The storage device 31 is further connected to the first processing circuit 25.

The information to be written, read or rewritten at an image point I _ij consists of the potential difference applied between the plates of the capacitor corresponding to this image point.

In the example of the read / write circuit shown in FIG. 3, the first processing circuit 25 is produced by two transistors 24, 26 connected so as to constitute a switch; the storage device 31 is made by a transistor 30 and a capacitor 32. The second processing circuit 33 is made for example by a window comparator well known to those skilled in the art, formed for example by an amplifier against -reacted or else logic gates and dividing bridges; he can be also produced by any device making it possible, from the information read, to determine the state of the corresponding image point, in other words to transform the information read into an electrical signal of the binary type compatible with the external electronics connected to the bus 21, ( a zero electrical signal corresponds to a non-displayed state and a non-zero electrical signal to a displayed state).

The capacitor 32 is connected on the one hand to the transistor 30 and to the transistor 26 and, on the other hand, to ground; in addition, the transistor 30 is connected to both the processing circuit 33 and the amplifier 29, and the transistor 26 is connected to both the transistor 24 and the amplifier 27.

The signals for selecting a write operation or an operation for updating information at the image point I _ij , and the signals for selecting a read operation at this image point I _ij are produced by the circuit 17 associated with the read / write circuit 15. These selection signals are constituted by electrical signals applied to the circuit 15, at E and at 37 for a write operation, at L and at 35 for a read transfer operation the image point information on the bus 21 by the read / write circuit, in R and in 37 for a refresh operation and in L for a read operation transmitting the information from the image point to the read / write circuit and more precisely to the capacitor 32 of the storage device.

To perform a write operation to the image point I _ij, corresponding to a row conductor L _i and a column conductor C _j, therefore selects the row conductor L _i and the column conductor C _j. The transistor 5 associated with this image point is then at the passing state. Furthermore, a non-zero electrical signal is sent at E to the transistor 24 of the processing circuit 25 and a non-zero electrical signal at 37 to the amplifier 27 so that the transistor 24 and the amplifier 27 are at passing state. The information conveyed in the form of an electrical signal by the conductor 16 and coming from the corresponding line of the data bus 21 will pass through the transistor 24 then be amplified by the amplifier 27 before being transmitted to the conductor C _j . The transistor 5 being in the on state, the signal will be transmitted to the capacitor corresponding to the image point I _ij , by this transistor 5. Between the armatures of the capacitor, there is then established a potential difference proportional to the transmitted signal, this potential difference will create an electric field which will therefore excite the molecules of the liquid crystal interposed between the armatures of this capacitor.

The information displayed at this point I _ij therefore depends on the signal transmitted by the line of the bidirectional data bus 21.

To read information at image point I _ij and transfer it to the corresponding bus line 21, select the corresponding line conductor and column conductor and send a non-zero electrical signal at 35 on the processing circuit 33 and a non-electrical signal zero in L on the transistor 30 of the storage device 31 so as to make pass the circuit 33 and the transistor 30. The information contained by the capacitor I _ij , in the form of an electric field, is transferred to the inverting amplifier 29, the amplifier 27 being in a high impedance state because it has not received an electrical signal at 37. At the output of the amplifier 29, the signal from the capacitor is inverted and transmitted on the one hand to the device storage 31 and, on the other hand, to the circuit 33. The transistor 30 of the storage device being in the on state, it therefore transmits to the capacitor 32 the signal read in order to temporarily store the information contained by this signal. On the other hand, the processing circuit 33, also in the on state, will transmit the signal read to the corresponding line of the bidirectional data bus 21 via the conductor 16.

To read information at the image point I _ij corresponding to a row conductor L _i and to a column conductor C _j and to transfer it to the capacitor 32, it suffices to select the corresponding row conductor, (the column conductor C _j may or may not be selected ), and to send a non-zero electrical signal at L on the transistor 30 so as to make it conducting. This transistor 30 then transmits the information read to the capacitor 32.

The information contained in, the capacitor 32, in the form of an electric field, makes it possible to refresh the corresponding image point, by rewriting this stored information. Thus, to rewrite information, at the image point I _ij , it suffices to select the corresponding line conductor L _i (the column conductor C _j may or may not be selected) and to send a non-zero electrical signal at R to make the transistor 26 of the processing circuit 25 and a non-zero electrical signal at 37 to turn on the amplifier 27. The transistors 24 and 30 being blocked, the information will therefore pass through the transistor 26 and through the amplifier 27 before be transmitted to the corresponding column conductor C _j . The information initially contained in the capacitor I _ij , in the form of an electrical signal, will be rewritten with reverse polarity due to the signal inversion effected by the inverting amplifier 29.

The amplifier 29 has been chosen inverter, but we could just as easily have taken the inverting amplifier 27 and the non-inverting amplifier 29. Each time the information is refreshed, the polarity of the corresponding signal will be reversed; the application of an alternating signal to the capacitor I _ij thus makes it possible to extend the life of the display material, such as the liquid crystal, interposed between the frames of this capacitor. The refresh is carried out for example over a period of approximately 20 ms.

The timing diagrams of FIGS. 4a and 4b show examples of excitation signals V _{L i} , V _Cj applied respectively to a row conductor L _i and to a column conductor C _j during a writing operation (FIG. 4a) and during of a reading operation (FIG. 4b) of information at the corresponding image point, and the resulting signals V _ij at the image point. The excitation signals shown in this figure are rectangular impulse signals, but other signals such as sinusoidal signals could also have been applied.

The signal V _{L i} applied to the line conductor L _i is not zero during a time T called line time, equal to the addressing period T divided by the number of line conductors, n, of the device. Outside this line time T _L , the signal V _{L i} is zero. The transistors associated with the line conductor L _i are therefore in the on state only during the non-zero pulse of the signal V _Li , that is to say during a time T _L. Thus, during a writing operation (FIG. 4a), the transistor 5 associated with the image point I _ij corresponding to a row conductor L _i and to a column conductor C _j being in the on state, it transmits the signal V _Cj applied to column C _j , to capacitor I _ij corresponding to the image point. When the signal V _Cj is not zero, it is established between the armatures of the con densifier a potential difference equal to the signal V _Cr. -V _R. The resulting signal V _ij seen by the liquid crystal therefore has an equal amplitude V _Cj -V _R. Throughout the duration of the addressing time T, the armatures of the capacitor remain charged, the corresponding image point therefore keeps during this time T the information written during the line time T _L , except for charge leaks.

A refresh operation consists in writing the information read. It therefore takes place as before, the signals V _Cj and V _ij will be the same but of opposite polarity to that of the previous period.

During a read operation (FIG. 4b), as for a write or refresh operation, the transistor associated with the image point, from which the information must be read, must be in the on state. The read operation is therefore carried out when the signal V _Li applied to the line conductor L _i is not zero.

An equal partition of the charge C _ij (image of the signal V _ij ) contained by the capacitor I _ij , in this same capacitor and in a possible parasitic capacitance associated with the column conductor C _j , produces a signal V _{C j} which is then transferred by the column conductor C _j at the read / write circuit 15. After reading the signal V _ij contained by the capacitor, the potential difference between the plates of this capacitor is not zero; it decreases by a maximum level 40 obtained during a write operation to an equal value V _Cj -V _R.

FIG. 5 represents an example of a processing circuit 17 of a control device according to the invention.

This circuit 17 comprises a logic gate 51 such as an AND gate with two inputs and a logic gate 53 such as a NOR gate also with two in very. The two inputs of door 51 are connected respectively by a conductor 45 'to the corresponding conductor 18' of the selection circuit 19 and to the bus 20 by a conductor 41. The two inputs of door 53 are respectively connected to the output of the door 51 and to the bus 20 via a conductor 43. Furthermore, this circuit 17 comprises a conductor 45 connected to the selection circuit 19 via the corresponding conductor 18 'and two conductors 47 and 49 respectively connected to the bus 20.

At the output, the conductor 45, the door 51, the door 53, the conductor 47 and the conductor 49 are connected respectively at 35, E, R, L and 37 of all the read / write circuits associated with this processing circuit.

The signals applied at L and at 37 conveyed by the conductors 47 and 49 do not depend on the output signal from the selection circuit 19; therefore, these signals are identical for all of the read / write circuits of the control device and depend solely on the control signals.

The control signals conveyed by the conductors 47 and 49 do not undergo electronic processing in the circuit 17 shown in FIG. 5, but of course, this example is not limiting; one could indeed use in circuit 17 other elements to process said signals.

For clarity in the description, the electrical signals will be assimilated to binary type levels, high level "1" and low level "0".

The electrical signals sent to conductors 41, 43, 47 and 49 by bus 20 depend on the operations to be validated and the signal conveyed by conductors 45 and 45 'corresponds to a high level when the processing circuit is selected and to a level low otherwise. To validate an operation for reading the data from the image points to the read / write circuits, the conductor 47 must convey a signal at a high level "1". To validate an operation for reading the data from the image points to the data bus 21 via the read / write circuits, the conductors 47 and 45 must respectively carry a signal at the high level. To validate a data write operation, from the data bus 21 to the image points by the read / write circuits, the signals conveyed by the conductors 45 ′ and 41 must both be high for the output signal of door 51 is at the high level. To validate a refresh operation, the output signal from door 51 must be at the low level as well as the signal conveyed by the conductor 43 so that the output signal from door 53 is at high level. In addition, to validate a write or refresh operation, the conductor 49 must convey a signal at a high level.

Thus, with this circuit 17, when a write operation is validated, a refresh operation cannot be validated. On the other hand, when a write operation is not validated, in particular in the case where the processing circuit is not selected, and the signal of the conductor 43 is at the low level, the refresh operation can be validated.

The control device according to the invention can be easily integrated into a conventional imager with attached devices.

In addition, because of the integration of the image memory with the imager, it makes it possible to save in particular an image memory external to the imager, a screen controller, circuits of video signals used in communication devices known command. It also allows the information contained in this integrated memory to be read, and therefore the information read to be refreshed. In addition, the writing operations being able to be carried out in l image points at the same time and the refreshment in m image points at the same time, the device according to the invention can be produced in slow technology and in particular in amorphous silicon.

The above description, made with reference to the selection of column conductors per packet is not limiting, in fact, the control device according to the invention also applies to column conductors selected in a unitary manner.

Furthermore, the examples of the various circuits described above of the device according to the invention are not limiting. Indeed, other modifications can be made to these circuits without departing from the scope of the invention. The bidirectional data bus 21 could in particular have been connected to the read / write circuits 15 via the processing circuits 17, these circuits 17 would then have transferred the information from the bus 21 to the read / write circuits 15 and vice versa. In addition, the selection circuits 13, 19 described in FIG. 2 are not essential for the operation of the device according to the invention, they make it possible to reduce the number of connections.

Claims

CLAIMS 1. Device for controlling a matrix imager (9) comprising nm image points arranged in a matrix, a first family of n row conductors (L _i ) and a second family of m column conductors (C _j ) carrying signals suitable for the excitation of an electrooptical display material, each image point (I _ij ) of the imager, formed of a capacitor whose dielectric consists of the display material being associated with a line conductor (L _i ), to a column conductor (C _j ) and to a switch (5), each image point constituting an imager point memory in which one can write, read and refresh information, characterized in that this control device comprises m circuits read / write (15) each connected to a column conductor (C _j ) to write, read and refresh information at the image points associated with said column conductor (C _j ), said read / write circuits (15) being reg grouped into k packets, each packet comprising at most l read / write circuits, with m, l and k integers such as 1≤l≤m and 1 <k <m, the packets of read / write circuits being connected to a bi-directional data bus (21) of l lines, the p read / write circuit of a packet being connected to the p ^th line of said bus, with p integer such that 1 ≤p ≤l, the read operations, write and refresh performed by these read / write circuits (15) being selected from control signals (20).

2. Control device according to claim 1, characterized in that it comprises processing means comprising k processing circuits (17) each connected to a packet of read / write circuits (15), the read operations, d writing and refreshing by the circuits of read / write being selected via the processing circuits receiving the control signals (20) and sending selection signals (35, E, R, L, 37) to the read / write circuits.

3. Control device according to claim 1, characterized in that it comprises a first selection circuit (13) connected at the input to n 'address lines (14) and at the output to the n line conductors (L _i ), with n ≤2 ^{n '} , to select only one line conductor at a time.

4. Control device according to claim 2, characterized in that it comprises a second selection circuit (19) connected at the input to k 'address lines (18) and at the output to the k processing circuits (17), with k≤2 ^{k '} to select a single packet of column conductors (C _j ) by choosing one processing circuit (17) at a time.

5. Control device according to claim 1, characterized in that each read / write circuit (15) comprises:

- writing means (25, 27) comprising, in the direction of information transfer, a first processing circuit (25) and a first amplifier (27) connected together, - reading means (29, 31, 33) connected in parallel to the writing means, these reading means comprising, in the direction of information transfer, a second amplifier (29) connected both to a storage device (31) and to a second processing circuit (33), the storage device being further connected to the first processing circuit (25) to allow the refreshment of the information read and stored, the first processing circuit making it possible to transmit information from the data bus or from the storage device to the first amplifier and the second processing circuit This allows information to be transmitted from the second amplifier to the data bus.

6. Control device according to claim 5, characterized in that the first processing circuit (25) comprises a first transistor (24) connected to the first amplifier (27), serving to transfer information to be written to this first amplifier , and a second transistor (26) connected on the one hand to the first transistor (24) and to the amplifier (27) and, on the other hand, to the storage device (31), this second transistor (26) serving to transfer information read to refresh to this first amplifier.

7. Control device according to claim 5, characterized in that the storage device (31) comprises a transistor (30) and a capacitor (32) connected together, the transistor being further connected to the second processing circuit (33 ) and the second amplifier (29) and the capacitor (32) being further connected to the first processing circuit (25).

8. Control device according to claim 5, characterized in that one of the first and second amplifiers (27, 29) is an inverting amplifier used to apply an alternating signal to the image points.

9. Device for controlling a matrix imager (9) comprising n.m image points arranged in a matrix, a first family of n line conductors

(L _i ) and a second family of m column conductors (C _j ) conveying signals suitable for the excitation of an electrooptical display material, each image point (I _ij ) of the imager, formed of a capacitor the dielectric of which consists of the display material being associated with a line conductor (L _i ), a column conductor (C _j ) and a switch (5), each image point constituting a memory point of the Imager in which one can write, read and refresh information, characterized in that this control device comprises m read / write circuits (15) each connected to a column conductor (C _j ) for writing, reading and updating information at the image points associated with said column conductor (C _j ), said read / write circuits (15) being connected to a bidirectional data bus (21), the read, write and of refreshment performed by the read / write circuits (15) being selected from control signals (20), each read / write circuit comprising:

writing means (25, 27) comprising, in the direction of information transfer, a first processing circuit (25) and a first amplifier (27) linked together,

- reading means (29, 31, 33) connected in parallel to the writing means, these reading means comprising, in the direction of information transfer, a second amplifier (29) connected at the same time to a device for storage (31) and a second processing circuit (33), the storage device being further connected to the first processing circuit (25) to allow the refreshment of the information read and stored, the first processing circuit making it possible to transmitting information from the data bus or the storage device to the first amplifier and the second processing circuit making it possible to transmit information from the second amplifier to the data bus.

10. Control device according to claim 9, characterized in that it comprises processing means (17) connected to the read / write circuits (15), the read, write and refresh operations performed by the circuits of read re / write being selected by the processing means receiving the control signals and sending selection signals (35, E, R, L, 37) to the read / write circuits.

11. Control device according to claim 9, characterized in that the m read / write circuits are grouped into k packets, each packet comprising at most l read / write circuits, with m, l and k integers such that 1 ≤ l≤m and 1≤k≤m, the data bus (21) comprising l lines, the p ^th read / write circuit of a packet being connected to the p ^th line of said bus with p integer such that 1 ≤p ≤ l.

12. Control device according to claim 11, characterized in that it comprises processing means comprising k processing circuits (17) each connected to a packet of read / write circuits (15), the read operations, d write and refresh performed by the read / write circuits being selected via the processing circuits receiving the control signals (20) and sending selection signals (35, E, R, L, 37) to the circuits read / write.

13. Control device according to claim 9, characterized in that it comprises a first selection circuit (13) connected at the input to n 'address lines (14) and at the output to the n line conductors (L _i ), with n ≤2 ^{n '} , to select only one line conductor at a time.

14. Control device according to any one of claims 10 and 12, characterized in that it comprises a second selection circuit (19) connected at the input to address lines (18) and at the output to the processing means. (17) to select at least one column conductor (C _j ) at a time.

15. Control device according to claim 9, characterized in that the first circuit of processing (25) comprises a first transistor (24) connected to the first amplifier (27), used to transfer information to be written to this first amplifier, and a second transistor (26) connected on the one hand to the first transistor (24) and to the amplifier (27) and, on the other hand, to the storage device (31), this second transistor (26) serving to transfer information read to be refreshed, to this first amplifier.

16. Control device according to claim 9, characterized in that the storage device (31) comprises a transistor (30) and a capacitor (32) connected together, the transistor being further connected to the second processing circuit (33 ) and the second amplifier (29) and the capacitor (32) being further connected to the first processing circuit (25).

17. Control device according to claim 9, characterized in that one of the first and second amplifiers (27, 29) is an inverting amplifier used to apply an alternating signal to the image points.

18. Method for controlling the control device according to any one of claims 1 and 9, characterized in that to read information at an image point (I _ij ) of the imager by transmitting it from the image point to the bus (21 ) of data via the read / write circuit (15) corresponding to this image point, or to write information at this image point by transmitting it in the opposite direction, both the line conductor (L _i ) is selected and the column conductor (C _j ) corresponding to this image point and for reading information at an image point of the imager by transmitting it from the image point to the corresponding read / write circuit or for updating information at this image point by transmitting in sense inverse, at least the line conductor corresponding to this image point is selected, these read, write and refresh operations being selected from the control signals.