EP0226892A3 - Process for manufacturing of bipolar and complementary mos-transistors on a common silicon substrate - Google Patents

Process for manufacturing of bipolar and complementary mos-transistors on a common silicon substrate Download PDF

Info

Publication number
EP0226892A3
EP0226892A3 EP19860116739 EP86116739A EP0226892A3 EP 0226892 A3 EP0226892 A3 EP 0226892A3 EP 19860116739 EP19860116739 EP 19860116739 EP 86116739 A EP86116739 A EP 86116739A EP 0226892 A3 EP0226892 A3 EP 0226892A3
Authority
EP
Grant status
Application
Patent type
Prior art keywords
bipolar
transistors
manufacturing
process
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19860116739
Other versions
EP0226892B1 (en )
EP0226892A2 (en )
Inventor
Hans-Christian Dr. Schaber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248Combination of bipolar and field-effect technology
    • H01L21/8249Bipolar and MOS technology
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/009Bi-MOS
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90MOSFET type gate sidewall insulating spacer
EP19860116739 1985-12-17 1986-12-02 Process for manufacturing of bipolar and complementary mos-transistors on a common silicon substrate Expired - Lifetime EP0226892B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE3544599 1985-12-17
DE3544599 1985-12-17

Publications (3)

Publication Number Publication Date
EP0226892A2 true EP0226892A2 (en) 1987-07-01
EP0226892A3 true true EP0226892A3 (en) 1989-12-06
EP0226892B1 EP0226892B1 (en) 1993-09-08

Family

ID=6288653

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860116739 Expired - Lifetime EP0226892B1 (en) 1985-12-17 1986-12-02 Process for manufacturing of bipolar and complementary mos-transistors on a common silicon substrate

Country Status (3)

Country Link
US (1) US4752589A (en)
EP (1) EP0226892B1 (en)
JP (1) JPS62155553A (en)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3230077A1 (en) * 1982-08-12 1984-02-16 Siemens Ag Integrated bipolar and MOS transistors containing semiconductor circuit on a chip and process for their preparation
DE3745036C2 (en) * 1986-02-28 1996-05-15 Canon Kk Bipolar transistor combined with FET or photodiode
DE3706278C2 (en) * 1986-02-28 1993-09-09 Canon K.K., Tokio/Tokyo, Jp
US4962053A (en) * 1987-01-30 1990-10-09 Texas Instruments Incorporated Bipolar transistor fabrication utilizing CMOS techniques
US4902640A (en) * 1987-04-17 1990-02-20 Tektronix, Inc. High speed double polycide bipolar/CMOS integrated circuit process
JPS63304657A (en) * 1987-06-04 1988-12-12 Fujitsu Ltd Manufacture of semiconductor device
KR900001062B1 (en) * 1987-09-15 1990-02-26 강진구 Manufacture of bicmos
EP0312965B1 (en) * 1987-10-23 1992-12-30 Siemens Aktiengesellschaft Method of producing a planar self-aligned heterojunction bipolar transistor
US5017995A (en) * 1987-11-27 1991-05-21 Nec Corporation Self-aligned Bi-CMOS device having high operation speed and high integration density
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
KR930008899B1 (en) * 1987-12-31 1993-09-16 문정환 Manufacturing method of semiconductor device
US5124817A (en) * 1988-01-19 1992-06-23 National Semiconductor Corporation Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5179031A (en) * 1988-01-19 1993-01-12 National Semiconductor Corporation Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5001081A (en) * 1988-01-19 1991-03-19 National Semiconductor Corp. Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
DE68911321T2 (en) * 1988-01-21 1994-07-07 Exar Corp A method of manufacturing a complementary BiCMOS transistor with isolated vertical PNP transistor.
US5293077A (en) * 1988-02-29 1994-03-08 Hitachi, Ltd. Power switching circuit
JPH01270260A (en) * 1988-04-21 1989-10-27 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH025464A (en) * 1988-06-24 1990-01-10 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPH025463A (en) * 1988-06-24 1990-01-10 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JP2549726B2 (en) * 1989-01-30 1996-10-30 株式会社東芝 The semiconductor integrated circuit and a manufacturing method thereof
US4918026A (en) * 1989-03-17 1990-04-17 Delco Electronics Corporation Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip
US5091760A (en) * 1989-04-14 1992-02-25 Kabushiki Kaisha Toshiba Semiconductor device
GB8913904D0 (en) * 1989-06-16 1989-08-02 Philips Nv A method of manufacturing a semiconductor device
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
EP0414013A3 (en) * 1989-08-23 1991-10-16 Texas Instruments Incorporated Method for forming bipolar transistor in conjunction with complementary metal oxide semiconductor transistors
US4960726A (en) * 1989-10-19 1990-10-02 International Business Machines Corporation BiCMOS process
KR100234550B1 (en) * 1990-04-02 1999-12-15 클라크 3세 존 엠 Transistor device with increased breakdown voltage and the manufacturing method thereof
US5013671A (en) * 1990-06-20 1991-05-07 Texas Instruments Incorporated Process for reduced emitter-base capacitance in bipolar transistor
US5124271A (en) * 1990-06-20 1992-06-23 Texas Instruments Incorporated Process for fabricating a BiCMOS integrated circuit
US5001073A (en) * 1990-07-16 1991-03-19 Sprague Electric Company Method for making bipolar/CMOS IC with isolated vertical PNP
US5082796A (en) * 1990-07-24 1992-01-21 National Semiconductor Corporation Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers
DE69133446D1 (en) * 1990-11-14 2005-03-24 Samsung Semiconductor Inc BiCMOS processes with bipolar transistor with low base recombination current
US5221630A (en) * 1990-11-19 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having a two layered structure gate electrode
JP2625602B2 (en) * 1991-01-18 1997-07-02 インターナショナル・ビジネス・マシーンズ・コーポレイション Manufacturing process of the integrated circuit device
JPH04239760A (en) * 1991-01-22 1992-08-27 Sharp Corp Manufacture of semiconductor device
JP2694395B2 (en) * 1991-04-17 1997-12-24 三菱電機株式会社 Semiconductor device and manufacturing method thereof
KR930008018B1 (en) * 1991-06-27 1993-08-25 김광호 Bicmos device and manufacturing method of the same
JP2886420B2 (en) * 1992-10-23 1999-04-26 三菱電機株式会社 A method of manufacturing a semiconductor device
JP2770762B2 (en) * 1995-01-25 1998-07-02 日本電気株式会社 A method of manufacturing a semiconductor device
US5614422A (en) * 1995-03-17 1997-03-25 Harris Corporation Process for doping two levels of a double poly bipolar transistor after formation of second poly layer
DE69615487T2 (en) * 1995-03-28 2002-05-23 Koninkl Philips Electronics Nv A method for manufacturing a semiconductor module with BiCMOS circuit
JP3583228B2 (en) 1996-06-07 2004-11-04 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
FR2756104B1 (en) * 1996-11-19 1999-01-29 Sgs Thomson Microelectronics Manufacture of bipolar integrated circuits / cmos
FR2756100B1 (en) 1996-11-19 1999-02-12 Sgs Thomson Microelectronics bipolar transistor emitter inhomogeneous in a circuit integrated BiCMOS
FR2756101B1 (en) * 1996-11-19 1999-02-12 Sgs Thomson Microelectronics Process for manufacture of an npn transistor in a BiCMOS technology
FR2756103B1 (en) * 1996-11-19 1999-05-14 Sgs Thomson Microelectronics Manufacture of integrated circuits bipolar / CMOS and a capacitor
US6674134B2 (en) * 1998-10-15 2004-01-06 International Business Machines Corporation Structure and method for dual gate oxidation for CMOS technology
US6448124B1 (en) * 1999-11-12 2002-09-10 International Business Machines Corporation Method for epitaxial bipolar BiCMOS

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0083785A2 (en) * 1981-12-30 1983-07-20 International Business Machines Corporation Method of forming self-aligned field effect transistors in integrated circuit structures
EP0110313A2 (en) * 1982-11-24 1984-06-13 Hitachi, Ltd. Semiconductor integrated circuit device and a method for manufacturing the same
EP0054259B1 (en) * 1980-12-12 1986-08-06 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device of the mis type

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58158942A (en) * 1982-03-17 1983-09-21 Hitachi Ltd Semiconductor ic device and manufacture thereof
US4637125A (en) * 1983-09-22 1987-01-20 Kabushiki Kaisha Toshiba Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
JPH0315346B2 (en) * 1983-10-07 1991-02-28 Tokyo Shibaura Electric Co
JPH0441503B2 (en) * 1983-12-26 1992-07-08 Hitachi Ltd

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054259B1 (en) * 1980-12-12 1986-08-06 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device of the mis type
EP0083785A2 (en) * 1981-12-30 1983-07-20 International Business Machines Corporation Method of forming self-aligned field effect transistors in integrated circuit structures
EP0110313A2 (en) * 1982-11-24 1984-06-13 Hitachi, Ltd. Semiconductor integrated circuit device and a method for manufacturing the same

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ELEKTROTECHNIK UND MASCHINENBAU Band 103, Nr. 1, Januar 1985, Seiten 34-37, Wien, Oesterreich; P. SIEBER: "Telefunken electronic auf dem Weg zur Submikron-Technologie" *
IBM TECHNICAL DISCLOSURE BULLETIN Band 24, Nr. 1B, Juni 1981, Seiten 466-470, New York, USA; J.A. DORLER et al.: "Complementary bipolar-FET integrated circuit" *
PATENT ABSTRACTS OF JAPAN Band 7, Nr. 280 (E-216)(1425), 14. Dezember 1983; & JP-A-58 158 942 (HITACHI SEISAKUSHO K.K.) 21.09.1983 *

Also Published As

Publication number Publication date Type
EP0226892B1 (en) 1993-09-08 grant
EP0226892A2 (en) 1987-07-01 application
JPS62155553A (en) 1987-07-10 application
US4752589A (en) 1988-06-21 grant

Similar Documents

Publication Publication Date Title
JPS61294846A (en) Manufacture of semiconductor device
JPS6318661A (en) Manufacture of compound semiconductor and semiconductor circuit
JPS61237476A (en) Manufacture of compound semiconductor
JPS60253291A (en) Electronic part placing substrate and method of producing same
JPS6134990A (en) Substrate for placing electronic part and method of producing same
JPS63212595A (en) Substrate for manufacturing semiconductor module
JPS61144043A (en) Formation of glass layer on semiconductor substrate
JPS61215008A (en) Method of dividing ceramic substrate
JPS62108007A (en) Method of dividing semiconductor board
JPS61229549A (en) Manufacture of ceramic multilayer wiring substrate
JPS6134989A (en) Substrate for placing electronic part and method of producing same
JPS6214490A (en) Substrate for pga
JPS62128973A (en) Method of burning ceramic substrate
JPS62101034A (en) Method for removing protrusions of semiconductor substrate surface
JPS61196558A (en) Monolithic substrate for power element and making thereof
JPS62106697A (en) Processing of metal base substrate
JPS63181396A (en) Method of mounting semiconductor
JPS61273921A (en) Method of molding and coating substrate
JPS629914A (en) Method of separating semiconductor element
JPS62117391A (en) Connection of circuit substrate
JPS62169347A (en) Integrated circuit wafer carrier
JPS62120096A (en) Circuit substrate
JPS612510A (en) Manufacture of ceramic roughened-surface substrate
JPS63148631A (en) Method of forming flat film on wafer substrate
JPS61256728A (en) Silicon etching

Legal Events

Date Code Title Description
AK Designated contracting states:

Kind code of ref document: A2

Designated state(s): AT DE FR GB IT NL

AK Designated contracting states:

Kind code of ref document: A3

Designated state(s): AT DE FR GB IT NL

RHK1 Main classification (correction)

Ipc: H01L 21/82

17P Request for examination filed

Effective date: 19900110

17Q First examination report

Effective date: 19910709

AK Designated contracting states:

Kind code of ref document: B1

Designated state(s): AT DE FR GB IT NL

REF Corresponds to:

Ref document number: 94306

Country of ref document: AT

Date of ref document: 19930915

Kind code of ref document: T

Format of ref document f/p: P

REF Corresponds to:

Ref document number: 3689001

Country of ref document: DE

Date of ref document: 19931014

Format of ref document f/p: P

PGFP Postgrant: annual fees paid to national office

Ref country code: GB

Payment date: 19931122

Year of fee payment: 08

PGFP Postgrant: annual fees paid to national office

Ref country code: AT

Payment date: 19931124

Year of fee payment: 08

ITF It: translation for a ep patent filed

Owner name: STUDIO JAUMANN

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19931115

PGFP Postgrant: annual fees paid to national office

Ref country code: FR

Payment date: 19931223

Year of fee payment: 08

PGFP Postgrant: annual fees paid to national office

Ref country code: NL

Payment date: 19931231

Year of fee payment: 08

ET Fr: translation filed
26N No opposition filed
PG25 Lapsed in a contracting state announced via postgrant inform. from nat. office to epo

Ref country code: AT

Effective date: 19941202

Ref country code: GB

Effective date: 19941202

PG25 Lapsed in a contracting state announced via postgrant inform. from nat. office to epo

Ref country code: NL

Effective date: 19950701

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19941202

PG25 Lapsed in a contracting state announced via postgrant inform. from nat. office to epo

Ref country code: FR

Effective date: 19950831

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 19950701

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PGFP Postgrant: annual fees paid to national office

Ref country code: DE

Payment date: 19970218

Year of fee payment: 11

PG25 Lapsed in a contracting state announced via postgrant inform. from nat. office to epo

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19980901

PG25 Lapsed in a contracting state announced via postgrant inform. from nat. office to epo

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20051202