EP0157768A4 - String comparator device system, circuit and method. - Google Patents
String comparator device system, circuit and method.Info
- Publication number
- EP0157768A4 EP0157768A4 EP19830903352 EP83903352A EP0157768A4 EP 0157768 A4 EP0157768 A4 EP 0157768A4 EP 19830903352 EP19830903352 EP 19830903352 EP 83903352 A EP83903352 A EP 83903352A EP 0157768 A4 EP0157768 A4 EP 0157768A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- output
- indicia
- string
- input
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/903—Querying
- G06F16/90335—Query processing
- G06F16/90344—Query processing by using string matching techniques
Definitions
- An associative memory is a special kind of storage device. Whereas most memories are numerically addressed, associative memories are addressed via their contents. For example, one might ask an associative memory to return all records containing the letters "ZXU" in columns one, two, and three respectively.
- the address applied to an associati memory is the query. If some record exactly satisfies the query, then the query is said to be exact, otherwise it is said to be inexact.
- Conventional associative memories provide no information in response to an inexact query. Inexact queries are merely rejected. If a record exists within the associative memory that is only slightly differen from the supplied query, then in many cases it would be desirable to know of its existence. Such records are minor corruptions of the query. Alternatively, they are ' very similar to the query.
- a storage loop is formed when a storage device repeatedly and sequentially transmits its entire contents to external devices over a high speed data bus.
- An associative memory may be formed by attaching to this bus a device whose funct it is to scrutinize in a passive manner the data stream originating from the storage device as it passes by on the bus. This attached device senses data appearing on the bus that is related in some predetermined fashion to a supplied query.
- the system circuit a computer peripherial devic includes an indicia string comparator device that compares strings of indicia or characters at high speeds. This sys circuit performs an approximate string comparison operatio
- the system circuit computes a measure of string similarity.
- the system circuit is accessed by a computer in the same manner as a Random Access Memory.
- Query strings and recor strings are written into the system's memory, the approxim similarity measures are automatically computed and the bes matches are recorded in a memory inside the systems circui These best matches may then be accessed by the host comput
- the system circuit would be used to search a large lexicon or database of record strings for th entries which are most similar to a query string.
- the quer string is entered into the system circuits and then each lexicon or database record string is entered. At the end, the pointers to the record strings most similar to the quer string are automatically available in a list in memory in the system circuit.
- the measure of string similarity is an extremely general function which can be tailored or adapted under software control for a specific application by the setting of parameters.
- the computation time is proportional to the average length of a string of indicia.
- the string comparison device is a means described in Appendix 1 which is made a part of this application.
- First the string comparator means is described in "the simplest string comparison function" in pages 1 through 6 o Appendix 1, second it is described in “string comparison function with variable character weights” in pages 7 throug 10 of Appendix 1, third, it is described in “string comparis function with unmatched character compensation and variable character weight", in pages 11 through 14 of Appendix 1, fourth it is described in “string comparison function with directional biasing and variable character weights” in page 15 through 18 of Appendix 1, and fifth it is described in “the full string comparison function with variable characte weights, unmatched character compensation and directional biasing" in pages 19 through 22 of Appendix 1.
- the system circuit is an electronic device which includes a string comparator means.
- the elect circuit performs the calculation of the string similarity function 0
- the string comparator which is an electronic circuit, and an I/O controller and ranker means together comprise an electronic device which is referred to as the String Comparator means.
- the system circuit is connected t a computer system by means of an interface circuit to utiliz the string comparator means.
- the string comparator means includes Bus Control means. Master Control means, Ranker me Divider means, and a String Similarity Computer.
- the Strin Comparator means is used like a random access memory.
- Bus Control means uses well-known techniques to control int bus lines and the external signals. Master Control impleme DMA operation and DMA editing in the manner described in de herein below.
- the Ranker means maintains a ranked list of best comparison results.
- the Divider means computes the ratio of two binary numbers from the String Similarity Comp
- the String Similarity Computer computes the full string similarity function ⁇ defined in appendix 1.
- the Master Control means, the Bus Control means , the Ranker means, the Divider means and the String Similarity Computer may be logic circuits and may be embodied with well-known electron c ⁇ roonents.
- the String Similarity Computer is comprised of th String Control means.
- Parameter Generation means Core sect C section, CB section, R section, M section, TOTR section TOTM section.
- the purpose of the String Control means is to con and coordinate the activities of the rest of the string simi computer.
- the String Control means is connected as shown in the drawings and has internal storage registers and memory.
- the Parameter Generation means is used to obtain t indicia or character weight and compensation values.
- the in or character itself is received from the string control mean or circuit.
- the character weight and compensation value are
- the Parameter Generation means is connected as shown in drawings
- the Core section is the decision-making part of the String Similarity Computer.
- the Core section identifies common portion of the query string and the record string, and is connected as shown in drawings.
- the CA section is used to compute the total compensation value for the indicia or characters in the string A.
- the CA section is connected as shown in the drawings.
- the CB section is used to compute the total compensation value for the indicia or characters in the string B.
- the CB section is shown in the drawings.
- the R section computes an intermediate subtotal value. The values computed by the R section correspond precisely to the R function described in the description of string similarity function.
- the R function is connected as shown in the drawi
- the M section computes the numerator of the ratio defining t string -similarity function.
- the M function is connected as shown in the drawings.
- the TOTR section computes an interme subtotal value.
- the values computed by the TOTR section correspond precisely to the values of the variable TOTR used in the C programs.
- the TOTR section is connected as shown i the drawings.
- the TOTM computes the denominator of the ratio defining the string similarity function.
- the TOTM section is connected as shown in the drawings.
- the original disclosure of the invention related t new and improved word comparator device, referred to hereina as a word associator circuit, that provides a numeric measur of the degree of a word similarity between the compared word as defined by mathematical formula.
- the original disclosure also related to an associative retrieval system and method for retrieval of inexact queries in a quick and expeditious manner.
- the circuit may be an electrical digital circuit or other
- Appendix 1 also describes four improvements to th original string comparison function. These improvements pr an extremely flexible string comparison function which can adapted for a given application by the setting of parameter Any of these improvements to the word associator circuit ma be used in an associative memory in the same manner as the original word associator circuit.
- the word similarity of two indicia strings may be expressed in three different forms: absolute, ratio, and fractional.
- Absolute word similarity provides a single non negative number M which is a measure of the total weight of common portions of the indicia strings.
- the common portion are symbols or indicia occuring in both of the indicia stri the total weight of which depends on the individual indicia weights and the relative positions of the common portions.
- Absolute word similarity is most useful when the lengths or total weights of the indicia strings are always equal or ne equal.
- Ratio word similarity provides the absolute word similarity value M and the total word weight TOTM. The tot
- Absolute word similarity and ratio word similari are most useful in applications which search for a word similarity value exceeding a certain threshold.
- a possibl application would involve monitoring a heartbeat by contin encoding recorded heartbeats as a string of indicia. This indicia string would then be compared to one or more indic strings which denote abnormal heartbeats. If the similari of the two indicia strings were above a certain threshold, an alarm could be sounded.
- Fractional word similarity is useful in applicat such as the associative memory circuit, where a large numb of indicia strings are compared with a word associator cir and a ranked list of the most similar indicia strings is maintained. The fractional representation of word similari provides a convenient way to compare word similarity values
- O PI IPO extract the records most similar to the supplied query.
- configurations may achieve a wide range of cost/response-time possibilities.
- the associativ retrieval system with associator circuits could off load fro a host processor, the task of searching for database records In doing this, it could provide improved services as well as entirely new services.
- Figure 2 is the improved block diagram of' the sys circuit including the string comparator means.
- Figure 3 is an illustration of the improved timin
- Figure 4 is a block diagram of the String Control in Figure 2.
- Figure 5 is an illustration of components of the String Control of Figure 4.
- Figure 6 is a block diagram of the Parameter Generation shown in Figure 2.
- Figure 7 is a block diagram .of the Core Section shown in Figure 2.
- Figure 8 is a block diagram of the CA section shown in Figure 2.
- Figure 9 is a block diagram of the CB section shown in Figure 2.
- Figure 11 is a block diagram of the M section shown in Figure 2.
- SUBSTITUTE SHEET OMPI Figure 12 is a block diagram of the TOTR section shown in Figure 2.
- Figure 13 is a block diagram of the TOTM section shown in Figure 2.
- Figure 14 is a block diagram of an associative retrieval system.
- Figure 15 is a block diagram of the associator circuit illustrated in Figure 14.
- Figure 16 is an illustration of the timing of ⁇ a ⁇ .
- Figure 18 is a block diagram of the basic word associator circuit in another system.
- Figure 19 is a schematic diagram of the selector circuit shown in Figure 17.
- Figure 20 is a schematic diagram of the tally mem circuit shown in Figure 17.
- Figure 21 is a schematic diagram of the add circu shown in Figure 17.
- Figure 22 is a schematic diagram of the latch cir shown in Figure 17.
- Figure 23 is a schematic diagram of the test circ shown in Figure 17.
- Figure 24 is a schematic diagram of the add-latch circuit or R section shown in Figure 17.
- Figure 25 is a schematic diagram of another add- latch circuit or M section shown in Figure 17.
- Figure 26 is an illustration of the operation of the word comparator.
- This invention is to a new and improved string comparator device which provides a numeric measurement of th
- the preferred embodiment of the system circuit is an electronic device which is a string comparator means including a comparator device.
- Figure 1 shows a system in which this electronic device would be used.
- the string comparator 105 performs the calculation of the string similarity function ⁇ .
- the string similarity computer 105 and an I/O controller and ranker means 104 together comprise the system circuit 103 referred to as the String Comparator means.
- the system circuit 103 is connected to a computer sy 101 by means of an interface circuit 102.
- the computer syst 101 is shown with a keyboard 101' and a display 101" for hum interaction.
- a variety of well-known devices for storage, communications and computation may also be attached to the computer system 101.
- FIG. 1A Another use of the string comparator circuit 105 ' is shown in Figure 1A.
- an interface means 106 monitors a stream of data 107, formats words denoting the contents of the data stream, and uses a string comparator circuit 105' to compare against one or more predefined strings. When a predetermined similarity threshhold value is exceeded, an output signal 108 denotes a match condition.
- String Comparator means The logic design of the String Comparator means is explained below. Appendix 2 made a part of this specificati gives a complete, detailed logic specification for the prefe embodiment of the String Comparator means as a Large Scale Integrated (LSI) electronic circuit. String Comparator mean
- OMPI refers to the preferred embodiment as well as alternate cir for performing particular functions.
- the preferred embodiment of the String Comparator means 103 of Figure 1 is shown in Figure 2. It consists of Bus Control means 21, Master Control means 20, Ranker means Divider means 23, and a String Similarity Computer 10.
- the string comparator means is used like a random access memory as described in Appendix 3.
- the Bus Control 21 uses well-known techniques to control internal bus lines 24, 24* and 24" and the external signals 26.
- Bus Control 21 controls all external accesses to system circuit, and monitors the activities of the other in components of the system circuit.
- Master Control 20 implements DMA (Direct Memory A operation and DMA editing in the manner documented in Appen 3. Master Control controls automatic loading of data from an external memory.
- DMA Direct Memory A operation and DMA editing in the manner documented in Appen 3.
- Master Control controls automatic loading of data from an external memory.
- the Ranker means 22 maintains a ranked list of the best comparison results.
- the ranked lists contain up to 16 entries; each entry consists of the string similarity value and a record pointer. Appendix 3 describes the effect of the Ranker means.
- the Divider means 23 computes the ratio of two binary numbers from M 17 shown in Figure 11 and TOTM 19 shown in Figure 13; this ratio is expressed as a fractional binary number.
- the String Similarity Computer 10 computes the full string similarity function ⁇ defined in detail in Appendix 1.
- the Master Control means 20 the Bus Control means
- Figure 1A may include any one of the following circuit configurations.
- the design of the PF474 is based upon a structure design methodology which uses two-clock logic.
- Figure 3 shows the two clocks ⁇ l and ⁇ 2.
- the clocks are designed so that only one is high (active) at a time.
- ⁇ l hi inputs are accepted into a logic block; when ⁇ l falls, the inputs are latched into the input registers.
- ⁇ 2 is high the output of a logic block may change; when ⁇ 2 falls, the output signals are latched.
- the string similarity computer 10 is also describ in further detail in Appendices 2.
- the string similarity computer 10 is now described on a functional level.
- the purpose of the String Control means 11 is to and coordinate the activities of the rest of the string similarity computer 10.
- the String Control means 11 is sho
- Figure 4 shows the input and ou signals which are important for the logical functionality.
- Figure 5 shows the internal storage registers and memory.
- the GO input 30 is a 1-bit signal.
- String Control will initiate a string comparison operation.
- the RBUSY signal 36 and the CTS signal 37 are status indicators.
- a string comparison operation can be started only when the RBUSY signal 36 is low (inactive) or CTS signal 37 is high (active) .
- the SBUSY output signal 35 is high (active) whil string comparison operation is in progress. This signal i used by Master Control 20.
- the String Control means contains Random Access Memory 80 which contains areas for strings of 8-bit characters. The two strings are designat
- String-1 and String-2 are loaded into the Ra Access Memory 80 by the Bus Control means 21.
- String-1 an String-2 are terminated with the character NULL.
- Addition two 8-bit registers LENl 81 and LEN2 82 contains the lengt of String-1 and String-2, respectively.
- the DISP register 83 and the POS register 84 are internal 8-bit registers used to perform the Forward and Reverse scans.
- the lengths LENl and LEN2 are compared.
- the shorter of the two strings is designated String-A, the other is designated StringB. If the lengths are equal, the designation is made arbitrarily.
- the CMD output signal 31 is a 3-bit signal which is used to sequence the activities of other parts of the string similarity computer 10.
- Table 1 shows the valid values for the CMD signal 31. The entries in Table 1 are listed in the order in which the values are output.
- Control implements the following Forward Scan Program: char strA[128], strB[128]; /*Two Strings*/ int lenA, lenB; /*Strings' lengths.
- the Reverse Scan phase of the String Control mean operation causes the computation of the function M, as desc in the previous section defining the string similarity func 0 ⁇ .
- the Reverse Scan is divided into two stages to facilita the computation of the compensation functions. In effect.
- String Control left-justifies the String-1 and String-2 and transmits every character beginning with the rightmost and ending with the leftmost. More precisely, String Control 5 implements the following Reverse Scan Program:
- POS and DISP correspond exactly in function and purpose to the 8-bit regi POS 42 and DISP 41 shown in Figure 5.
- POS and DISP are initialized in the program RSCAN to the values which the held at the end of the program FSCAN.
- RSCAN can c ⁇ nven be run directly after FSCAN with no extra initialization.
- the purpose of the Paramater Generation means 12 is to obtain the character weight and compensation values.
- the character itself is received from the String Control circuit 11.
- the character weight and compensation values ar used by the rest of the string similarity computer 10.
- the Parameter Generation means 12 is shown in Figure 6.
- Figure 6 shows the input signals 31-34, the output signals 39-43 an the internal Random Access Memory 38.
- the input signals are the CHAR input 32, the SCID input 34; the STRID input 33, and the CMD input 31. All of these signals are outputs of the String Control means 11.
- the Random Access Memory 38 contains, for each of 255 characters, a compensation value between 0 and 7, a weig value between 0 and 7, and a bias value between -2 and +1. These values correspond to the compensation function C, the forward weight function W f , and the bias function B which we described in the appendix defining the string similarity function ⁇ .
- the Random Access Memory 38 is loaded via the Bus Control means 21.
- the CHAR output signal 39 is always the same as th previous CHAR input signal 32.
- the CHAR signals 32, 39 are 8-bit data items.
- the STRID output signal 40 is always the same as t previous STRID input- signal 33.
- the STRID signals 33, 40 ar 1-bit signals.
- the CMD output signal 43 is always the same as the previous CMD input signal 31.
- the CMD signals 31, 43 are 3- signals.
- the Core Section 13 is the decision-making part of t string similarity computer 10. It receives data from the
- Parameter Generation means 12 maintains character counts and determines what the rest of the string similarity computer must do.
- the Core Section 13 is pictured in Figure 7 with its input signals 39-43, internal TALLY memory 44, and output signals 45-52. '
- the input signals are CHAR 39, STRID 40, WGHT 42, C and CMD 43. These input signals are all outputs of the Parame Generation means 12.
- the TALLY memory 44 is a fast clear memory means of size 256X4.
- the TALLY memory contains a 4-bit signed (two's complement) number in the range -7 to 7, inclusive, for each character specified by the CHAR input signal 39.
- the clear control of the TALLY memory zeros the entire memory. Furtherm individual entries in the TALLY memory may be incremented or decremented. Attempting to increment the value 7 or to decrement the value -7 results in an unchanged state. This is referred to as latching at +7.
- the TALLY memor 44 correspond directly to the array T used in the C programs in the earlier sections defining the string similarity function ⁇ .
- the WX output signal 46 is equal to the arithmetic (two's complement) inverse of the WGHT input signal 41.
- WX 46 is a 4-bit non-positive integer.
- the WGHT output signal 49 is equal to the previous WGHT input signal 41.
- the WGHT signals 41, 49 are 3-bit unsigned integers.
- the CMD output signal 50 is a 3-bit signal that is always equal to the previous CMD input signal 43.
- the CMDX output signal 48 is a 1-bit signal equal to the low-order bit of the CMD input signal 43.
- the CMDB output signal 47 is a 2-bit signal.
- SUBSTITUTESHEET low-order bit of CMDB 47 is high (active) only if the CMD in 43 is equal to '001' denoting a Process Character command.
- the high-order bit of CMDB 47 is high only if the CMD input is equal to '010' or Oil", denoting a Clear command.
- the CMD input 43 is equal to '010* or Oil',
- a Process Character command is specified.
- the CHAR input 39 specifies a character to be processed.
- Each character designates a 4-bit entry in the TALLY memory 44".
- Character processing consists of incrementing or decrementing the entry in the TA memory 44 which corresponds to the character denoted by the CHAR input 39.
- the CMD input 43 is equal to '001' and the ST input 40 is high (.active).
- the appropriate TALLY memory entr is incremented and latched at 7. If the result is not posit then the T output signal 52 is high (active) otherwise the T 52 is low (inactive) .
- the appropriate TALLY memory entry is decremented and latched at -7. If the result is no negative then the T output signal 52 is high (active) otherw the T output 52 is low (inactive) . If the T output signal 52 as computed above is hig
- the CA section 14 is used to compute the total compensation value for the characters in the STRING-A.' The CA section 14 is shown in Figure 7 with its inputs 45, 49-52
- the signal COMPA 53 is an output signal which is also fed-back as an input to CA.
- the input signals are STRID 45, WGHT 49, CMD 50, C and T 52. These signals are outputs of the CORE section 13.
- the output signals STRID 54, WGHT 55, CMD 56, C 57 and T 58 always the same value as the corresponding inputs; i.e. thes signals are passed through unchanged.
- the COMPA output signal 53 is a 9-bit unsigned non negative integer.
- the COMPA outpu value 53 is zero.
- the CMD input signal 50 is equal tc '001', denoting a Process Character command, and the value of the STRID input signal 45 is equal to the value of the T input signal 52; then the 4-bit signed input C 51 is added t the previous value of COMPA 53; the resulting sum is output as the COMPA signal 53. If an overflow occurs on this ' addition, the carry bit is lost; an overflow will not occur if the programming restraints documented in Appendix 3 are obyeed. When neither of the above condition is met., the COM output signal 51 is the same as the previous COMPA input sig
- the CB section 15 is used to compute the total compensation value for the characters in the STRING-B.
- the CB section 15 is shown in Figure B with its inputs 53-58 and outputs 59-63.
- the signal COMPB 59 is an output signal whic also fed-back as an input to CB.
- the input signals are COMPA 53, STRID 54, WGHT 55, CMD 56, C 57, and T 58. These signals are outputs of the CA section 14.
- the output signals STRID 60, WGHT 61, CMD 62, a T 63 are always the same value as the corresponding inputs; i.e. these signals are passed through unchanged.
- the COMPB output signal 59 is a 9-bit unsigned non
- the R section 16 computes an intermediate subtotal value.
- the R section 16 is pictured in Figure 10 with its inputs ' 59-63 and its outputs 64-66.
- the RSUM signal fedback is an input to the R section 16.
- the values of the output signals STRID 65 and CMD 6 are always the same as the values ot the inputs STRID 60 and CMD 62.
- £i IBQT ⁇ TC iTE SHEIT- is equal to '001', denoting a Process Character command, and the T input signal 63 is high (active) ; then twice the value of the WGHT input signal 61 is added to the value of the prev RSUM input 64; the result is the next RSUM output 64.
- the RSUM output signal 6 is equal to the previous RSUM input signal 64.
- the M section 17 is shown in Figure 7.
- the inputs to the M section 17 are the signals RSUM 64 (a 10-bit unsigne integer) , STRID 65 and CMD 66.
- the outputs are the READY output signals 68 and the MVAL output signal 67.
- MVAL 67 is a 16-bit nonnegative integer which is fedback as an" input to the M section 17.
- the output READY 68 is high (active) only when the CMD input 66 is equal to ' 110 ' , denoting a Transmit Result command. While the READY signal 68 is active, the output of M section 17 and the TOTM section 19 are valid and ready for the DIVIDER section 23 to use them.
- the MVAL output 67 is zero. Whe either of the following two conditions hold (1) the CMD input 66 is equal to '100', denoting a Load CA into R command, or ( the STRID input 65 is high (active) and the CMD input 66 is e to '001', denoting a Process Character command; then, the MVA input 67 is added to the RSUM input 64 and the result of the addition is the next MVAL output 67.
- the TOTR section 18 computes an intermediate subt value.
- the values computed by the TOTR section correspond precisely to the values of the variable TOTR used in the C programs in the appendix 1 defining the ⁇ string similarity function.
- the TOTR section 18 is shown in Figure 12 with its input signals 45-48 and its output signals 71-74.
- the TOTRS output 71 is an 11-bit signed (two's complement) integer whi is fedback as an input to the TOTR section 18.
- the WX input 46 is a 4-bit signed (two's complemen integer. Both WX 46 and TOTRSUM 71 have only non-positive v
- the CMDX output 74 and the STRID output 72 are alw equal to the previous CMDX input 48 and STRID input 45, respectively.
- the high-order bit of the CMDB input 47 is hi
- the TOTM section 19 computes the denominator of th ratio defining the ⁇ , string similarity function.
- the TOTM section 19 is shown in Figure 19 with its inputs 71-74 and its output TOTMVAL 75.
- the TOTMVAL signal 7 is a 16-bit non-positive integer which is fedback to the M s 19 as an input.
- a non-positive integer is either zero or is negative number in two's complement format with an implicit negative sign bit.
- the reason TOTMVAL 75 is a non-positive integer is to simplify the circuit design of the DIVIDER sec 23.
- the TOTRSUM input 71 is an 11-bit signed (two's complem number.
- the TOTMVAL outpu 75 is zero.
- the low-order bit of the CMDB input 73 is (active) , denoting a Process Character command, and the STRI input 72 is high (active) ; then the TOTRSUM input 71 is adde to the TOTMVAL input 75 and the result is the next TOTMVAL output 75.
- the TOTMVAL output 75 is unchanged from the previous TOTMVAL input 75.
- FIG. 1 shows a block diagram of the PF474.
- the Master Control means 20 and the Bus Control means 21 are implemented with nodes 2700-3299.
- Ranker means 22 is implemented with nodes 3300-3900.
- the Divider means 23 is node numbers 1-299.
- the String Similari Computer 10 is implemented with nodes 700-2000.
- the String Similarity Computer 10 consists of several different logic blocks.
- the String Control is implemented as nodes 300-600.
- the chip manual entitled Advanced Product Descripti is included as Appendix 3 and made a part hereof to provide disclosure of use of the chip.
- Appendix 4 is included herein and made a part hereof as an example of an electrical interface of the chip with the S-100 Bus, a widely used system for computer interconnection.
- the circuit described in Appendix 4 supports appropriate communication between the chip, a 4K-word by 8-bit RAM, and any of the widely used computer system which are compatible with the S-100.
- Appendix 4 included drawings A4-1 through A4-8.
- the improved string comparator is based on the associative memory circuit originally disclosed and filed on March 14, 1979 as Serial Number 20,618 includes a word associator circuit shown in detail as an electrical digital circuit in Figures 14 through 26.
- the system or associative memory circuit is shown in Figure 14.
- This associative memory circuit is an improved associative retrieval device that includes the use of the word associator or comparator circuit connected in a storage loop to locate and extract records that are most similar to the supplied query. Inexact queries will rapidly locate records similar with respect to word, numeric and mask related measurements of similarity.
- the new and improved method that is set forth below in detail provides a method of word comparison and a method of processing in the improved associative memory circuit or associative retrieval device.
- the processing is preferably in a parallel configuration that provides rapid response to queries, while processing a large number of simultaneous requests.
- shared memory 312 such as a time multiplexed multi-po random access read-write memory of any well known design such as TI-s 74200.
- shared memory 312 such as a time multiplexed multi-po random access read-write memory of any well known design such as TI-s 74200.
- 312 is allotted a brief time slice on the order of one millise A port may disconnect prior to this time elapsing.
- the associative memory circuit 10 communicates with the outside world through its communications modules 314 and 314' of any well known design.
- the communications modules or circuits may communicate with the other associative memory circuits 10 using shared memory through buses 316 and 316' in any well known manner and by use of any well known design. These communication modules mig also perform considerable preprocessing before passing a query onto the other system components.
- the main storage units (MSU) 320 and 320' of any well known design are devices that contain the actual records to be searched in memory units of any well known design.
- the main storage units contain any o a variety of well known control circuits to transmit these records in a fixed format over a bus.
- a plurality of main storage units may be used as illustrated by number 322 and the dots.
- the transmission format requires the simultaneous transmission of recor characters taken sequentially from the record moving from right to left and from left to right, see Figure 25 and the in-use description set forth hereinbelow. Numeric portions of a record are transmitted separately.
- the bus or lines 324 and 324' also contain control and timing signals, error correction codes and a data path of well known design for use in the communications between associator circuits 342, 344, 342' and 344' and extractor circuits 356 and 356'.
- MSU main storage units
- a short blanking period is required to permit the associator circuits to initialize themselves for another record.
- the MSU 320 and 320' Prior to the transmission of each records data, the MSU 320 and 320' must transmit an internal record number for the record that follows.
- SUBSTITUTE SHEET numbers should be assigned sequentially by the MSU 320 and 320'.
- the control circuit 330 is connected to the MSU devices 320 and 320 r by bus 326.
- the control circuit 330 is responsible for all update and control of the MSU's.
- the control circuit may consist of one or more simple micro ⁇ computers of well known design.
- Control circuit 330 communicate through shared memory 312 over bus 340.
- a direct interface 332 of well known design might be attached by bus 334. This would permit a direct data path from an MSU 320 and 320' to an external high speed device. This would facilitate the rapid loading of an entire MSU 320 and 320' as might occur at bootstrap time.
- the associator circuits (ac) 342, 344, 342' and 344' are an important part of this invention.
- the associator circuit 342, 344, 342' and 344' are connected in strings terminated at one end by a single or multiple extractor circuits 356 and respectively by continuations of bus 338 or 338' respectively and at the other end by the network switching module 336.
- Data from a selected MSU passes through network switching 336 5 and then through an associator circuit 342, 344, 342 and 344'. This circuit scrutinizes the data as it passes, locking for records that are very similar to the query provided.
- the associator circuits 342, 344, 342', and 344' flag the most similar records and they are 15 then extracted from the data stream by the extractor circuits 356 and 356' and eventually passes back through shared memory 312 over bus 360 to the communications circuits 314 and 314'.
- the diagnostic computer 364 also of any well known design, is connected in a well known manner to the associative 20 memory 310 to provide system performance statistics and maintenance information in a well known manner.
- FIG. 343 is a more detailed block diagram of associator circuits 342 and 342' of Figure 14.
- Each 25 pair of associator circuits in Figure 14 is similar to the
- the numerator is computed by any well known means and is equal to twice the sum of the M quantities output from the two copies of the circuit.
- the denominator is computed by any well known means and is equal to the sum of the TOTM quantities output from each copy of the circuit.
- the word associator circuit 384 may or may not actually perform a division to arrive at the degree of word similarity. Instead, the ranker 396 and the other associator circuits 380 and 388 might work entirely with fractional representations of similarity.
- the word associator circuit 384 is mainly made up of circuits 400 and 400' and interconnecting circuitry of well known design.
- N is an integer design parameter in any well known manner. Loading of the many parameters involved in the association process is controlled by an onboard microprocessor or controller 398 of well known design. The microprocessor is connected to the basic module in a well known manner. When all records have been observed, the ranker waits for the highest ranking records to appear again in the storage loop. As they appear, the ranker 396 marks them for extraction in' any well known manner.
- bidirectional serial we mean that successive positions from each of the two words under comparison and from their flips are simultaneously transmitted.
- two observers of the data stream performing the procedure or method as illustrated in Figure 26.
- signi ⁇ ficance is the fact that each observer needs knowledge only of the data instantaneously before him in the data stream.
- FIG. 17 the one word associ circuit in block diagram form is illustrated as-numeral 4 Two of these circuits 400 are included in the word associ circuit 384 in Figure 15.
- the data selection 1 illustra in Figure 17 is shown in detail in Figure 19 and may uti two quadruple bus gates such as Texas Instruments, Incor circuit 74125 and 74126, Exhibit A in the original appli and made a part of this application. It has two input b 404 and 406 entering from above. One of these two in on time frame is routed to a single output 408 exiting belo
- Figure 19 discloses the schematic for a single bus line.
- Clock input potential ⁇ 110 is connected to the selector 402. Two clocks are utilized in circuit 400, Figure
- ⁇ The purpose of ⁇ is to define whether a query or a bus character is currently being processed. A complete cycle of 0 * corresponding to a read/write cycle in 114 occurs during each half cycle of ⁇ as shown in Figure 16. Another purpose of ⁇ is to provide a trigger to latch 182 of Figure 17. The event consisting of a high to low transition of ⁇ a may serve as a trigger to latch 182. The clock ⁇ is used as a control input in blocks 144, 126 and 402 of Figure 17.
- the main portion of the Figure 17 circuit is design ated by numeral 112 and includes a random access read/write memory 114 referred to as tally or a tally memory.
- the memory address enters from above through bus 408.
- the read/write mode of operation is selected by the read/write potential 0" entering from the right through line 116 from a clock means of well known design not shown. When read/write potential is low, the read mode is selected. When read/write potential is high, the write mode is selected. Data exists from the lower left on bus 120 and enters from the upper right.
- tally is organized as 256 8 bit words.
- addresses and data are 8-bit quantiti Figure 20 shows the schematic for each bit of a tally word.
- tally may include one or more Texas Instrument Incorporated
- the add block Figure 17 is an incrementer/decremen 126. Data enters from the right. Depending on the state of input potential, the input potential value of the entering data is either incremented or decremented before exiting the two four bit binary full adders circuit 130 on bus 132, as shown in Figure 21.
- the adders 130 may include a Texas Instrument Incorporated 4-bit binary full adder No. 7483, Exhibit C in the original application and made a part hereof Hex inverters 134 No. 7404, Exhibit AA in the original appli is connected between the input potential over bus 128.
- the incrementer/decrementer 126 in Figure 17 is actually an adde in which one of the summands is restricted to either plus or one. If input potential of 128 is zero, then plus one is ad
- a positive edge triggered data latch 136 in Figur 17 is connected to bus 132 by bus 138. Data enters through bus extension 138 from the left and exits from the right on bus 140 to tally 114. On the positive going edge of read/ write potential actuated by input 2, the contents entering latch 136 are latched and become the output from the latch over bus 140.
- the latch is a two-bit D-type register 5 with 3-state output 142 shown in Figure 22, Texas Instrument Incorporated Number 74173 attached to the original application as Exhibit D and made a part hereof.
- a convertible sign tester 144 in Figure 17 has an input through bus 132 for data entering from the right and the tester 144 determines if this data is non-positive or non-negative, depending on the state of the input potential on bus 146 entering from below. The test is performed relative to two's complement arithemetic. If the input potential is low, then test will output high on output bus 148 to the left, provided that its input is greater than or equal to zero.
- tester 144 is shown in Figure 23 as an 8-bit device.
- the input 132 is connected to two dual 5-input positive no gate 150 and 152 Texas Instrument No.
- Texas Instrument No 7408 attached in the original applicat as Exhibit E and made a part hereof connected to one gate of quadruple 2-input positive and gate 154, Texas Instrument No 7408 attached in the original application as Exhibit EE and a part hereof.
- Gate 154 is connected to one gate of a quadr 2-input positive or gates 156 Texas Instrument Incorporated 7432 attached in the original application as Exhibit EEE and a part hereof.
- Gate 156 Texas Instrument No. 7432 is also connected to and gate 158.
- gate 158 Texas Instrument No. 7408 is connected to one of the input lines 132 and line
- a clearable edge triggered latch 170 is shown in Figure 17 and shown in detail in Figure 24 with an adder attached as described below.
- Input 172 inserts a one (1) in latch 170.
- the output is transmitted on bus 174 to add latc 182.
- the adder 170 has two inputs on busses 148 and 172 and a single output on bus 174 which is the sum of the inputs.
- output 178 of the adders 176 such as a 4-bit binary full a of Texas Instrument, Incorporation No. 7483 attached as Exhi c on the original application become the input to the latche 180, such a 4-bit D-type registers with 3-state outputs, Exhibit D.
- One of the inputs to the adder is.the output of the latch.
- latch 170 is an latch coupled to an adder with an 8-bit output and two 7-bit inputs as shown in Figure 24.
- the clearing connections are shown in Figure 24, but may be accomplished by any well know manner.
- Add-latch 182 shown in Figures 17 and 25, is like item 170. Its input enters from bus 174 from above. Add- latch 182 is triggered on the negative going edge of the re write potential ⁇ . In the preferred embodiment, add-latch 182 includes 4-bit binary full adders 184 such as Texas Instruments Corporation No. 7483, is a 13-bit latch
- the memo 190 contains the words ABC and ABB which are to be compared They are transmitted via two transmitters 192 and 194 over data stream four characters wide, as illustrated.
- the top half of the stream contains the transmission of the unalter words and the bottom half contains the transmission of the flips of the words.
- On each side of the stream sits an observer 196 and 200. Each observer is watching a single column at a time as columns flow from left to right.
- the ' memory 190 and transmitters 192 and 194 correspond to the MSU 320 of Figure 14 and the data stream roughly for illust purposes corresponds to the data bus 338 of Figure 15 (alth query characters do not occur on the data bus or in the MSU)
- the two observers correspond for illustration purposes to t two copies of the circuit 100 shown in Figure 17 contained within the word associator 384 of Figure 15.
- each observer must "remember" a numeric qua assocaited with each alphabet member. In this example ther are but three; A, B, and C. This collection of quantities corresponds for illustration purposes to tally 114 of Figur
- Each observer must also "remember” a numeric quantity R tha is 170 and another M that is 182. These correspond for illustration purposes directly with Figure 17.
- each observer notices two characters before him. processes one at a time in some fixed order, say top to bot
- OBSERVER ONE shown as 196 in Figure 26 corresponds to one copy of the circuit 400 of Figure 17.
- the circuit of Figure 17 is -controlled by two cloc cycles shown in Figure 16.
- the bottom signal (THETA) is the major timing signal.
- THETA is the major timing signal.
- PHI is called the minor clock.
- th circuit first processes the character "A” from the query and from the bus word. Then it processes the character “B” from query word and “B” from the bus word. Then it processes the character “C” from the query word and "B” from the bus word.
- this quantity may be "normalized" by a proce involving a- division as discussed elsewhere if one desires similarity measure that ranges from zero to one.
- the character "A” is present at the selection inpu
- the character "A” is present at the selector input
- the R register shown as 170 in Figure 4 contains z
- the M register shown as 182 in Figure 4 contains z
- Tally location "B” 0
- Tally location "C” 0
- the character "A" is present at the selector input
- the R register shown as 170 in Figure 17 contains at the start of this period and 1 at the completion.
- the M register shown as 182 in Figure 17 contains at the start of this period and 1 at the completion.
- the character "B" is present at the selector input 404.
- the R register shown as 170 in Figure 17 contains 1 throughout.
- the M register shown as 182 in Figure 17 contains
- Tally location "A” 0
- Tally location "B” 0
- Tally location "C” 0
- the R register shwon ' as 170 in Figure 17 contains the start of this period and 2 at the completion.
- the M register shown as 182 in Figure 17 contains the start of this period and 3 at the completion.
- Tally location "C” 0
- M is updated and becomes 3.
- Minor clock cycle 1 During the start of this period while PHI is low, character "C" is routed from 404 to become the address of th memory 114 and since PHI is low the memory responds by readi out this location and presenting it to the ADD block 126. S THETA is low this block adds one to the value producing 1. is then routed both into LATCH 136 and TEST 144. Since THET
- OMPI_ is low TEST outputs a 0.
- the LATCH contents are frozen as TALLY switches into write m This in effect writes the updated quantity just computed by ADD back into location "C". Also at this transition the R register is incremented if signal 148 is 1. In this case it is not. During the second half of this period while PHI is high, TALLY is writing its updated information.
- the character "C” is present at the selector input
- the character "B” is present at the selector input
- the R register shown as 170 in Figure 17 contains
- the M register shown as 182 in Figure 17 contains start of this period and 5 at the completion.
- Tally location "A” 0
- Tally location "B” -1
- Tally location "C” 1
- circuit invention evol from the formula to the algorithm to the circuit.
- follo criteria are met: 1.
- the next evolutionary step is the invention of an algorithm which quickly computes the formula.
- This algorith is presented herein in the form of a Fortran function sub ⁇ program. It is called with three input parameters: IQ, IR and N. IQ and IR each of which is a dimension N integer vector. Upon return, the variable Theta is the degree of similarity between the input words IQ and IR. Alphabet members are integers between 1 and 256 inclusive.
- our circuit requires on two internal clock cycles. Each represents approximately a read/write cycle pertaining to a high speed random access memory. Actually, the clock must be slightly slower than
- ITALLY (IR(I) ) ITALLY(IR(I) ) -1
- the SEL is a random access read/write memory 208. Its address enters on bus 224 from above and data output is to the right on bus 214. In Figure 18, it is assumed that the read mode is selected as the device is only written to during master initialization. In th preferred embodiment the read/write memory 208 is organized as 127 2-bit words.
- SYN consists of three random access read/write memories, 202, 204, and 206. In each, the address enters on bus 406' from above the data output transmitted on bus 220, 220', and 220 ' ' from below.
- the read mode is selected as the device is only written to during master initialization. In the preferred embodiment, it is organized as three memories, each consisting of 256 8-bit words.
- Select is a data selector 210. It has three input busses 220, 220', and 220'' entering from above. One of these three is routed to a single output 224 existing below, depending upon the nume value of the 2-bit value entering from the left. If this valu 0, then Select ignores its input and outputs zero. If this va is 1, 2 or 3, then the first, second or third input data bus
- SHEET respectively is routed to the output.
- it has 8-bit inputs and outputs.
- MV is a one bit latch 222. It is set/reset during master initialization. The current state of MV exists above.
- Select 402 is a data selector. It has two input busses 224 and 404' entering from above. One of these is routed to a single output exiting below, depending upon the • state of ⁇ entering from the right. If ⁇ is low, then the right input bus is selected. Otherwise, the left bus is selected. In the preferred embodiment. Select has 8-bit inpu and outputs.
- PW is a random access read/write memory. Its addre enters from the left and data output is to the right. In the figure, we assume that the read mode is selected, as the devi is only written to during master initialization. In the preferred embodiment, it is organized as 127 2-bit words.
- CW is a random access read/write memory. Its addre enters from above and data output is to the right. In the fi we assume that the read mode is selected, as the device is on written to during master initialization. In the preferred embodiment, it is organized as 256 2-bit words.
- Distributor is a data distributor. It has three ou above and a 2-bit control input to the left. When this input is zero, all three outputs are zero. When it is 1, 2, or 3, the first, second or third output goes high respectively, lea the others zero.
- Each gate is a pair of logical and gates used to control the propagation of the data output from CW. Both bi leaving CW center each gate to the left. Inside gate there two 2-input and gates. One input from each becomes a common control input shown entering from below. The remaining two inputs connect to the two entering data lines. The outputs the gates are shown to the right. When the control input is low, the gate outputs zero. When it is high, gate simply propagates its two bit input. The combination of the three gate circuits and the distributor circuit forms a variable shift register which sh the output of CW, depending upon the output of PW. This aff the computation of the final weight.
- TOTM is an add-latch device. Its input enters abo It is triggered on a negative ⁇ transition.
- TOTM is a 17-bit latch together with an adder having one 17-bit input and one 11-bit input.
- R is an add-latch device. Its input enters above and its output exists below. It is triggered on a positive transition provided that T entering from the right is equal one.
- R is an 11-bit latch coup to an adder having one 11-bit input and one four bit input.
- M is an add-latch device. Its input enters above.
- SUBSTITUTE SHEET It is triggered on a negative ⁇ transition.
- it is a 17-bit latch together with an adder havi one 17-bit input and one 11-bit input.
- this diagram illustrates ho the basic circuit of Figure 17 may be considerably enhanced without sacrificing speed of processing.
- befor data reaches the core or data selector, circuit 402 and the basic word associator circuit 112 that is identical to that shown in Figure 17, several tasks are performed.
- a memory word is fetched corresponding to the current column position being processed. If this word is zero, then the current column is ignored. This is accomplished by using the double skip on zero circuit 220 of well known design.
- This circuit merely blocks propagation of all timing signals durin the current character pair. Therefore, the circuit ignores the current column. Whereas the circuit of Figure 17 process every column unconditionally, this facility permits column selection in the circuit of Figure 18.
- the fetched word i non zero, then it is used to select one of three tables to be used in translating the data character from the record before it reaches the select circuit 402. This is called synonym processing and permits additional flexibility.
- the facilitie above are implemented via the random access memory's SEL 208 and the three random access memory's labels SYN 202, 204, and 206, and by the SEL 208 component which simply selects one of the three outputs from the SYN memories 202, 204, and 206.
- the SEL 208 is of any well known design.
- the SYN 202, 204 an 206 is a set of three random access memories of a well known design. If the translated value of a record character is zer
- MV 222 is a one bit latch of a well known design. This permits the definition of missing value fields not to detract from the measure of the similarity between the record and the query.
- Position bus 224 is connected to SEL 2 and PW 226 that is a random access memory of well known desig.
- Figure 18 implements a weighing scheme wherein the column number currently under consideration and the current characte are used to determine a weight which is to be added to R inst of "1". In this way, one can weight characters heavier than others.
- Figure 18 contains one such circuit. In this circuit, each alphabet character is assigned a two bi weight. This weights 0, 1, 2, 3 are possible. Each column position is also assigned a weight also two bits. But this weight is used to control a shift register so that here the possible weights are 0, 1, 2, 4. The character weight is effectively multiplied by the column weight to arrive at the final weight.
- a complete word associator circuit must of course contain two copies of the circuit of Figure 18.
- the character is not processed.
- This is accomplishe the "single skip on zero" circuit 230 which blocks propagat of timing signals for the duration of a single character.
- the weight scheme is implemented by the random access memories PW 226 and CW 242 of well known design and the selectable shift register 244 formed by the distributor and gate components 248, 250, and 252 and by the single ski on zero circuit 230, all of which are of well known designs
- the final result M needed to divide by N(N+L) where N is the length of the wor under comparison, to arrive at the measure of similarity.
- this denominator must be compu since it will depend upon the weights encountered during processing.
- TOTR 254 and TOTM 256 that are add-latches, compute a denominator term.
- a corresponding term is computed by the other copy of the circuit.
- the sum of these two terms is the final denominator.
- the final numerator is twice the sum of the two M values read out of the two circuit copies.
- the similarity between the query and bus words is the quotient of the numerator and the denominator quantities.
- the circuit 112' in the lower right of Figure 18 is recognizable as very simila to the circuit of Figure 17. The only difference is that t selection component is now external and R may now be update by quantities other than "1".
- the circuit of Figure 18 is divided by dashed lin into three stages designated by I, II and III. Note that busses passing from stage to stage are broken. These indic that buffers might be inserted to achieve a pipeline with three stages. In this way the circuit can process data as
- INSTITUTE SHEET (OMPI io fast as the circuit of Figure 17. Without pipeline buffers, the circuit is two to three times slower.
- the timing signal are labeled identically in each stage but may vary from stage to stage both because of the optional pipeline and bec of the skip on zero circuits.
- the circuit of Figure 18 must be initialized befor use.
- a master initialization must be performed once per sea to establish weights, etc. This initialization must load th 208, SYN 202, 204 and 206, PW 226, and CW 242 memories.
- Als the MV 222 flag must be set or reset.
- the tally memory in 112' not illustrated must be set to zero as must t R and M, not shown, the TOTR 254 and TOTM 256 add-latches. each record is processed, the contents of M, not shown in 11 and TOTM 256 are read out of the circuit.
- th bus data character must be stable on the bus even during the processing of the query character. This permits the bus character to be translated while the query character, which does not pass through synonym translation, is processed. Th query translation is better left to software since the query is fixed during a search.
Abstract
Description
Claims
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PCT/US1983/001540 WO1985001600A1 (en) | 1983-10-04 | 1983-10-04 | String comparator device system, circuit and method |
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EP0157768A1 EP0157768A1 (en) | 1985-10-16 |
EP0157768A4 true EP0157768A4 (en) | 1987-12-09 |
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Citations (3)
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EP0031493A1 (en) * | 1979-12-28 | 1981-07-08 | International Business Machines Corporation | Alpha content match prescan method and system for automatic spelling error correction |
US4385371A (en) * | 1981-02-09 | 1983-05-24 | Burroughs Corporation | Approximate content addressable file system |
EP0136379A2 (en) * | 1983-10-03 | 1985-04-10 | Proximity Technology Inc. | Word comparator means and method |
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GB1588827A (en) * | 1978-05-31 | 1981-04-29 | System Dev Corp | Data processor method and means for determining degree of match between two data arrays |
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1983
- 1983-10-04 EP EP19830903352 patent/EP0157768A4/en not_active Ceased
- 1983-10-04 WO PCT/US1983/001540 patent/WO1985001600A1/en not_active Application Discontinuation
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Publication number | Priority date | Publication date | Assignee | Title |
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EP0031493A1 (en) * | 1979-12-28 | 1981-07-08 | International Business Machines Corporation | Alpha content match prescan method and system for automatic spelling error correction |
US4385371A (en) * | 1981-02-09 | 1983-05-24 | Burroughs Corporation | Approximate content addressable file system |
EP0136379A2 (en) * | 1983-10-03 | 1985-04-10 | Proximity Technology Inc. | Word comparator means and method |
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See also references of WO8501600A1 * |
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