EP0132646B1 - Hochgeschwindigkeitsmultiplizierer für Fest- und Gleitkommaoperanden - Google Patents

Hochgeschwindigkeitsmultiplizierer für Fest- und Gleitkommaoperanden Download PDF

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Publication number
EP0132646B1
EP0132646B1 EP19840107808 EP84107808A EP0132646B1 EP 0132646 B1 EP0132646 B1 EP 0132646B1 EP 19840107808 EP19840107808 EP 19840107808 EP 84107808 A EP84107808 A EP 84107808A EP 0132646 B1 EP0132646 B1 EP 0132646B1
Authority
EP
European Patent Office
Prior art keywords
bits
operands
register
fractional
exponent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19840107808
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English (en)
French (fr)
Other versions
EP0132646A2 (de
EP0132646A3 (en
Inventor
Steven Lee George
James Lee Hefner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US515845 priority Critical
Priority to US06/515,845 priority patent/US4594679A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0132646A2 publication Critical patent/EP0132646A2/de
Publication of EP0132646A3 publication Critical patent/EP0132646A3/en
Application granted granted Critical
Publication of EP0132646B1 publication Critical patent/EP0132646B1/de
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system, floating-point numbers
    • G06F7/487Multiplying; Dividing
    • G06F7/4876Multiplying
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/3808Details concerning the type of numbers or the way they are handled
    • G06F2207/3812Devices capable of handling different types of numbers
    • G06F2207/3816Accepting numbers of variable word length
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/3808Details concerning the type of numbers or the way they are handled
    • G06F2207/3812Devices capable of handling different types of numbers
    • G06F2207/3824Accepting both fixed-point and floating-point numbers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding, overflow
    • G06F7/49905Exception handling
    • G06F7/4991Overflow or underflow
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding, overflow
    • G06F7/49936Normalisation mentioned as feature only

Claims (1)

  1. Eine digitale Multipliziereinheit zum Multiplizieren von zwei Operanden und zur Erzeugung eines Endproduktes, welche jeweils Mantissenbits, Charakteristik-Bits und ein Vorzeichenbit aufweisen, enthaltend ein erstes und ein zweites Mantissenregister (34-37; 38―41; 42-45) zur Aufnahme der Mantissenbits der beiden Operanden, Multipliziermittel, welche mit dem ersten und dem zweiten Mantissenregister (34-37; 38―41; 42-45) zur Erzeugung resultierender Mantissenbits verbunden sind, ein erstes und ein zweites Exponentenregister (31; 32; 33) zur Aufnahme der Charakteristik-Bits der beiden Operanden, Exponentenaddier-Mittel (61), welche mit dem ersten und dem zweiten Exponentenregister (31; 32; 33) zur Erzeugung resultierender Charakteristik-Bits verbunden sind, Logikmittel (XOR) zur Erzeugung eines resultierenden Vorzeichenbits in Abhängigkeit der Vorzeichenbits der beiden Operanden, Schiebemittel (75), welche mit der Multipliziereinheit zur Durchführung von notwendigen Verschiebungen der resultierenden Mantissenbits verbunden sind, gekennzeichnet dadurch, daß das erste und das zweite Mantissenregister (34-37; 38―41; 42-45) jeweils eine Vielzahl von Teilregistern (34-45) aufweist, welche einen Teil der Mantissenbits der beiden Operanden aufnehmen, daß die Multipliziermittel eine Vielzahl von Teilmultiplizierern (MULTIPLY) aufweisen, die jeweils mit entsprechenden Teilregistern des ersten und des zweiten Mantissenregisters (34-37; 38―41; 42-45) verbunden sind, und die jeweils entsprechende Teile der Mantissenbits der beiden Operanden aufnehmen sowie entsprechende Partialprodukte erzeugen, sowie einen Addierer (55, 56), welcher mit jedem der Teilmultiplizierer (MULTIPLY) verbunden ist und die Partialprodukte zur Erzeugung der resultierenden Mantissenbits aufsummiert, daß jedes der Teilregister des ersten Mantissenregisters (34-37; 42-45) aufweist ein erstes Register (34, 35, 36, 37) zur Aufnahme des genannten Teiles der Mantissenbits von einem der beiden Operanden in einem ersten Zyklus, und ein zweites Register (42, 43, 44, 45) welches mit dem ersten Register (34, 35, 36,37) zur Aufnahme des Inhalts des ersten Registers (34, 35, 36, 37) verbunden ist, wenn die Teilregister des zweiten Mantissenregisters (38-41) den genannten Teil des anderen der beiden Operanden in einem darauffolgenden Zyklus aufnehmen, daß die Logikmittel (XOR) zur Erzeugung eines resultierenden Vorzeichenbits mit dem ersten und dem zweiten Exponentenregister (31, 32) verbunden sind, wobei das erste und das zweite Exponentenregister (31, 32) die Vorzeichenbits der beiden Operanden erhält, daß Exponentenzusammensetzungs-Mittel (64) vorgesehen sind, welche mit dem Addierer (55, 56), den Logikmitteln (XOR) und den Exponentenaddiermitteln (61) zum Zusammensetzen des korrekten resultierenden Vorzeichenbits und der Charakteristik-Bits, welche zum Endprodukt gehören, verbunden sind, und daß mit den Schiebemitteln (75) verbundene Mantissen-Zusammensetzungsmittel (60) zum Zusammensetzen der korrekten resultierenden Mantissenbits mit dem Endprodukt vorgesehen sind.
EP19840107808 1983-07-21 1984-07-05 Hochgeschwindigkeitsmultiplizierer für Fest- und Gleitkommaoperanden Expired - Lifetime EP0132646B1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US515845 1983-07-21
US06/515,845 US4594679A (en) 1983-07-21 1983-07-21 High speed hardware multiplier for fixed floating point operands

Publications (3)

Publication Number Publication Date
EP0132646A2 EP0132646A2 (de) 1985-02-13
EP0132646A3 EP0132646A3 (en) 1987-04-15
EP0132646B1 true EP0132646B1 (de) 1991-01-16

Family

ID=24052998

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19840107808 Expired - Lifetime EP0132646B1 (de) 1983-07-21 1984-07-05 Hochgeschwindigkeitsmultiplizierer für Fest- und Gleitkommaoperanden

Country Status (6)

Country Link
US (1) US4594679A (de)
EP (1) EP0132646B1 (de)
JP (1) JPH0414366B2 (de)
AR (1) AR241060A1 (de)
BR (1) BR8401796A (de)
DE (1) DE3483929D1 (de)

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US4716539A (en) * 1984-12-31 1987-12-29 Gte Communication Systems Corporation Multiplier circuit for encoder PCM samples
JPH0368413B2 (de) * 1985-10-09 1991-10-28 Hitachi Seisakusho Kk
JPH069028B2 (ja) * 1986-02-18 1994-02-02 日本電気株式会社 演算装置
US4974198A (en) * 1986-07-16 1990-11-27 Nec Corporation Vector processing system utilizing firm ware control to prevent delays during processing operations
US4991131A (en) * 1987-10-06 1991-02-05 Industrial Technology Research Institute Multiplication and accumulation device
US4893268A (en) * 1988-04-15 1990-01-09 Motorola, Inc. Circuit and method for accumulating partial products of a single, double or mixed precision multiplication
US4926371A (en) * 1988-12-28 1990-05-15 International Business Machines Corporation Two's complement multiplication with a sign magnitude multiplier
US4953119A (en) * 1989-01-27 1990-08-28 Hughes Aircraft Company Multiplier circuit with selectively interconnected pipelined multipliers for selectively multiplication of fixed and floating point numbers
JPH04205559A (en) * 1990-11-30 1992-07-27 Koufu Nippon Denki Kk Vector arithmetic unit
US5187679A (en) * 1991-06-05 1993-02-16 International Business Machines Corporation Generalized 7/3 counters
JPH0820942B2 (ja) * 1991-09-26 1996-03-04 インターナショナル・ビジネス・マシーンズ・コーポレイション 高速乗算器
US5253195A (en) * 1991-09-26 1993-10-12 International Business Machines Corporation High speed multiplier
US5200912A (en) * 1991-11-19 1993-04-06 Advanced Micro Devices, Inc. Apparatus for providing power to selected portions of a multiplying device
US5265043A (en) * 1991-12-23 1993-11-23 Motorola, Inc. Wallace tree multiplier array having an improved layout topology
US5740398A (en) * 1993-10-18 1998-04-14 Cyrix Corporation Program order sequencing of data in a microprocessor with write buffer
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US6219773B1 (en) 1993-10-18 2001-04-17 Via-Cyrix, Inc. System and method of retiring misaligned write operands from a write buffer
US5615402A (en) * 1993-10-18 1997-03-25 Cyrix Corporation Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
JP3583474B2 (ja) * 1994-06-29 2004-11-04 株式会社ルネサステクノロジ 乗算装置
US5586070A (en) * 1994-08-03 1996-12-17 Chromatic Research, Inc. Structure and method for embedding two small multipliers in a larger multiplier
US5912832A (en) * 1996-09-12 1999-06-15 Board Of Regents, The University Of Texas System Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders
US6021422A (en) * 1998-03-04 2000-02-01 International Business Machines Corporation Partitioning of binary quad word format multiply instruction on S/390 processor
US6055554A (en) * 1998-03-04 2000-04-25 Internatinal Business Machines Corporation Floating point binary quad word format multiply instruction unit
US6523055B1 (en) 1999-01-20 2003-02-18 Lsi Logic Corporation Circuit and method for multiplying and accumulating the sum of two products in a single cycle
US6480872B1 (en) * 1999-01-21 2002-11-12 Sandcraft, Inc. Floating-point and integer multiply-add and multiply-accumulate
US6341300B1 (en) * 1999-01-29 2002-01-22 Sun Microsystems, Inc. Parallel fixed point square root and reciprocal square root computation unit in a processor
US6912557B1 (en) * 2000-06-09 2005-06-28 Cirrus Logic, Inc. Math coprocessor
US6829627B2 (en) * 2001-01-18 2004-12-07 International Business Machines Corporation Floating point unit for multiple data architectures
KR100402734B1 (ko) * 2001-12-21 2003-10-22 한국전자통신연구원 부호화된 피승수를 사용하는 고정 소수점 곱셈 장치 및 그방법
US7188133B2 (en) * 2002-06-20 2007-03-06 Matsushita Electric Industrial Co., Ltd. Floating point number storage method and floating point arithmetic device
US8073892B2 (en) * 2005-12-30 2011-12-06 Intel Corporation Cryptographic system, method and multiplier
US7519646B2 (en) * 2006-10-26 2009-04-14 Intel Corporation Reconfigurable SIMD vector processing system
US8706790B1 (en) * 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
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Also Published As

Publication number Publication date
AR241060A1 (es) 1991-04-30
DE3483929D1 (de) 1991-02-21
EP0132646A3 (en) 1987-04-15
US4594679A (en) 1986-06-10
EP0132646A2 (de) 1985-02-13
JPH0414366B2 (de) 1992-03-12
JPS6027026A (en) 1985-02-12
AR241060A2 (es) 1991-04-30
BR8401796A (pt) 1985-03-19

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