EP0105324A4 - OHMIC CONTACT FOR N-TYPE GaAs. - Google Patents

OHMIC CONTACT FOR N-TYPE GaAs.

Info

Publication number
EP0105324A4
EP0105324A4 EP19830901446 EP83901446A EP0105324A4 EP 0105324 A4 EP0105324 A4 EP 0105324A4 EP 19830901446 EP19830901446 EP 19830901446 EP 83901446 A EP83901446 A EP 83901446A EP 0105324 A4 EP0105324 A4 EP 0105324A4
Authority
EP
European Patent Office
Prior art keywords
layer
germanium
gold
contact
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19830901446
Other languages
German (de)
French (fr)
Other versions
EP0105324A1 (en
Inventor
James M Frary
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0105324A1 publication Critical patent/EP0105324A1/en
Publication of EP0105324A4 publication Critical patent/EP0105324A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor devices and, in particular, to ohmic contact metallization for N-type gallium-arsenide (GaAs) devices.
  • GaAs gallium-arsenide
  • the contact metallization to N-type GaAs comprises gold-germanium and nickel layers wherein the gold-germanium layer is formed by evaporation from a common melt, or pellets or by co-evaporation.
  • the resulting alloy typically comprises 88% gold-12% germanium by weight.
  • a nickel layer is then deposited and, occasionally, a gold layer is deposited atop the nickel layer.
  • the resulting structure while providing an ohmic contact, exhibits inconsistent contact resistance, which affects device saturation characteristics. Further, in tests performed on field effect transistor (FET) devices, it has been found that device saturation current changes during processing. The change is not uniform, however. Wafers processed together in a lot do not exhibit the same amount of change.
  • FET field effect transistor
  • the appearance of the surface of the contact region varies from an overall rough texture to a light texture with lumps, which are believed due to non-uniform alloying of the gold and germanium.
  • the surface texture can cause contact problems, e.g. when a lump is near a step. If such must be accounted for in design rules, it raises the lower limit in fine line geometries.
  • Another object of the present invention is to provide an improved contact for N-type GaAs devices. Another object of the present invention is to consistently provide a lower resistance contact for GaAs devices than has been attainable in the prior art.
  • a further object of the present invention is to minimize or eliminate variations in GaAs device characteristics due to contact metallization.
  • Another object of the present invention is to provide a contact having improved morphology for GaAs devices.
  • a multi-layer contact metallization comprises, as separately deposited layers, germanium, gold, nickel and, optionally, a second gold layer.
  • FIGURE 1 illustrates a GaAs FET in accordance with the prior art.
  • FIGURE 2 illustrates a GaAs FET in accordance with a preferred embodiment of the present invention.
  • FIGURE 1 illustrates what is know in the art as a dual gate HESFET (metal semiconductor field effect transistor) having source and drain contacts in accordance with the prior art.
  • MESFET 10 comprises a substrate 11 which may, for example, comprise semi-insulating gallium arsenide. Overlying substrate 11 is N-type conductivity gallium arsenide layer 12 which forms the active layer of the MESFET. Overlying separated portions of layer 12 are ohmic contact metallizations 13 and 14 which form the source and drain of the FET. As known in the prior art, these contact metallizations comprise an alloy of gold and germanium, typically 88% gold and 12% germanium by weight. Between source and drain contacts 13 and 14 are gate . contacts 15 and 16. Gate contacts 15 and 16 typically comprise a titanium, platinum, and gold metal system.
  • contact metal layers 17 and 18 Overlying source and drain contacts 13 and 14 are contact metal layers 17 and 18, respectively.
  • the contact metal layer is typically 40 n . thick and comprises nickel.
  • the gold-germanium ohmic contact layer is typically 120 nm. thick.
  • FIGURE 2 illustrates a dual gate MESFET having source drain contacts formed in accordance with the present invention.
  • semi-insulating substrate 11 has N-type conductivity gallium arsenide layer 12 formed thereon.
  • a layer of germanium is deposited in predeter ⁇ mined, spaced apart regions to form source and drain contacts 21 and 22.
  • the germanium layer is from 45 to 75 nm. thick and is preferably approximately 60 nm. thick.
  • Overlying germanium layers 21 and 22 are gold layers 23 and 24, respectively, which may be from 100 to 160 nm. thick and are preferably approximately 120 nm. thick.
  • Overlying gold layers 23 and 24 are nickel layers 25 and 26 respectively. These nickel layers may be from 30 to 50 nm. thick and are preferably appro imately 40 nm. thick.
  • Devices in accordance with the present invention can be made by conventional processing steps. Specifically, the germanium, gold, and nickel layers are deposited over a patterned layer of positive photoresist which has been deposited on N-type conductivity layer 12. The photoresist is removed in a conventional lift-off technique to pattern the germanium, gold, and nickel layers. The wafer is then subjected to an alloy step in which the germanium and gold layers are brought to a temperature above their 356°C eutectic temperature, forming an alloy therebetween. For example, the wafer is transported through an oven having a maximum temperature of approximately 470° at a rate such that the wafer temperature is brought to approximately 360 o for a short time, e.g. 10 seconds.
  • the entire alloy step typically takes about two and one-half minutes.
  • the gate contact metallization is applied, also using the lift-off technique, preferably the gate contact metal, e.g. titanium-platinum-gold, is also applied to the source drain metallizations to provide contact areas thereon.
  • the wafer is then passivated and diced to form separate devices, which may be either discrete transistors or integrated circuits.
  • the germanium increases surface doping concentration, thereby decreasing the barrier height to form an ohmic contact with the gold, which provides a low contact resistance.
  • the nickel serves to improve morphology and wetting characteristics to the surface of the source and drain contacts. It is believed that the nickel layer also prevents deformation of the germanium and gold layers during the eutectic melt.
  • Devices built in accordance with the present invention exhibit as little as one tenth the contact resistance of prior art devices. For any given material, the contact resistance is consistently lower with the contact of the present invention.
  • the surface morphology of the source and drain contacts is markedly smoother than those of the prior art. This is believed to be due to the more uniform alloying of the gold and germanium. In prior art devices, despite the presence of the nickel layer, the surface morphology of the contacts is characteristically rough.

Abstract

An improved multi-layer contact for N-type GaAs comprising discrete layers of germanium (21, 22), gold (23, 24), and nickel (25, 26).

Description

OHMIC CONTACT FOR N-TYPE GaAs
Background
This invention relates to semiconductor devices and, in particular, to ohmic contact metallization for N-type gallium-arsenide (GaAs) devices.
In the past, and currently, the contact metallization to N-type GaAs comprises gold-germanium and nickel layers wherein the gold-germanium layer is formed by evaporation from a common melt, or pellets or by co-evaporation. The resulting alloy typically comprises 88% gold-12% germanium by weight. A nickel layer is then deposited and, occasionally, a gold layer is deposited atop the nickel layer.
The resulting structure, while providing an ohmic contact, exhibits inconsistent contact resistance, which affects device saturation characteristics. Further, in tests performed on field effect transistor (FET) devices, it has been found that device saturation current changes during processing. The change is not uniform, however. Wafers processed together in a lot do not exhibit the same amount of change.
In devices of the prior art, the appearance of the surface of the contact region varies from an overall rough texture to a light texture with lumps, which are believed due to non-uniform alloying of the gold and germanium. The surface texture can cause contact problems, e.g. when a lump is near a step. If such must be accounted for in design rules, it raises the lower limit in fine line geometries.
In view of the foregoing, it is therefore an object of the present invention to provide an improved contact for N-type GaAs devices. Another object of the present invention is to consistently provide a lower resistance contact for GaAs devices than has been attainable in the prior art.
A further object of the present invention is to minimize or eliminate variations in GaAs device characteristics due to contact metallization.
Another object of the present invention is to provide a contact having improved morphology for GaAs devices.
Summary
The foregoing objects are achieved in the present invention wherein a multi-layer contact metallization comprises, as separately deposited layers, germanium, gold, nickel and, optionally, a second gold layer.
A more complete understanding of the present invention can be obtained by considering the following detailed description in conjunction with the accompanying drawings, in which: FIGURE 1 illustrates a GaAs FET in accordance with the prior art.
FIGURE 2 illustrates a GaAs FET in accordance with a preferred embodiment of the present invention.
Detailed Description
FIGURE 1 illustrates what is know in the art as a dual gate HESFET (metal semiconductor field effect transistor) having source and drain contacts in accordance with the prior art. Specifically, MESFET 10 comprises a substrate 11 which may, for example, comprise semi-insulating gallium arsenide. Overlying substrate 11 is N-type conductivity gallium arsenide layer 12 which forms the active layer of the MESFET. Overlying separated portions of layer 12 are ohmic contact metallizations 13 and 14 which form the source and drain of the FET. As known in the prior art, these contact metallizations comprise an alloy of gold and germanium, typically 88% gold and 12% germanium by weight. Between source and drain contacts 13 and 14 are gate . contacts 15 and 16. Gate contacts 15 and 16 typically comprise a titanium, platinum, and gold metal system.
Overlying source and drain contacts 13 and 14 are contact metal layers 17 and 18, respectively. The contact metal layer is typically 40 n . thick and comprises nickel. The gold-germanium ohmic contact layer is typically 120 nm. thick.
FIGURE 2 illustrates a dual gate MESFET having source drain contacts formed in accordance with the present invention. Specifically, semi-insulating substrate 11 has N-type conductivity gallium arsenide layer 12 formed thereon. Instead of a mixture or alloy of gold and germanium, a layer of germanium is deposited in predeter¬ mined, spaced apart regions to form source and drain contacts 21 and 22. The germanium layer is from 45 to 75 nm. thick and is preferably approximately 60 nm. thick. Overlying germanium layers 21 and 22 are gold layers 23 and 24, respectively, which may be from 100 to 160 nm. thick and are preferably approximately 120 nm. thick. Overlying gold layers 23 and 24 are nickel layers 25 and 26 respectively. These nickel layers may be from 30 to 50 nm. thick and are preferably appro imately 40 nm. thick.
Devices in accordance with the present invention can be made by conventional processing steps. Specifically, the germanium, gold, and nickel layers are deposited over a patterned layer of positive photoresist which has been deposited on N-type conductivity layer 12. The photoresist is removed in a conventional lift-off technique to pattern the germanium, gold, and nickel layers. The wafer is then subjected to an alloy step in which the germanium and gold layers are brought to a temperature above their 356°C eutectic temperature, forming an alloy therebetween. For example, the wafer is transported through an oven having a maximum temperature of approximately 470° at a rate such that the wafer temperature is brought to approximately 360 o for a short time, e.g. 10 seconds. The entire alloy step typically takes about two and one-half minutes. Thereafter, the gate contact metallization is applied, also using the lift-off technique, preferably the gate contact metal, e.g. titanium-platinum-gold, is also applied to the source drain metallizations to provide contact areas thereon. The wafer is then passivated and diced to form separate devices, which may be either discrete transistors or integrated circuits.
In operation, the germanium increases surface doping concentration, thereby decreasing the barrier height to form an ohmic contact with the gold, which provides a low contact resistance. The nickel serves to improve morphology and wetting characteristics to the surface of the source and drain contacts. It is believed that the nickel layer also prevents deformation of the germanium and gold layers during the eutectic melt.
Devices built in accordance with the present invention exhibit as little as one tenth the contact resistance of prior art devices. For any given material, the contact resistance is consistently lower with the contact of the present invention. In addition, the surface morphology of the source and drain contacts is markedly smoother than those of the prior art. This is believed to be due to the more uniform alloying of the gold and germanium. In prior art devices, despite the presence of the nickel layer, the surface morphology of the contacts is characteristically rough.
There is thus provided by the present invention an improved contact metallization for N-type conductivity gallium arsenide regions. Device characteristics are improved and made consistent, and contact resistance is reduced. In addition, contacts in accordance with the present invention have improved thermal stability as compared to prior art contacts. Having thus described the invention it will be apparent to those of skill in the art that modifications can be made within the spirit and scope of the present invention. For example, an N+ conductivity region is sometimes formed over the N-type conductivity region. A comparison of devices made in accordance with the present invention, and including an N+ layer beneath the contact metallization, with devices having contacts in accordance with the prior art, the least favorable comparison showed < contact resistance for devices in accordance with the present invention as 75% of the contact resistance of devices having contacts built in accordance with the prior art. If desired, a gold-germanium layer can be included between the germanium and gold layers. While described with respect to a dual gate MESFET, it is understood that the contact metallization of the present invention can be used for any device having a gallium arsenide N-type conductivity region to which contact is made.
"VΛP

Claims

Claims
1. In a semiconductor device having at least one GaAs N-type conductivity region, an ohmic contact to said region comprising? a layer consisting essentially of germanium in contact with and overlying at least a portion of said region; and a layer consisting essentially of gold overlying said germanium layer.
2. The device as set forth in claim 1 and further comprising a layer consisting essentially of nickel overlying said gold layer.
3. The device as set forth in claim 2 and further comprising a gold layer overlying said nickel layer.
4. The device as set forth in claim 1 wherein said germanium layer is 45 to 75 nm. thick and wherein said gold layer is 100 to 160 nm. thick.
5. The device as set forth in claim 3 wherein said germanium layer is approximately 60 nm. thick and said gold layer is approximately 120 nm. thick.
6. The device as set forth in claim 5 wherein said region comprises germanium diffused from said germanium layer.
7. The device as set forth in claim 2 wherein said nickel layer is 30 to 50 nm. thick.
8. The device as set forth in claim 7 wherein said nickel is approximately 40 nm. thick.
EP19830901446 1982-04-12 1983-03-01 OHMIC CONTACT FOR N-TYPE GaAs. Withdrawn EP0105324A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36749882A 1982-04-12 1982-04-12
US367498 1982-04-12

Publications (2)

Publication Number Publication Date
EP0105324A1 EP0105324A1 (en) 1984-04-18
EP0105324A4 true EP0105324A4 (en) 1986-07-24

Family

ID=23447416

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19830901446 Withdrawn EP0105324A4 (en) 1982-04-12 1983-03-01 OHMIC CONTACT FOR N-TYPE GaAs.

Country Status (3)

Country Link
EP (1) EP0105324A4 (en)
JP (1) JPS59500542A (en)
WO (1) WO1983003713A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213261B (en) * 1984-12-20 1989-12-14 Sgs Thomson Microelectronics SEMICONDUCTOR DEVICE WITH METALLISATION WITH MORE THICKNESS AND PROCEDURE FOR ITS MANUFACTURE.
FR2602094B1 (en) * 1986-07-23 1988-10-21 Labo Electronique Physique SEMICONDUCTOR DEVICE OF THE BIPOLAR TRANSISTOR TYPE WITH HETEROJUNCTION
JP2907452B2 (en) * 1989-08-30 1999-06-21 三菱化学株式会社 Electrodes for compound semiconductors
GB8921004D0 (en) * 1989-09-15 1989-11-01 Secr Defence Ohmic contact for gaas and gaa1as
JPH03167877A (en) * 1989-11-28 1991-07-19 Sumitomo Electric Ind Ltd Ohmic electrode of n-type cubic boron nitride and its formation
EP0457344A3 (en) * 1990-05-18 1992-03-11 Kabushiki Kaisha Toshiba Semiconductor light-emitting device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3702290A (en) * 1970-09-01 1972-11-07 Fairchild Camera Instr Co Method of forming contacts to epitaxial gaas and the resulting structure
FR2358751A1 (en) * 1976-07-15 1978-02-10 Siemens Ag SEMICONDUCTOR COMPONENT INCLUDING A SCHOTTKY CONTACT CONTAINING A LOW VALUE SERIAL RESISTOR AND PROCESS FOR ITS MANUFACTURING

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3981073A (en) * 1973-06-21 1976-09-21 Varian Associates Lateral semiconductive device and method of making same
US3871016A (en) * 1973-12-26 1975-03-11 Gen Electric Reflective coated contact for semiconductor light conversion elements
JPS5439573A (en) * 1977-09-05 1979-03-27 Toshiba Corp Compound semiconductor device
US4186410A (en) * 1978-06-27 1980-01-29 Bell Telephone Laboratories, Incorporated Nonalloyed ohmic contacts to n-type Group III(a)-V(a) semiconductors
JPS5530834A (en) * 1978-08-25 1980-03-04 Nec Corp Method of forming ohmic contact in semiconductor pellet
US4268844A (en) * 1979-12-31 1981-05-19 The United States Of America As Represented By The Secretary Of The Navy Insulated gate field-effect transistors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3702290A (en) * 1970-09-01 1972-11-07 Fairchild Camera Instr Co Method of forming contacts to epitaxial gaas and the resulting structure
FR2358751A1 (en) * 1976-07-15 1978-02-10 Siemens Ag SEMICONDUCTOR COMPONENT INCLUDING A SCHOTTKY CONTACT CONTAINING A LOW VALUE SERIAL RESISTOR AND PROCESS FOR ITS MANUFACTURING

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO8303713A1 *

Also Published As

Publication number Publication date
EP0105324A1 (en) 1984-04-18
JPS59500542A (en) 1984-03-29
WO1983003713A1 (en) 1983-10-27

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Inventor name: FRARY, JAMES M.