EP0085385A2 - Dispositif d'affranchissement électronique controllé par un système à microprocesseur - Google Patents

Dispositif d'affranchissement électronique controllé par un système à microprocesseur Download PDF

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Publication number
EP0085385A2
EP0085385A2 EP83100639A EP83100639A EP0085385A2 EP 0085385 A2 EP0085385 A2 EP 0085385A2 EP 83100639 A EP83100639 A EP 83100639A EP 83100639 A EP83100639 A EP 83100639A EP 0085385 A2 EP0085385 A2 EP 0085385A2
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EP
European Patent Office
Prior art keywords
data
microprocessor
random access
memories
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83100639A
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German (de)
English (en)
Other versions
EP0085385A3 (fr
Inventor
Frank T. Check, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pitney Bowes Inc
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Pitney Bowes Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23348071&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0085385(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Pitney Bowes Inc filed Critical Pitney Bowes Inc
Priority to EP86116058A priority Critical patent/EP0231452B2/fr
Publication of EP0085385A2 publication Critical patent/EP0085385A2/fr
Publication of EP0085385A3 publication Critical patent/EP0085385A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
    • G07B2017/00395—Memory organization
    • G07B2017/00411—Redundant storage, e.g. back-up of registers

Definitions

  • This invention relates to micropressor systems and is applicable to electronic postage meters having electronic accounting units.
  • An electronic postage meter having an accounting unit with a microprocessor, and nonvolatile memory for storing accounting data is disclosed, for example, in U.S. Patent Application Serial No. 089,413 (U.S. Patent No. 4,301,507).
  • the accounting data is stored in the random access memory and retrieved from the random access memory by way of common address and data lines of the microcomputer system. While in most instances it can be ensured that the accounting data stored in the memory will be correct, there are certain conditions that can occur that can result in non-detectable errors in the data.
  • the microprocessor program for the postal meter thus includes a subroutine for comparing the data stored in the redundant memories, to provide an error indication if the stored data in the two memories is different. While this technique increases the reliability of the stored data, there are certain conditions in which even this type of a redundant system will not enable the determination of an error. It must, of course, be emphasized that, in a postage meter, it is essential that the highest degree of reliability of the accounting data be obtained.
  • An object of the present invention is to provide a microprocessor system for an electronic postage meter having redundant memory wherein the possibility of error conditions that are not detectable is reduced.
  • a microprocessor system for an electronic postage meter characterised by: at least one microprocessor connected to a plurality of address lines, a plurality of data lines, and control line means; and random access memory means connected to said address and data lines and to said control line means to enable storage of data in said memory means and reading of data from said memory means under control of said microprocessor, said random access memory means comprising first and second random access memories each connected to separate groups of said address lines and separate groups of said data lines, whereby data may be transferred to and from said first and second random access memories independently of any common interconnection.
  • a microprocessor system for an electronic postage meter and characterised by: a microprocessor with a plurality of address lines and a plurality of data lines, and control line means, and random access memory means connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor; a printer connected to be controlled by said microprocessor; and feedback means for signalling the setting of the printer means to the microprocessor, wherein said random access memory comprises first and second random access memories; and means independently responsive to feedback from said feedback means to update the accounting data in each of said first and second random access memories.
  • a microprocessor system for an electronic postage meter characterised by: a printing means; first and second microprocessors; first and second accounting memories connected to be separately controlled by said first and second microprocessors, said first and second microprocessors having program routines for separately updating their respective accounting memories to account for the printing of postage by said printing means; and means for comparing the accounting results in said first and second accounting memories for disabling said postage meter in the absence of a valid comparison.
  • a microprocessor system characterised by an address bus having a plurality of address lines; a data bus having a plurality of data lines; a control bus having a plurality of control lines; a microprocessor connected to each of the address lines of data lines of said address and data bus, and coupled to said control bus; and first and second random access memories each connected to different lines of said address bus and different lines of said data bus, whereby said random access memories may be separately addressed.
  • the ports are in the form of a pair of one-way transmission paths with opto couplers 15 and 16 at the secure housing, in order to inhibit the application of any electric potentials to the accounting unit without showing evidence of attempts to damage the unit.
  • the opto couplers preferably provide for two-way serial intercommunication between the units on a bit-by- bit basis, in order to minimize the number of ports necessary in the housing.
  • a pair of random access memories 20, 21 is also provided within the secure housing.
  • the random access memories 20 and 21 are preferably nonvolatile memories of conventional nature, so that accounting data may be stored therein without loss even though external power to the system may be lost.
  • the random access memories may be of the type employing battery back-up, Earom or EEPROM.
  • the random access memory 20 is connected to the central processing unit 10 by way of a plurality of address lines 22 and a plurality of data lines 23.
  • the random access memory is coupled to the central processing unit 10 by way of another plurality of address lines 24, and another plurality of data lines 25. It is necessary that both the address lines and the data lines coupled to the random access memories be different.
  • address lines AO - A7 are of a conventional microprocessor system and may be coupled to the random access memory 20, while address lines CO - C7 are coupled to the random access memory 21.
  • conventional data lines BO - B3 may be coupled to the random access memory 20, with data lines D4 - D7 being coupled to the random access memory 21.
  • redundancy In an accounting system that requires both security and reliability, it is desirable to provide redundancy. A certain degree of redundancy may be obtained if the random access memories are connected to the central processing unit by separate data lines, although employing the same address lines. In such a system, the same data may be stored or retrieved from the two random access memories by way of their respective separate data lines, either simultaneously or at different times under control of the respective chip enable signals. While in many instances such an arrangement will enable the detection of errors, upon comparison of data in the two memories, there are in fact possibilities of error that cannot be detected.
  • the two random access memories may be simultaneously addressed, employing their separate address lines, for the storage or recovery of the same information, this may also result in errors that could not be detectable or correctable. For example, it is possible that a transient on the bus lines could interfere, in the same manner, with the simultaneously transmitted data. Accordingly, as illustrated in Figure 2, the two memories are addressed, with respect to the same data, in a sequential manner. For example, all of the sequential bytes of a message may be first applied to, or received from, the first memory, i.e. memory 1. Following the transfer of this message, with respect to the first memory, the same message is then transmitted with respect to the second memory. It will, of course, be apparent that the term "byte" herein refers to data of a length equal to the number of data lines connected to each memory.
  • each memory may be updated or read simultaneously but with different data being transmitted to or from each memory at any instant, as illustrated in Figure 3.
  • Figures 2 and 3 hence illustrate two techniques for minimizing the occurrence of undetectable errors resulting from the occurrence, for example, of transient pulses. It is apparent that it would be unlikely for the same interference to occur with sequentially transmitted data.
  • the data may be stored in the two memories in a different form.
  • the data stored in one or both of the memories may be coded, in order further to minimize the occurrence of errors undetectable by comparison of the data stored in the two memories.
  • a coder/decoder 30 may be employed to code and decode the data stored in the random access memory 20, applied to and received from the data bus 23.
  • a coder/decoder 31 may optionally be provided for coding and decoding data in the random access memory 21. If such an additional coder/decoder is employed, it is preferable that it have a different coding than that of the coder/ decoder 30.
  • each memory unit may be made independently responsive to determined conditions.
  • the two memories may be independently responsive to each feedback of a printer setting, in order to update the separate memories, with an overriding subroutine being provided for cross-checking, i.e., comparing the data stored in the two memories.
  • the independent control may be, for example, in the form of a memory controller.
  • the positions of the various shutter bars and interposers are also determined by software routines initiated by various externally originating conditions, such as, for example, manually controlled operations for initiating the printing of postage.
  • the error checking routines for checking such sensors, as well as for checking additional conditions such as the correctness of data stored in the memories are hence invoked only when specifically requested in response to external stimuli. Thus, even though a condition may have occurred, between operations of the postage meter, that would eventually cause it to cease operation (i.e. upon the next call for printing of postage), the meter may still deceptively appear externally to be operable.
  • a program for the microprocessor effects the checking of the registers of the random access memory, as well as the various sensors, which may be optical switches, and all other critical data indicators at regular times during the course of operation of the postage meter, rather than simply checking these parameters at startup of the meter and uncalled for by external stimuli.
  • the main routine of the postage meter to which it always returns following the completion of, for example, a postage printing operation, includes software subroutines that periodically check critical parameters, such as the proper positioning of mechanical elements in the meter and the correct comparison of data in memories, as well as the correctness of the data in accordance with control sum data. This technique enables the additional advantageous periodic checking of further sensors mounted, for example, to detect.mechanical violation of the security of the housing.
  • the sensors 50, 51 and 52 may be connected to set a plurality of stages of a shift register 55. It will, of course, be understood that the number of such sensors-may be greater than the three illustrated.
  • the shift register 55 is coupled to the address and read out by the central processing unit 10 at determined times in the main program. A coded bit pattern is provided in the read only memory 11, corresponding to the correct error-free conditions of the sensors. At the times during the program when the sensors are to be tested, the shift register, under control of the central processing unit, shifts out the existing bit pattern for comparison with the stored bit pattern in the read only memory 11.
  • the status of the various sensors in the meter may be continually determined, so that the meter may be disabled as soon as a condition exists that threatens the integrity of the meter.
  • the nonvolatile random access memories 20, 21 of the accounting system are intercoupled with separate microprocessors 60 and 61, each of the microprocessors having a separate read only memory 62, 63 respectively, for storing the operating programs for the respective microprocessor.
  • the read only memory as well as other components of the system, may be incorporated in the same integrated circuit as the microprocessor. Since the two microprocessors are separately controlled, and have separate address and data lines 64, 65 respectively, the two random access memories are thereby entirely independently controlled.
  • the two microprocessors separately communicate with the control unit 13 and printer 82 by way of separate selector switches 70 and 71 addressed by the respective microprocessors 60 and 61.
  • each of the microprocessors may receive signals from the printer and control unit, and each of them may also transmit messages.
  • data processed in the two microprocessors may be compared by means of a data latch 72 controllable by either of the microprocessors.
  • the printer unit is more completely shown as comprised of a microprocessor 80 coupled to the opto couplers 17 and 18, and controlling a print setter 81.
  • the print setter 81 sets the printwheels in a printer 82, the setting of the printwheels being fed back to the microprocessor 80 by way of a feedback path 83.
  • This feedback enables the printer unit to determine if an error has occurred in the setting of the printwheels, and thereby to disable the meter in the event of an erroneous setting.
  • the feedback setting may be applied from the microprocessor 80 to the opto couplers 17 and 18, thereby enabling the two microprocessors in the accounting system to be separately responsive to the feedback signals, for accounting for postage to be printed.
  • the function of disabling the meter in the illustrated embodiments, may be effected by inhibiting, under program control, operation of the mechanical elements of the meter.
  • the existence of an error requiring disabling of the meter may direct the routines of the microprocessor to perform an endless loop. Errors that do not require disabling of the meter may be displayed, under control of the microprocessor, by means of the display 73 coupled to the external control unit.
  • redundant nonvolatile memories are provided in the accounting unit of an electronic postage meter, the accounting unit having a microprocessor controlled to store accounting data redundantly in' the two memories.
  • the two redundant memories are interconnected with the microprocessor, i.e. the microcomputer bus, by way of entirely separate groups of data and address lines.
  • various error conditions such as the shorting of a pair of address lines, will not result in the erroneous addressing of both of the memories. Accordingly, under such conditions, the shorting of a pair of address lines will not result in the storage of the same data in both of the memories, so that a comparison of stored data will result in the detection of the error condition.
  • the redundancy of the accounting system may be increased by also employing redundant microprocessors for controlling the two memories.
  • the program of the microprocessor may be directed to the periodic testing of various critical parameters within the microprocessor, as part of a main routine, the testing routine only being interrupted, if necessary, during a conventional postage printing operation such as the printing of postage and accounting therefor.
  • the routine of the postage meter enables the continuous testing of such parameters, so that the postage meter may be disabled as soon as a condition exists that threatens the integrity of the accounting data.
  • the error checking on a periodic basis may test not only the physical parameters, such as positions of various mechanical elements, but also may effect the comparison of the data stored in the two memories, as well as performing control sum checks to determine'if the data stored in each memory is in accordance with determined relationships.
  • RAM random access memory

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Detection And Correction Of Errors (AREA)
EP83100639A 1982-01-29 1983-01-25 Dispositif d'affranchissement électronique controllé par un système à microprocesseur Withdrawn EP0085385A3 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP86116058A EP0231452B2 (fr) 1982-01-29 1983-01-25 Systèmes à microprocesseur pour dispositif d'affranchissement électronique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34387782A 1982-01-29 1982-01-29
US343877 1982-01-29

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP86116058A Division EP0231452B2 (fr) 1982-01-29 1983-01-25 Systèmes à microprocesseur pour dispositif d'affranchissement électronique
EP86116058.8 Division-Into 1983-01-25

Publications (2)

Publication Number Publication Date
EP0085385A2 true EP0085385A2 (fr) 1983-08-10
EP0085385A3 EP0085385A3 (fr) 1984-11-14

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Family Applications (3)

Application Number Title Priority Date Filing Date
EP96110413A Revoked EP0736846B1 (fr) 1982-01-29 1983-01-25 Système à microprocesseur pour arrangement d'affranchissement électronique
EP92114140A Expired - Lifetime EP0513880B1 (fr) 1982-01-29 1983-01-25 Systèmes à microprocesseur pour arrangements de machine à affranchir électronique
EP83100639A Withdrawn EP0085385A3 (fr) 1982-01-29 1983-01-25 Dispositif d'affranchissement électronique controllé par un système à microprocesseur

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EP96110413A Revoked EP0736846B1 (fr) 1982-01-29 1983-01-25 Système à microprocesseur pour arrangement d'affranchissement électronique
EP92114140A Expired - Lifetime EP0513880B1 (fr) 1982-01-29 1983-01-25 Systèmes à microprocesseur pour arrangements de machine à affranchir électronique

Country Status (4)

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EP (3) EP0736846B1 (fr)
JP (1) JPH0797417B2 (fr)
CA (1) CA1206619A (fr)
DE (4) DE3382810T2 (fr)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0173249A2 (fr) * 1984-08-22 1986-03-05 Pitney Bowes Inc. Système de mémoire non-volatile avec possibilité d'enregistrement de données de temps réels et de baisse de puissance pour une machine à affranchir électronique
EP0194663A2 (fr) * 1985-03-12 1986-09-17 Pitney Bowes Inc. Machine d'affranchissement avec un circuit protégeant une mémoire non volatile
EP0219118A2 (fr) * 1985-10-15 1987-04-22 Pitney Bowes Inc. Machine à affranchir électronique à double redondance
EP0222197A2 (fr) * 1985-10-16 1987-05-20 Pitney Bowes Inc. Systèmes pour l'emmagasinage non volatil de données et systèmes de machines à affranchir
EP0285955A1 (fr) * 1987-03-31 1988-10-12 Alcatel Satmam Dispositif de couplage de memoires non volatiles dans une machine electronique et machine à affranchir en faisant application
US4805109A (en) * 1985-10-16 1989-02-14 Pitney Bowes Inc. Nonvolatile memory protection arrangement for electronic postage meter system having plural nonvolatile memories
US4817004A (en) * 1985-10-16 1989-03-28 Pitney Bowes Inc. Electronic postage meter operating system
US4845632A (en) * 1985-10-16 1989-07-04 Pitney Bowes Inc. Electonic postage meter system having arrangement for rapid storage of critical postage accounting data in plural nonvolatile memories
WO1989011134A1 (fr) * 1988-05-09 1989-11-16 Ascom Hasler Ag Systeme electronique de calcul et d'enregistrement pour machines d'affranchissement
EP0356052A2 (fr) * 1988-08-18 1990-02-28 Neopost Limited Machine à affranchir
EP0740275A2 (fr) * 1986-09-02 1996-10-30 Pitney Bowes, Inc. Système automatisé de transactions avec tête d'impression modulaire ayant la possibilité d'authentifier une impression
GB2319217A (en) * 1996-11-18 1998-05-20 Neopost Ltd Postage meter and postage indicia printed thereby
US5946671A (en) * 1996-01-26 1999-08-31 Neopost Limited Postage meter

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US5661808A (en) 1995-04-27 1997-08-26 Srs Labs, Inc. Stereo enhancement system
DE59710554D1 (de) 1996-01-31 2003-09-18 Francotyp Postalia Ag Frankiermaschine
US5970152A (en) * 1996-04-30 1999-10-19 Srs Labs, Inc. Audio enhancement system for use in a surround sound environment
US5912976A (en) 1996-11-07 1999-06-15 Srs Labs, Inc. Multi-channel audio enhancement system for use in recording and playback and methods for providing same
DE29913639U1 (de) * 1999-07-30 2000-01-13 Francotyp-Postalia AG & Co., 16547 Birkenwerder Frankier- und Freimachungsmaschine
US7277767B2 (en) 1999-12-10 2007-10-02 Srs Labs, Inc. System and method for enhanced streaming audio
EP2661907B8 (fr) 2011-01-04 2019-08-14 DTS, Inc. Système de rendu audio immersif
WO2013032822A2 (fr) 2011-08-26 2013-03-07 Dts Llc Système de réglage audio

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EP0026734A1 (fr) * 1979-09-28 1981-04-08 Licentia Patent-Verwaltungs-GmbH Dispositif sûr de traitement de données
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GB2079223A (en) * 1980-07-09 1982-01-20 Roneo Alcatel Ltd Postal Franking Meter
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Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0173249A2 (fr) * 1984-08-22 1986-03-05 Pitney Bowes Inc. Système de mémoire non-volatile avec possibilité d'enregistrement de données de temps réels et de baisse de puissance pour une machine à affranchir électronique
EP0173249A3 (en) * 1984-08-22 1987-01-21 Pitney Bowes Inc. Non-volatile memory system with real time and power down data storage capability for an electronic postage meter
EP0194663A2 (fr) * 1985-03-12 1986-09-17 Pitney Bowes Inc. Machine d'affranchissement avec un circuit protégeant une mémoire non volatile
EP0194663A3 (en) * 1985-03-12 1987-04-22 Pitney Bowes Inc. A postage meter with a non-volatile memory security circuit
EP0219118A2 (fr) * 1985-10-15 1987-04-22 Pitney Bowes Inc. Machine à affranchir électronique à double redondance
US5029093A (en) * 1985-10-15 1991-07-02 Pitney Bowes Inc. Dual redundant electronic postage meter
EP0219118A3 (en) * 1985-10-15 1987-09-16 Pitney Bowes Inc. Dual redundant electronic postage meter
US4845632A (en) * 1985-10-16 1989-07-04 Pitney Bowes Inc. Electonic postage meter system having arrangement for rapid storage of critical postage accounting data in plural nonvolatile memories
US4805109A (en) * 1985-10-16 1989-02-14 Pitney Bowes Inc. Nonvolatile memory protection arrangement for electronic postage meter system having plural nonvolatile memories
US4817004A (en) * 1985-10-16 1989-03-28 Pitney Bowes Inc. Electronic postage meter operating system
EP0222197A3 (en) * 1985-10-16 1987-12-16 Pitney Bowes Inc. Systems for non-volatile storage of data and postage meter systems
EP0222197A2 (fr) * 1985-10-16 1987-05-20 Pitney Bowes Inc. Systèmes pour l'emmagasinage non volatil de données et systèmes de machines à affranchir
EP0457114A1 (fr) * 1985-10-16 1991-11-21 Pitney Bowes Inc. Système d'affranchissement pour la mémorisation non-volatile de données
EP0740275A2 (fr) * 1986-09-02 1996-10-30 Pitney Bowes, Inc. Système automatisé de transactions avec tête d'impression modulaire ayant la possibilité d'authentifier une impression
EP0740275B1 (fr) * 1986-09-02 2006-11-15 Pitney Bowes, Inc. Système automatisé de transactions avec tête d'impression modulaire ayant la possibilité d'authentifier une impression
FR2620259A1 (fr) * 1987-03-31 1989-03-10 Smh Alcatel Dispositif de couplage de memoires non volatiles dans une machine electronique et machine a affranchir en faisant application
US4916626A (en) * 1987-03-31 1990-04-10 Societe Anonyme Dite : Smh Alcatel Coupling circuit for non-volatile memories in an electronic machine, and franking machine applying said circuit
EP0285955A1 (fr) * 1987-03-31 1988-10-12 Alcatel Satmam Dispositif de couplage de memoires non volatiles dans une machine electronique et machine à affranchir en faisant application
WO1989011134A1 (fr) * 1988-05-09 1989-11-16 Ascom Hasler Ag Systeme electronique de calcul et d'enregistrement pour machines d'affranchissement
EP0356052A3 (en) * 1988-08-18 1990-08-29 Alcatel Business Systems Limited Franking machine
EP0356052A2 (fr) * 1988-08-18 1990-02-28 Neopost Limited Machine à affranchir
US5946671A (en) * 1996-01-26 1999-08-31 Neopost Limited Postage meter
GB2319217A (en) * 1996-11-18 1998-05-20 Neopost Ltd Postage meter and postage indicia printed thereby
GB2319217B (en) * 1996-11-18 2001-07-25 Neopost Ltd Postage meter and postage indicia printed thereby

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DE85385T1 (de) 1985-12-05
EP0513880A3 (en) 1993-01-13
EP0736846B1 (fr) 2000-10-25
DE3382744D1 (de) 1994-05-19
DE3382744T2 (de) 1994-09-01
DE3382744T3 (de) 2002-09-05
DE3382810T2 (de) 1997-05-22
JPS58144989A (ja) 1983-08-29
JPH0797417B2 (ja) 1995-10-18
DE3382810D1 (de) 1997-02-13
DE3382835D1 (de) 2000-11-30
EP0736846A2 (fr) 1996-10-09
EP0513880A2 (fr) 1992-11-19
EP0085385A3 (fr) 1984-11-14
EP0513880B1 (fr) 1997-01-02
CA1206619A (fr) 1986-06-24
EP0736846A3 (fr) 1996-10-16

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