EP0028490B1 - Integrated circuit with alpha radiation shielding means - Google Patents
Integrated circuit with alpha radiation shielding means Download PDFInfo
- Publication number
- EP0028490B1 EP0028490B1 EP80303803A EP80303803A EP0028490B1 EP 0028490 B1 EP0028490 B1 EP 0028490B1 EP 80303803 A EP80303803 A EP 80303803A EP 80303803 A EP80303803 A EP 80303803A EP 0028490 B1 EP0028490 B1 EP 0028490B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- integrated circuit
- radiation shielding
- shielding means
- alpha radiation
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W42/25—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Definitions
- the present invention relates to integrated circuits and to methods and apparatus for the shielding of integrated circuits from bombardment by ionising radiation.
- An error causing mechanism exists not encountered in the operation of small area integrated circuit memories, having physically large component members, whereby the passage of an alpha particle into the substance of the integrated circuit causes, by the dissipation of its kinetic energy, the generation of sufficient hole-electron pairs to disrupt the integrity of stored data.
- a large area circuit presenting a larger target, has a higher probability of being struck by an alpha particle than does a small one.
- a small memory storage cell requiring only a small number of electrons to be retained for the storage of a binary digit, is more easily disrupted by the sudden injection of alpha generated charge than is a larger cell which requires a large number of electrons for data digit storage.
- Threshold levels have also been changed, so that a higher noise immunity is present.
- the alpha particle problem promises to become increasingly severe as further attempts are made to increase data storage capacity per device.
- the error rates of a few per hour, presently encountered in the 64k bit memories will be increased to one every few seconds, thanks to the enormous relative increase in area.
- the alpha particles responsible for charge induced errors, originate from radioactive decay of foreign inclusions in the material used to fabricate the integrated circuit case.
- the integrated circuit case does indeed protect the integrated circuit from terrestrial and other sources of background radiation, it itself contributes to the problem setting a lower limit on the number of particles colliding with the integrated circuit every hour.
- integrated circuits may be protected from the incidence thereon of alpha particles and which is free from radioactive inclusions.
- the present invention is based on this latter approach, and provides a particularly convenient and satisfactory form of protective coating.
- the invention consists in an integrated circuit fabricated on a silicon surface and protected from the effects of ionising radiation by a coating applied to its upper surface, characterised in that said coating consists of a layer of polycrystalline silicon at least 10 microns thick, said layer being continuously deposited over said integrated circuit so as to sandwich said circuit between itself and said surface and said polycrystalline silicon being substantially free from radio-active inclusions.
- a silicon slice (40) has an integrated circuit (42) fabricated thereon.
- a layer of polycrystalline silicon (44) is deposited over the entire surface of the integrated circuit.
- the polycrystalline silicon layer is at least ten microns thick. It is the same style of layer as is used in the normal course of fabrication of charge storage semiconductor memory integrated circuits.
- the silicon slice (40) is mounted into an integrated circuit enclosure in a completely normal manner, as a last stage of integrated circuit manufacture.
- the polycrystalline silicon layer must meet the electrical insulation criterion for such deposition over an integrated circuit, and must be free from radio-active inclusions and be thick enough to prevent the through-passage of alpha particles with energies up to 10 MeV.
- the integrated circuit (42) is thus protected by a complete shielding, being surrounded by silicon above and below.
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
- The present invention relates to integrated circuits and to methods and apparatus for the shielding of integrated circuits from bombardment by ionising radiation.
- The trend in the design and manufacture of integrated circuits, especially those intended for memory storage of informational data, for use in conjunction with data processing equipment, is towards the creation of larger area circuits having on them an increased number of yet smaller components.
- An error causing mechanism exists not encountered in the operation of small area integrated circuit memories, having physically large component members, whereby the passage of an alpha particle into the substance of the integrated circuit causes, by the dissipation of its kinetic energy, the generation of sufficient hole-electron pairs to disrupt the integrity of stored data. A large area circuit, presenting a larger target, has a higher probability of being struck by an alpha particle than does a small one. Likewise, a small memory storage cell, requiring only a small number of electrons to be retained for the storage of a binary digit, is more easily disrupted by the sudden injection of alpha generated charge than is a larger cell which requires a large number of electrons for data digit storage.
- As cell size decreases, there exists a critical limit, below which an intruding alpha particle is able to disrupt the stored data in several physically adjacent data storage cells. The process of inbuilt error correction, an old art in the design and operation of semiconductor memories, then becomes difficult to achieve and hardware consuming, as it is necessary to correct a plurality of erroneous adjacent bits, requiring long, redundant codes to be added to the stored data. Memory efficiency must suffer if this course is chosen.
- The alpha particle problem has proved particularly troublesome in the development of high capacity, charge storage memories. It has become apparent that a soft error rate must be accepted as integral with the operation such integrated circuits. In order to successfully exploit the capacity of such devices, the usual design process of simply scaling and combining earlier, lower capacity memory device designs has largely been abandoned, memory cells in the high capacity devices having higher charge storage per unit area than their earlier counterparts. This has increased the number of stored electrons per memory cell, and so decreased the likelehood of a charge induced error. Other improvements have been incorporated, such as the employment of more efficient electron collectors for each memory cell, so that a smaller number of residual electrons may be interpreted as the presence of a stored binary digit. Threshold levels have also been changed, so that a higher noise immunity is present. The alpha particle problem promises to become increasingly severe as further attempts are made to increase data storage capacity per device. In particular, as new wafer scale circuits are introduced, where the entire surface of a silicon wafer, several inches in diameter, is used for the fabrication of a single circuit, the error rates of a few per hour, presently encountered in the 64k bit memories, will be increased to one every few seconds, thanks to the enormous relative increase in area.
- It has been shown that the alpha particles, responsible for charge induced errors, originate from radioactive decay of foreign inclusions in the material used to fabricate the integrated circuit case. The few parts per million of radio- active impurities, present in the materials of the case, emit a sufficiency of alpha particles as nuclear decay products, to cause an unacceptably high probability of the collision of an alpha particle with signal bearing or storage elements in the integrated circuit. While the integrated circuit case does indeed protect the integrated circuit from terrestrial and other sources of background radiation, it itself contributes to the problem setting a lower limit on the number of particles colliding with the integrated circuit every hour.
- Accordingly, it is desirable to find means whereby. integrated circuits may be protected from the incidence thereon of alpha particles and which is free from radioactive inclusions.
- It has already been proposed to attack this problem by devising new packaging material processes, or applying protective coatings to the upper surface of the chip. The present invention is based on this latter approach, and provides a particularly convenient and satisfactory form of protective coating.
- The invention consists in an integrated circuit fabricated on a silicon surface and protected from the effects of ionising radiation by a coating applied to its upper surface, characterised in that said coating consists of a layer of polycrystalline silicon at least 10 microns thick, said layer being continuously deposited over said integrated circuit so as to sandwich said circuit between itself and said surface and said polycrystalline silicon being substantially free from radio-active inclusions.
- The single Figure of the accompanying drawings shows an integrated circuit having deposited thereover a continuous layer of semiconducting material.
- As shown in the drawing, a silicon slice (40) has an integrated circuit (42) fabricated thereon. As a final stage of fabrication, a layer of polycrystalline silicon (44) is deposited over the entire surface of the integrated circuit.
- The polycrystalline silicon layer is at least ten microns thick. It is the same style of layer as is used in the normal course of fabrication of charge storage semiconductor memory integrated circuits.
- The silicon slice (40) is mounted into an integrated circuit enclosure in a completely normal manner, as a last stage of integrated circuit manufacture.
- It is to be appreciated that the polycrystalline silicon layer must meet the electrical insulation criterion for such deposition over an integrated circuit, and must be free from radio-active inclusions and be thick enough to prevent the through-passage of alpha particles with energies up to 10 MeV.
- The integrated circuit (42) is thus protected by a complete shielding, being surrounded by silicon above and below.
Claims (1)
- An integrated circuit fabricated on a silicon surface and protected from the effects of ionising radiation by a coating applied to its upper surface, characterised in that said coating consists of a layer of polycrystalline silicon at least 10 microns thick, said layer being continuously deposited over said integrated circuit so as to sandwich said circuit between itself and said surface, and said polycrystalline silicon being substantially free from radio-active inclusions.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7938118 | 1979-11-02 | ||
| GB7938118 | 1979-11-02 | ||
| GB7938119 | 1979-11-02 | ||
| GB7938119 | 1979-11-02 | ||
| GB7938134 | 1979-11-03 | ||
| GB7938134 | 1979-11-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0028490A1 EP0028490A1 (en) | 1981-05-13 |
| EP0028490B1 true EP0028490B1 (en) | 1983-12-21 |
Family
ID=27260792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP80303803A Expired EP0028490B1 (en) | 1979-11-02 | 1980-10-27 | Integrated circuit with alpha radiation shielding means |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0028490B1 (en) |
| DE (1) | DE3065954D1 (en) |
| WO (1) | WO1981001345A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4423548A (en) * | 1981-07-06 | 1984-01-03 | Motorola, Inc. | Method for protecting a semiconductor device from radiation indirect failures |
| US4380566A (en) * | 1981-07-13 | 1983-04-19 | Fairchild Camera & Instrument Corp. | Radiation protection for integrated circuits utilizing tape automated bonding |
| JPS58207657A (en) * | 1982-05-28 | 1983-12-03 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR920001026B1 (en) * | 1984-02-09 | 1992-02-01 | 페어챠일드 카메라 앤드 인스트루먼트 코포레이션 | Semiconductor Structure Having Alpha Particle Protection Film and Manufacturing Method Thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588356A (en) * | 1978-12-27 | 1980-07-04 | Hitachi Ltd | Semiconductor device |
| JPS55163850A (en) * | 1979-06-08 | 1980-12-20 | Fujitsu Ltd | Semiconductor device |
-
1980
- 1980-10-27 WO PCT/GB1980/000180 patent/WO1981001345A1/en not_active Ceased
- 1980-10-27 EP EP80303803A patent/EP0028490B1/en not_active Expired
- 1980-10-27 DE DE8080303803T patent/DE3065954D1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3065954D1 (en) | 1984-01-26 |
| WO1981001345A1 (en) | 1981-05-14 |
| EP0028490A1 (en) | 1981-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4852060A (en) | Soft error resistant data storage cells | |
| Koga et al. | On the suitability of non-hardened high density SRAMs for space applications | |
| US5315544A (en) | Radiation-hardened memory storage device for space applications | |
| Koga et al. | Single-word multiple-bit upsets in static random access devices | |
| US4423548A (en) | Method for protecting a semiconductor device from radiation indirect failures | |
| KR100326221B1 (en) | Semiconductor device | |
| US4481526A (en) | Semiconductor device | |
| US4328610A (en) | Method of reducing alpha-particle induced errors in an integrated circuit | |
| US7629196B1 (en) | Method for manufacturing an integrated circuit having increased radiation hardness and reliability | |
| EP0028490A1 (en) | Integrated circuit with Alpha radiation shielding means | |
| Shindou et al. | Bulk damage caused by single protons in SDRAMs | |
| Fogle et al. | Flash memory under cosmic and alpha irradiation | |
| Baumann | Impact of single-event upsets in deep-submicron silicon technology | |
| US8946874B2 (en) | IC in-process solution to reduce thermal neutrons soft error rate | |
| Browning et al. | Single event upset rate estimates for a 16-K CMOS SRAM | |
| Irom et al. | Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies | |
| AU2023238217A1 (en) | Systems and methods for reducing effect of noise on solid state quantum processors | |
| Gadlage et al. | Low-energy electron irradiation of NAND flash memories | |
| Gerardin et al. | Scaling trends of neutron effects in MLC NAND flash memories | |
| Stassinopoulos et al. | Radiation-induced anomalies in satellites | |
| Han et al. | Asymmetric ECC organization in 3D-memory via spare column utilization | |
| Bozhko et al. | a Study of Improvement of a Technology for Obtaining Radiation-Protecting Materials for Spacecraft and Rocketry Systems | |
| Tang | Nuclear processes and soft fails in microelectronics | |
| Anolick et al. | The characteristics of alpha particle effects on 64K CCD's | |
| Claeys et al. | Radiation environments and component selection strategy |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Designated state(s): BE DE FR GB IT LU NL |
|
| 17P | Request for examination filed |
Effective date: 19810311 |
|
| ITF | It: translation for a ep patent filed | ||
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Designated state(s): BE DE FR GB IT LU NL |
|
| REF | Corresponds to: |
Ref document number: 3065954 Country of ref document: DE Date of ref document: 19840126 |
|
| ET | Fr: translation filed | ||
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| 26N | No opposition filed | ||
| ITPR | It: changes in ownership of a european patent |
Owner name: FUSIONI;BURROUGHS DELAWARE INCORPORATED ( DETROIT |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732 |
|
| NLS | Nl: assignments of ep-patents |
Owner name: BURROUGHS CORPORATION TE DETROIT, MICHIGAN, VER. S |
|
| ITTA | It: last paid annual fee | ||
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: BE Payment date: 19911113 Year of fee payment: 12 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 19921027 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Effective date: 19921031 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: LU Payment date: 19921231 Year of fee payment: 12 |
|
| EPTA | Lu: last paid annual fee | ||
| BERE | Be: lapsed |
Owner name: BURROUGHS CORP. Effective date: 19921031 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 19931031 Year of fee payment: 14 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Effective date: 19950501 |
|
| NLV4 | Nl: lapsed or anulled due to non-payment of the annual fee | ||
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 19950918 Year of fee payment: 16 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 19951020 Year of fee payment: 16 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 19951027 Year of fee payment: 16 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Effective date: 19961027 |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 19961027 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Effective date: 19970630 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Effective date: 19970701 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 19911031 |