EP0028490B1 - Integrated circuit with alpha radiation shielding means - Google Patents

Integrated circuit with alpha radiation shielding means Download PDF

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Publication number
EP0028490B1
EP0028490B1 EP80303803A EP80303803A EP0028490B1 EP 0028490 B1 EP0028490 B1 EP 0028490B1 EP 80303803 A EP80303803 A EP 80303803A EP 80303803 A EP80303803 A EP 80303803A EP 0028490 B1 EP0028490 B1 EP 0028490B1
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
radiation shielding
shielding means
alpha radiation
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP80303803A
Other languages
German (de)
French (fr)
Other versions
EP0028490A1 (en
Inventor
John Malcolm Wilkinson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of EP0028490A1 publication Critical patent/EP0028490A1/en
Application granted granted Critical
Publication of EP0028490B1 publication Critical patent/EP0028490B1/en
Expired legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/20Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/25Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to integrated circuits and to methods and apparatus for the shielding of integrated circuits from bombardment by ionising radiation.
  • An error causing mechanism exists not encountered in the operation of small area integrated circuit memories, having physically large component members, whereby the passage of an alpha particle into the substance of the integrated circuit causes, by the dissipation of its kinetic energy, the generation of sufficient hole-electron pairs to disrupt the integrity of stored data.
  • a large area circuit presenting a larger target, has a higher probability of being struck by an alpha particle than does a small one.
  • a small memory storage cell requiring only a small number of electrons to be retained for the storage of a binary digit, is more easily disrupted by the sudden injection of alpha generated charge than is a larger cell which requires a large number of electrons for data digit storage.
  • Threshold levels have also been changed, so that a higher noise immunity is present.
  • the alpha particle problem promises to become increasingly severe as further attempts are made to increase data storage capacity per device.
  • the error rates of a few per hour, presently encountered in the 64k bit memories will be increased to one every few seconds, thanks to the enormous relative increase in area.
  • the alpha particles responsible for charge induced errors, originate from radioactive decay of foreign inclusions in the material used to fabricate the integrated circuit case.
  • the integrated circuit case does indeed protect the integrated circuit from terrestrial and other sources of background radiation, it itself contributes to the problem setting a lower limit on the number of particles colliding with the integrated circuit every hour.
  • integrated circuits may be protected from the incidence thereon of alpha particles and which is free from radioactive inclusions.
  • the present invention is based on this latter approach, and provides a particularly convenient and satisfactory form of protective coating.
  • the invention consists in an integrated circuit fabricated on a silicon surface and protected from the effects of ionising radiation by a coating applied to its upper surface, characterised in that said coating consists of a layer of polycrystalline silicon at least 10 microns thick, said layer being continuously deposited over said integrated circuit so as to sandwich said circuit between itself and said surface and said polycrystalline silicon being substantially free from radio-active inclusions.
  • a silicon slice (40) has an integrated circuit (42) fabricated thereon.
  • a layer of polycrystalline silicon (44) is deposited over the entire surface of the integrated circuit.
  • the polycrystalline silicon layer is at least ten microns thick. It is the same style of layer as is used in the normal course of fabrication of charge storage semiconductor memory integrated circuits.
  • the silicon slice (40) is mounted into an integrated circuit enclosure in a completely normal manner, as a last stage of integrated circuit manufacture.
  • the polycrystalline silicon layer must meet the electrical insulation criterion for such deposition over an integrated circuit, and must be free from radio-active inclusions and be thick enough to prevent the through-passage of alpha particles with energies up to 10 MeV.
  • the integrated circuit (42) is thus protected by a complete shielding, being surrounded by silicon above and below.

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

    Background to the invention 1. Field of the invention
  • The present invention relates to integrated circuits and to methods and apparatus for the shielding of integrated circuits from bombardment by ionising radiation.
  • 2. The prior art
  • The trend in the design and manufacture of integrated circuits, especially those intended for memory storage of informational data, for use in conjunction with data processing equipment, is towards the creation of larger area circuits having on them an increased number of yet smaller components.
  • An error causing mechanism exists not encountered in the operation of small area integrated circuit memories, having physically large component members, whereby the passage of an alpha particle into the substance of the integrated circuit causes, by the dissipation of its kinetic energy, the generation of sufficient hole-electron pairs to disrupt the integrity of stored data. A large area circuit, presenting a larger target, has a higher probability of being struck by an alpha particle than does a small one. Likewise, a small memory storage cell, requiring only a small number of electrons to be retained for the storage of a binary digit, is more easily disrupted by the sudden injection of alpha generated charge than is a larger cell which requires a large number of electrons for data digit storage.
  • As cell size decreases, there exists a critical limit, below which an intruding alpha particle is able to disrupt the stored data in several physically adjacent data storage cells. The process of inbuilt error correction, an old art in the design and operation of semiconductor memories, then becomes difficult to achieve and hardware consuming, as it is necessary to correct a plurality of erroneous adjacent bits, requiring long, redundant codes to be added to the stored data. Memory efficiency must suffer if this course is chosen.
  • The alpha particle problem has proved particularly troublesome in the development of high capacity, charge storage memories. It has become apparent that a soft error rate must be accepted as integral with the operation such integrated circuits. In order to successfully exploit the capacity of such devices, the usual design process of simply scaling and combining earlier, lower capacity memory device designs has largely been abandoned, memory cells in the high capacity devices having higher charge storage per unit area than their earlier counterparts. This has increased the number of stored electrons per memory cell, and so decreased the likelehood of a charge induced error. Other improvements have been incorporated, such as the employment of more efficient electron collectors for each memory cell, so that a smaller number of residual electrons may be interpreted as the presence of a stored binary digit. Threshold levels have also been changed, so that a higher noise immunity is present. The alpha particle problem promises to become increasingly severe as further attempts are made to increase data storage capacity per device. In particular, as new wafer scale circuits are introduced, where the entire surface of a silicon wafer, several inches in diameter, is used for the fabrication of a single circuit, the error rates of a few per hour, presently encountered in the 64k bit memories, will be increased to one every few seconds, thanks to the enormous relative increase in area.
  • It has been shown that the alpha particles, responsible for charge induced errors, originate from radioactive decay of foreign inclusions in the material used to fabricate the integrated circuit case. The few parts per million of radio- active impurities, present in the materials of the case, emit a sufficiency of alpha particles as nuclear decay products, to cause an unacceptably high probability of the collision of an alpha particle with signal bearing or storage elements in the integrated circuit. While the integrated circuit case does indeed protect the integrated circuit from terrestrial and other sources of background radiation, it itself contributes to the problem setting a lower limit on the number of particles colliding with the integrated circuit every hour.
  • Accordingly, it is desirable to find means whereby. integrated circuits may be protected from the incidence thereon of alpha particles and which is free from radioactive inclusions.
  • It has already been proposed to attack this problem by devising new packaging material processes, or applying protective coatings to the upper surface of the chip. The present invention is based on this latter approach, and provides a particularly convenient and satisfactory form of protective coating.
  • The invention consists in an integrated circuit fabricated on a silicon surface and protected from the effects of ionising radiation by a coating applied to its upper surface, characterised in that said coating consists of a layer of polycrystalline silicon at least 10 microns thick, said layer being continuously deposited over said integrated circuit so as to sandwich said circuit between itself and said surface and said polycrystalline silicon being substantially free from radio-active inclusions.
  • The single Figure of the accompanying drawings shows an integrated circuit having deposited thereover a continuous layer of semiconducting material.
  • As shown in the drawing, a silicon slice (40) has an integrated circuit (42) fabricated thereon. As a final stage of fabrication, a layer of polycrystalline silicon (44) is deposited over the entire surface of the integrated circuit.
  • The polycrystalline silicon layer is at least ten microns thick. It is the same style of layer as is used in the normal course of fabrication of charge storage semiconductor memory integrated circuits.
  • The silicon slice (40) is mounted into an integrated circuit enclosure in a completely normal manner, as a last stage of integrated circuit manufacture.
  • It is to be appreciated that the polycrystalline silicon layer must meet the electrical insulation criterion for such deposition over an integrated circuit, and must be free from radio-active inclusions and be thick enough to prevent the through-passage of alpha particles with energies up to 10 MeV.
  • The integrated circuit (42) is thus protected by a complete shielding, being surrounded by silicon above and below.

Claims (1)

  1. An integrated circuit fabricated on a silicon surface and protected from the effects of ionising radiation by a coating applied to its upper surface, characterised in that said coating consists of a layer of polycrystalline silicon at least 10 microns thick, said layer being continuously deposited over said integrated circuit so as to sandwich said circuit between itself and said surface, and said polycrystalline silicon being substantially free from radio-active inclusions.
EP80303803A 1979-11-02 1980-10-27 Integrated circuit with alpha radiation shielding means Expired EP0028490B1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB7938118 1979-11-02
GB7938118 1979-11-02
GB7938119 1979-11-02
GB7938119 1979-11-02
GB7938134 1979-11-03
GB7938134 1979-11-03

Publications (2)

Publication Number Publication Date
EP0028490A1 EP0028490A1 (en) 1981-05-13
EP0028490B1 true EP0028490B1 (en) 1983-12-21

Family

ID=27260792

Family Applications (1)

Application Number Title Priority Date Filing Date
EP80303803A Expired EP0028490B1 (en) 1979-11-02 1980-10-27 Integrated circuit with alpha radiation shielding means

Country Status (3)

Country Link
EP (1) EP0028490B1 (en)
DE (1) DE3065954D1 (en)
WO (1) WO1981001345A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4423548A (en) * 1981-07-06 1984-01-03 Motorola, Inc. Method for protecting a semiconductor device from radiation indirect failures
US4380566A (en) * 1981-07-13 1983-04-19 Fairchild Camera & Instrument Corp. Radiation protection for integrated circuits utilizing tape automated bonding
JPS58207657A (en) * 1982-05-28 1983-12-03 Fujitsu Ltd Manufacture of semiconductor device
KR920001026B1 (en) * 1984-02-09 1992-02-01 페어챠일드 카메라 앤드 인스트루먼트 코포레이션 Semiconductor Structure Having Alpha Particle Protection Film and Manufacturing Method Thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5588356A (en) * 1978-12-27 1980-07-04 Hitachi Ltd Semiconductor device
JPS55163850A (en) * 1979-06-08 1980-12-20 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date
DE3065954D1 (en) 1984-01-26
WO1981001345A1 (en) 1981-05-14
EP0028490A1 (en) 1981-05-13

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