EP0000317B1 - Verfahren zum Herstellen einer Silicid-Elektrode auf einem Substrat besonders auf einem Halbleitersubstrat - Google Patents

Verfahren zum Herstellen einer Silicid-Elektrode auf einem Substrat besonders auf einem Halbleitersubstrat Download PDF

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Publication number
EP0000317B1
EP0000317B1 EP78430003A EP78430003A EP0000317B1 EP 0000317 B1 EP0000317 B1 EP 0000317B1 EP 78430003 A EP78430003 A EP 78430003A EP 78430003 A EP78430003 A EP 78430003A EP 0000317 B1 EP0000317 B1 EP 0000317B1
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Prior art keywords
silicon
silicide
substrate
metal
layer
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Expired
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EP78430003A
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English (en)
French (fr)
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EP0000317A1 (de
Inventor
Billy Lee Crowder
Stanley Zirinsky
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/14—Schottky barrier contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Definitions

  • the present invention relates to a method for manufacturing a silicide electrode on a substrate making it possible to deposit a silicide such as a molybdenum, tantalum, rhodium or tungsten silicide on the substrate, and in particular on a semiconductor substrate constituted by doped silicon or by doped polycrystalline silicon.
  • a silicide such as a molybdenum, tantalum, rhodium or tungsten silicide
  • Polycrystalline silicon has been widely used for several years as an interconnection material in integrated circuits. The use of this type of silicon is desirable because it is very stable at high temperature and lends itself to chemical vapor deposition of silicon dioxide, or to its thermal growth. Polycrystalline silicon interconnections have been used in various types of integrated circuits, notably in sets of charge coupled devices, in logic sets and in sets of memory cells with a single field effect device.
  • polycrystalline silicon has the drawback of offering a relatively high electrical resistance.
  • the attempts which have been made so far to improve the performance of certain integrated circuits by reducing the dimensions of the devices have not been successful since the voltage drops which produce in the interconnections do not decrease when one decreases the voltage levels required for the operation of the circuits. It would therefore be desirable to reduce the layer (or sheet) resistance of the polycrystalline silicon interconnections in order to increase the speed of the circuit.
  • hafnium silicide obtained by depositing hafnium on polycrystalline silicon, then by heating the assembly to react the hafnium and the polycrystalline silicon.
  • the same article also suggests the use for this purpose of tantalum, tungsten or molybdenum silicides; the strips can then be covered with chemically deposited oxide in the vapor phase.
  • the spraying techniques proposed have a certain number of drawbacks. In particular, it is difficult to vary the composition of silicide precisely. On the other hand, when using spraying techniques, it is necessary to carry out a pickling to remove the metal from certain regions where no silicide should be formed.
  • One of the objects of the present invention is therefore to provide a process making it possible to produce silicides of certain refractory metals which makes it possible to control and vary precisely the composition of the silicide thus produced.
  • Another object of the invention is to provide a method making it possible to remove the silicide from certain desired parts of the substrate using simple pickling techniques using the use of a solvent, without there being any need to use more complex pickling techniques that require masking.
  • the present invention makes it possible to form a layer of a silicide on a substrate, the metal used being able to be molybdenum, tantalum, tungsten, rhodium or combinations of these materials.
  • the metal silicide is obtained by depositing, by simultaneous evaporation, the silicon and one of said metals on the desired substrate, then subjecting the assembly to a heat treatment.
  • silicon dioxide can be obtained from the silicide layer by thermal oxidation of the latter at high temperature.
  • silicides in the mass that is to say in the volume, does not allow us to assume that it would be possible by thermal oxidation of the oxide layers of sufficient thickness to be able be used in integrated circuits.
  • molybdenum silicide and tungsten silicide when they constitute a mass or a volume are known for their excellent resistance to oxidation.
  • the process of the present invention can be used to form films of the desired silicide on any substrate capable of withstanding the high temperatures used during the deposition process by simultaneous evaporation and sufficiently adherent to said silicide.
  • the present method can be advantageously used for the purposes of producing integrated circuits and, therefore, is of particular interest when the substrate is made of silicon or of polycrystalline silicon.
  • the present process lends itself particularly well to the production of layers intended to cover door electrodes made of doped polycrystalline silicon, to the replacement of polycrystalline silicon as the material constituting such electrodes, and finally to the formation of covering layers. directly broadcast bands in doped silicon.
  • the metal silicides to which the present invention is addressed are molybdenum silicide and / or tantalum silicide and / or tungsten silicide and / or rhodium silicide.
  • the preferred metals for constituting these silicides include molybdenum, tantalum and tungsten, and more particularly the latter.
  • metallic silicides comprise approximately 60 to 25% by atomic weight of the metal.
  • the metal and the silicon are vaporized under a high vacuum and deposited simultaneously on the substrate.
  • the vacuum employed is of the order of 10- 5 to 10- 7 torr.
  • the metal and the silicon are heated under a high vacuum and brought to a temperature sufficient to cause them to evaporate.
  • An electron beam evaporator is preferably used for this purpose and an electron beam gun is preferably used for silicon and another gun for metal due to the fact that the evaporation of these materials occurs at speeds different.
  • the use of said evaporator requires the use, as a heat source, of heat which is dissipated when a highly collimated electron beam strikes the material.
  • the evaporation of the metal and of the silicon should take place at the rate of approximately 25 to 50 Angstroms per second.
  • the substrate which it is desired to cover is generally maintained at a temperature of between ambient temperature and approximately 400 ° C., and preferably between 150 ° C. and approximately 250 ° C. during the deposition of the metal and the silicon.
  • the latter is removed from the apparatus used for the purposes of evaporation under vacuum, then heated in an inert atmosphere at temperatures varying between 700 ° C. and about 1100 ° C and preferably between 900 ° C and 1100 ° C.
  • the maximum suitable temperature is mainly a function of practical considerations and, in particular, is chosen so as to avoid excessive formation of grains in the silicide layer.
  • Suitable inert atmospheres in which the heat treatment can be carried out include argon, helium and hydrogen.
  • the inert atmosphere must not contain water vapor, oxygen, carbon compounds, nitrogen or other substances which could cause the formation of carbide, oxide or nitride during treatment thermal.
  • the substrate is heated to the above temperatures for a period of time sufficient to cause a reaction of the metal and the silicon deposited thereon so as to form the desired silicide.
  • This time interval generally varies between 15 minutes and 2 hours approximately, and it is inversely dependent on the temperature used.
  • the substrate covered with the silicide layer may optionally be subject to oxidation so as to cover said layer of self-passivation oxide. It was found that the decrease in the conductivity of the silicide layer which resulted from the oxidation was much less than that which theoretically should have resulted from the oxidation of a determined part of the layer. For example, an oxidation of 50% of the layer does not cause a corresponding reduction of 50% in its conductivity. This result would be due to a preferential oxidation of the silicon contained in the silicide layer and to a backscattering of the metal, thereby causing the formation of a metal-enriched silicide layer below the oxidized layer.
  • FIGS. 3B and 4B show the variations in the resistivity of certain oxidized silicides according to the temperatures.
  • the overall results indicate that an improvement of about 30% in the conductivity is obtained compared to the theoretical conductivity corresponding to the oxidized percentage of the layer.
  • the oxidation of molybdenum silicide at 1000 ° C for more than 15 minutes had a detrimental effect on the layer and modified its properties. Such conditions should therefore be avoided in the case of molybdenum silicide so that its conductivity remains high.
  • the oxidation was carried out in the vapor phase under the conditions specified.
  • the preferred oxidation process is wet oxidation (water vapor) or dry-wet-dry oxidation. This process makes it possible to obtain better results in terms of breakdown than the other techniques. Oxidation in the vapor phase should preferably be carried out at temperatures varying between 800 ° C and 1100 ° C approximately at a pressure corresponding soon after to atmospheric pressure. The duration of the oxidation depends on the thickness of the oxide layer which it is desired to obtain and generally varies between 15 minutes and 2 hours approximately. For example, obtaining a thickness close to or greater than 1000 Angstroms requires more than 2 hours at approximately 800 ° C. and approximately 30 minutes at approximately 950 ° C.
  • Figures 3A and 4A show the growth of the insulating oxide on the silicide during exposure to steam at temperatures and during the indicated time intervals.
  • Table 1 in the appendix indicates the measured values of the resistance of silicide film produced in accordance with the present invention by evaporation by means of an electron beam.
  • the films deposited on the silicon substrate were about 0.5 micron thick.
  • Table II in the appendix shows the improved conductivity of the silicide produced in accordance with the method of the present invention compared to that of doped silicon. This improved conductivity plays an important role in increasing the speed of transmission of signals on a transmission line.
  • Table 111 in the appendix shows that the use of metallic silicide produced in accordance with the present invention gives results at least as satisfactory as those obtained with polycrystalline silicon, taking into account the flat strip tension and the electrical breakdown voltage in the case where the oxide covers the silicide.
  • Flat band voltage is one of the parameters that are directly related to the gate control voltage needed to drive the field effect transistor (FET) and its specification limited to a narrow range is an important factor in operation FET transistors used in integrated circuits.
  • the average breakdown field in the case of an auto-oxidized silicide with a thickness of approximately 3000 Angstroms disposed between an aluminum conductor and the layer of silicide was greater than 2 to 3 mV / cm.
  • FIGS. 1A and 1B show one of the ways in which the present invention can be used in integrated circuits (for example for the purposes of forming a composite door made of polycrystalline silicon and of metal silicide).
  • the substrate is p-type silicon and that the diffused or implanted impurities are of n-type, which leads to obtaining an FET (Transistor with effect of field) to channel n.
  • FET Transistor with effect of field
  • the present invention can also be applied to a substrate made of a material other than silicon.
  • the expressions “metallic type interconnection strip and” high conductivity interconnection strip used below relate to strips of a metal such as aluminum as well as to non-metallic materials which may nevertheless have a comparable conductivity.
  • references made below to impurities of a "first type and a" second type mean, for example, that if the "first type is p, the second" second type is n, and vice versa.
  • FIGS. 1A and 1B show part of a p-type silicon substrate 1 having a desired crystal orientation (for example ⁇ 100 "and produced by cutting and polishing a p-type silicon ball or bar (that is to say in the presence of a p-type dopant such as boron) according to conventional techniques
  • a desired crystal orientation for example ⁇ 100 "and produced by cutting and polishing a p-type silicon ball or bar (that is to say in the presence of a p-type dopant such as boron
  • Other p-type dopants which can be used with silicon are aluminum, gallium and indium.
  • a door insulator consisting of a thin layer of silicon dioxide 2 is then grown or deposited. This layer, the thickness of which is generally between 200 and 1000 Angstroms, is preferably formed by thermal oxidation of the surface. silicon at 1000 ° C in the presence of dry oxygen.
  • a layer of polycrystalline silicon 3 is deposited.
  • This layer generally has a thickness varying between approximately 500 and 2,000 Angstroms and can be produced by chemical vapor deposition. It is then doped by chemical vapor deposition.
  • This layer is then doped with. using an n-type dopant such as arsenic, phosphorus or antimony, using a conventional technique.
  • this layer can be doped with phosphorus using the technique which consists of depositing a layer of POCl 3 and heating it to approximately 1000 ° C. so as to introduce the phosphorus into layer 3, which then becomes of the type not.
  • the residue is then removed from the layer of PQCI 3 by pickling the pellet in buffered hydrofluoric acid.
  • a silicide layer 4 with a thickness of about 2,000 to 4,000 Angstroms is then formed on the layer 3 using the method of the present invention and described above.
  • a door configuration can be carried out using any known technique for lithography, for example chemical pickling, pickling in a plasma, pickling with reactive ions, etc.
  • the techniques which can be used for this purpose vary in their details, but all make it possible to obtain a composite layer, silicide / polycrystalline silicon, having a determined configuration.
  • chemical pickling it has been found that hot H 3 P0 4 made it possible to selectively pickle silicides with respect to polycrystalline silicon or to Si0 2 .
  • the silicides should preferably be pickled using a so-called “dry technique such as the pickling technique using reactive ions using a material such as CF 4 .
  • n-type source and drain regions are then formed using well-known ion implantation or diffusion techniques.
  • source and drain regions 7 and 8 of type n, respectively, of a depth of 2000 Angstroms can be produced by implantation of As 75 using an energy of approximately 100 KeV and a dose of 4 x 10 15 atoms / cm 2 .
  • the polycrystalline silicon layer 3 and the silicide layer 4 act as a mask and prevent n-type impurities from entering the region of the FET channel which is below layer 3.
  • the boundaries between the n-type source and drain regions and therefore the FET channel are determined by the dimensions of the polycrystalline silicon gate. This technique is generally called “self-aligned door” technique.
  • a self-formed passivation silicon dioxide layer 5 is then formed in situ on the door regions using the oxidation techniques previously described.
  • the assembly is subjected to a vapor phase oxidation at approximately 950 ° C. for approximately 30 minutes to obtain an oxide thickness also greater than 1,000 and 3,000 Angstroms, which depends well on the metal chosen as we saw it above.
  • a layer of silicon dioxide 6 with a thickness of approximately 1000 to 1500 Angstroms to prevent any interaction between the layer of silicide and a metallic interconnection, for example, aluminum, which would later be applied.
  • the oxide layers and the metallic layers are defined using conventional masking and pickling techniques.
  • silicon dioxide can be removed using buffered hydrofluoric acid and aluminum can be stripped using a mixture of phosphoric acid and nitric acid.
  • Aluminum can be deposited by spraying or by evaporation. The structure finally obtained is shown in Figure 1 B.
  • FIGS. 2A to 2C illustrate another use of the present invention for the purpose of manufacturing integrated circuits.
  • the following technique is particularly advantageous because it offers the possibility of removing the deposited silicide from predetermined regions of the substrate, using lift-off techniques.
  • the substrate 11 is covered with a layer of a material 13 which makes it possible to obtain a suitable configuration for the separation step.
  • the material constituting the layer 13 is a resistant material sensitive to radiation in which the desired configuration is generated by conventional techniques (for example by means of a PMMA type resist electron with a masking device. electron beam).
  • the layer 13 could consist of several layers of sensitive materials, so as to obtain the desired separation geometry in the case of materials only capable of withstanding moderately high treatment temperatures.
  • the substrate is doped in the regions which are not protected by the mask so as to form n-type regions 12, for example source and drain regions of a FET.
  • Techniques such as ion implantation of As, P or Sb can be used for the purpose of doping this region.
  • a layer 14 of metal and silicon is deposited on the substrate by means of the simultaneous evaporation step previously described.
  • the layer 14 is not continuous, that is to say that there are no connections between the regions which are above the mask and those which are not, as would occur in the case of the use of a spraying technique, because the latter would cause an overlap of the edges which could cause such a connection or interconnection.
  • the material constituting the mask and that which covers it can therefore be easily removed by means of a simple release technique using a solvent such as acetone which removes the resistant material which remained to form said mask.
  • the assembly is then subjected to a heat treatment at temperatures varying between 700 and 1100 ° C. in an inert atmosphere such as argon, hydrogen or helium, as required by the present invention , to form the silicide.
  • the silicide layer 14 can then be oxidized so as to be covered with a passivation oxide layer.
  • a composite mask 15 such as a layer of silicon nitride deposited on top of a layer of silicon dioxide, is disposed above the channel region of the FET device, in order to serve as a mask preventing or blocking any oxidation substrate at this location.
  • Doping impurities 16 such as boron atoms can be introduced using ion implantation techniques into the field regions.
  • a layer 17 of silicon dioxide is then grown, for example, by chemical vapor deposition, on the parts of the substrate which are not protected by the mask 15.
  • the composite oxidation blocking mask is then removed using an appropriate solvent. If, for example, silicon nitride is used, it can be pickled in a phosphoric acid solution at 180 ° C. The silicon dioxide can be pickled in a buffered hydrofluoric acid solution.
  • a silicon dioxide door insulator 18 is then grown on the substrate.
  • the doping of the channel region, if necessary, is carried out by ion implantation.
  • the material constituting the door is deposited, then its delimitation according to a desired configuration by means of known techniques of masking and pickling. This material can be obtained by simultaneous evaporation and heating of silicon and metal, by deposition of polycrystalline silicon alone, or by deposition of polycrystalline silicon and a layer formed by simultaneous evaporation and heating of silicon and metal in accordance with the techniques of present invention.

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Claims (7)

1. Verfahren zum Herstellen einer Silicidelektrode auf einem Substrat, bei dem ein feuerfestes Metall und Silicium auf dem Substrat abgeschieden werden, dadurch gekennzeichnet, daß es folgende Verfahrensschritte umfaßt :
gleichzeitiges Aufdampfen von Metall und Silicium aus getrennten Quellen im Hochvakuum, wobei dieselben auf eine genügend hohe Temperatur erhitzt werden, um das Verdampfen zu bewirken, und
eine zum Erhalt des Silicids geeignete Wärmebehandlung.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß zum gleichzeitigen Aufdampfen als Wärmequelle für die Verdampfung des Silicids ein Elektronenstrahl und für die Verdampfung des Metalls ein weiterer Elektronenstrahl benutzt wird.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Wärmebehandlung des Substrats, um dieses auf eine Temperatur zwischen etwa 700 °C und 1 100 °C zu erhitzen, in einer inerten Atmosphäre aus der Gruppe von Wasserstoff, Argon, Helium und Mischungen dieser Gase vorgenommen wird.
4. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß das Substrat aus der Gruppe von einkristallinem und polykristallinem Silicium gewählt wird.
5. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß das feuerfeste Metall aus der Gruppe von Molybdän, Tantal, Wolfram, Rhodium und aus Mischungen dieser Metalle gewählt wird.
6. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß das Silicid ungefähr 60 bis 25 Atom-Gew.% dieses Metalls bzw. 40 bis 75 Atom-Gew.% Silicium enthält.
7. Verfahren nach Anspruch 6, dadurch gekennzeichnet, daß es außerdem die Oxidation eines Teils der Silicidschicht umfaßt, die nach der Trocken-Naß-Trockentechnik bei einer Temperatur zwischen ungefähr 800 °C und 1 100 °C während einer Zeitspanne von ungefähr 15 Minuten bis zu 1 Stunde durchgeführt wird.
EP78430003A 1977-06-30 1978-06-22 Verfahren zum Herstellen einer Silicid-Elektrode auf einem Substrat besonders auf einem Halbleitersubstrat Expired EP0000317B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US811914 1977-06-30
US05/811,914 US4180596A (en) 1977-06-30 1977-06-30 Method for providing a metal silicide layer on a substrate

Publications (2)

Publication Number Publication Date
EP0000317A1 EP0000317A1 (de) 1979-01-10
EP0000317B1 true EP0000317B1 (de) 1982-05-19

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EP78430003A Expired EP0000317B1 (de) 1977-06-30 1978-06-22 Verfahren zum Herstellen einer Silicid-Elektrode auf einem Substrat besonders auf einem Halbleitersubstrat

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US (1) US4180596A (de)
EP (1) EP0000317B1 (de)
JP (1) JPS5852342B2 (de)
CA (1) CA1100648A (de)
DE (1) DE2861841D1 (de)
IT (1) IT1112638B (de)

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US4332839A (en) * 1978-12-29 1982-06-01 Bell Telephone Laboratories, Incorporated Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide
USRE32207E (en) * 1978-12-29 1986-07-15 At&T Bell Laboratories Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide
US4364166A (en) * 1979-03-01 1982-12-21 International Business Machines Corporation Semiconductor integrated circuit interconnections
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
NL8002609A (nl) * 1979-06-11 1980-12-15 Gen Electric Samengestelde geleidende structuur en werkwijze voor het vervaardigen daarvan.
FR2459551A1 (fr) * 1979-06-19 1981-01-09 Thomson Csf Procede et structure de passivation a autoalignement sur l'emplacement d'un masque
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
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US4180596A (en) 1979-12-25
JPS5852342B2 (ja) 1983-11-22
DE2861841D1 (en) 1982-07-08
IT7824502A0 (it) 1978-06-13
JPS5413283A (en) 1979-01-31
EP0000317A1 (de) 1979-01-10
IT1112638B (it) 1986-01-20
CA1100648A (en) 1981-05-05

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