DE69819347D1 - Bootstrap prozessorauswahl in einem multiprozessorsystem - Google Patents

Bootstrap prozessorauswahl in einem multiprozessorsystem

Info

Publication number
DE69819347D1
DE69819347D1 DE69819347T DE69819347T DE69819347D1 DE 69819347 D1 DE69819347 D1 DE 69819347D1 DE 69819347 T DE69819347 T DE 69819347T DE 69819347 T DE69819347 T DE 69819347T DE 69819347 D1 DE69819347 D1 DE 69819347D1
Authority
DE
Germany
Prior art keywords
multiprocessor system
processor selection
bootstrap processor
bootstrap
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69819347T
Other languages
English (en)
Other versions
DE69819347T2 (de
Inventor
Muthurajan Jayakumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE69819347D1 publication Critical patent/DE69819347D1/de
Application granted granted Critical
Publication of DE69819347T2 publication Critical patent/DE69819347T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177Initialisation or configuration control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4405Initialisation of multiprocessor systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Multi Processors (AREA)
DE69819347T 1997-07-31 1998-07-28 Bootstrap prozessorauswahl in einem multiprozessorsystem Expired - Fee Related DE69819347T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US904109 1997-07-31
US08/904,109 US5904733A (en) 1997-07-31 1997-07-31 Bootstrap processor selection architecture in SMP systems
PCT/US1998/015537 WO1999006908A1 (en) 1997-07-31 1998-07-28 Bootstrap processor architecture selection in a multiprocessor system

Publications (2)

Publication Number Publication Date
DE69819347D1 true DE69819347D1 (de) 2003-12-04
DE69819347T2 DE69819347T2 (de) 2004-07-22

Family

ID=25418572

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69819347T Expired - Fee Related DE69819347T2 (de) 1997-07-31 1998-07-28 Bootstrap prozessorauswahl in einem multiprozessorsystem

Country Status (5)

Country Link
US (2) US5904733A (de)
EP (1) EP1010062B1 (de)
AU (1) AU8594498A (de)
DE (1) DE69819347T2 (de)
WO (1) WO1999006908A1 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904733A (en) * 1997-07-31 1999-05-18 Intel Corporation Bootstrap processor selection architecture in SMP systems
US6122677A (en) * 1998-03-20 2000-09-19 Micron Technology, Inc. Method of shortening boot uptime in a computer system
US6158000A (en) * 1998-09-18 2000-12-05 Compaq Computer Corporation Shared memory initialization method for system having multiple processor capability
US6336185B1 (en) * 1998-09-24 2002-01-01 Phoenix Technologies Ltd. Use of other processors during BIOS boot sequence to minimize boot time
US7774469B2 (en) 1999-03-26 2010-08-10 Massa Michael T Consistent cluster operational data in a server cluster using a quorum of replicas
US6401120B1 (en) * 1999-03-26 2002-06-04 Microsoft Corporation Method and system for consistent cluster operational data in a server cluster using a quorum of replicas
US6453426B1 (en) * 1999-03-26 2002-09-17 Microsoft Corporation Separately storing core boot data and cluster configuration data in a server cluster
US6601165B2 (en) * 1999-03-26 2003-07-29 Hewlett-Packard Company Apparatus and method for implementing fault resilient booting in a multi-processor system by using a flush command to control resetting of the processors and isolating failed processors
US6594756B1 (en) * 1999-09-08 2003-07-15 Intel Corporation Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor
US6662219B1 (en) 1999-12-15 2003-12-09 Microsoft Corporation System for determining at subgroup of nodes relative weight to represent cluster by obtaining exclusive possession of quorum resource
US6611911B1 (en) 1999-12-30 2003-08-26 Intel Corporation Bootstrap processor election mechanism on multiple cluster bus system
US7076551B2 (en) * 2000-04-03 2006-07-11 Texas Instruments Incorporated Using remote procedure calls to manage co-processor resources
US6584560B1 (en) * 2000-04-19 2003-06-24 Dell Usa, L.P. Method and system for booting a multiprocessor computer
US6766474B2 (en) * 2000-12-21 2004-07-20 Intel Corporation Multi-staged bios-based memory testing
US20020087828A1 (en) * 2000-12-28 2002-07-04 International Business Machines Corporation Symmetric multiprocessing (SMP) system with fully-interconnected heterogenous microprocessors
US6760838B2 (en) * 2001-01-31 2004-07-06 Advanced Micro Devices, Inc. System and method of initializing and determining a bootstrap processor [BSP] in a fabric of a distributed multiprocessor computing system
US6925556B2 (en) * 2001-02-14 2005-08-02 Intel Corporation Method and system to determine the bootstrap processor from a plurality of operable processors
US7251723B2 (en) * 2001-06-19 2007-07-31 Intel Corporation Fault resilient booting for multiprocessor system using appliance server management
GB0328153D0 (en) * 2003-12-04 2004-01-07 Electronic Game Card Ltd An electronic game device
US20040235550A1 (en) * 2001-07-20 2004-11-25 Mcnally Gordon Game device
US7277952B2 (en) * 2001-09-28 2007-10-02 Microsoft Corporation Distributed system resource protection via arbitration and ownership
US7350063B2 (en) 2002-06-11 2008-03-25 Intel Corporation System and method to filter processors by health during early firmware for split recovery architecture
US7065641B2 (en) * 2002-06-13 2006-06-20 Intel Corporation Weighted processor selection apparatus and method for use in multiprocessor systems
US7100034B2 (en) * 2003-05-23 2006-08-29 Hewlett-Packard Development Company, L.P. System for selecting another processor to be the boot strap processor when the default boot strap processor does not have local memory
TW591538B (en) * 2003-07-25 2004-06-11 Via Tech Inc Process for loading operating system
FR2862397A1 (fr) * 2003-11-13 2005-05-20 St Microelectronics Sa Demarrage securise d'un appareil electronique a architecture smp
US7222200B2 (en) * 2004-10-14 2007-05-22 Dell Products L.P. Method for synchronizing processors in SMI following a memory hot plug event
US20060156291A1 (en) * 2005-01-12 2006-07-13 Dell Products L.P. System and method for managing processor execution in a multiprocessor system
US7984281B2 (en) * 2005-10-18 2011-07-19 Qualcomm Incorporated Shared interrupt controller for a multi-threaded processor
US7702889B2 (en) * 2005-10-18 2010-04-20 Qualcomm Incorporated Shared interrupt control method and system for a digital signal processor
US7600109B2 (en) * 2006-06-01 2009-10-06 Dell Products L.P. Method and system for initializing application processors in a multi-processor system prior to the initialization of main memory
US7702893B1 (en) * 2006-09-22 2010-04-20 Altera Corporation Integrated circuits with configurable initialization data memory addresses
DK2083532T3 (da) 2008-01-23 2014-02-10 Comptel Corp Konvergerende formidlingssystem med forbedret dataoverføring
EP2107464A1 (de) * 2008-01-23 2009-10-07 Comptel Corporation Konvergentes Vermittlungssystem mit dynamischer Ressourcenzuweisung
US8954721B2 (en) 2011-12-08 2015-02-10 International Business Machines Corporation Multi-chip initialization using a parallel firmware boot process
CN103164234A (zh) * 2011-12-13 2013-06-19 鸿富锦精密工业(深圳)有限公司 双处理器切换装置
US9658861B2 (en) * 2011-12-29 2017-05-23 Intel Corporation Boot strap processor assignment for a multi-core processing unit
US9507404B2 (en) 2013-08-28 2016-11-29 Via Technologies, Inc. Single core wakeup multi-core synchronization mechanism
US9465432B2 (en) 2013-08-28 2016-10-11 Via Technologies, Inc. Multi-core synchronization mechanism
US9792112B2 (en) 2013-08-28 2017-10-17 Via Technologies, Inc. Propagation of microcode patches to multiple cores in multicore microprocessor
EP3324288B1 (de) * 2016-11-21 2021-09-08 VIA Technologies, Inc. Mehrkernmikroprozessor, der einen seiner prozessorkerne dynamisch als bootstrap-prozessor bestimmt
US11113113B2 (en) 2017-09-08 2021-09-07 Apple Inc. Systems and methods for scheduling virtual memory compressors
US11010173B2 (en) * 2019-09-17 2021-05-18 Dell Products L.P. Adjusting a processing state of an information handling system from multi-socket mode to multi-single socket mode

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3461825B2 (ja) * 1991-06-26 2003-10-27 三星電子株式会社 マルチプロセッサ分散型初期化および自己テストシステム
US5642506A (en) * 1994-12-14 1997-06-24 International Business Machines Corporation Method and apparatus for initializing a multiprocessor system
US5495569A (en) * 1994-12-30 1996-02-27 Compaq Computer Corp. Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active
US5675772A (en) * 1995-03-23 1997-10-07 Industrial Technology Research Institute Device and method for reconfiguring a computer system with an incompatible CPU
EP0817998A4 (de) * 1995-03-31 1998-09-23 Intel Corp Testen des speichers in einem mehrprozessor-computersystem
US5758325A (en) * 1995-06-21 1998-05-26 Mark Voting Systems, Inc. Electronic voting system that automatically returns to proper operating state after power outage
US5768585A (en) * 1995-11-21 1998-06-16 Intel Corporation System and method for synchronizing multiple processors during power-on self testing
US5724527A (en) * 1995-12-28 1998-03-03 Intel Corporation Fault-tolerant boot strap mechanism for a multiprocessor system
US5860002A (en) * 1996-07-12 1999-01-12 Digital Equipment Corporation System for assigning boot strap processor in symmetric multiprocessor computer with watchdog reassignment
US5790850A (en) * 1996-09-30 1998-08-04 Intel Corporation Fault resilient booting for multiprocessor computer systems
US5862151A (en) * 1997-01-23 1999-01-19 Unisys Corporation Array self-test fault tolerant programmable threshold algorithm
US5904733A (en) * 1997-07-31 1999-05-18 Intel Corporation Bootstrap processor selection architecture in SMP systems

Also Published As

Publication number Publication date
EP1010062B1 (de) 2003-10-29
EP1010062A1 (de) 2000-06-21
US6108781A (en) 2000-08-22
US5904733A (en) 1999-05-18
WO1999006908A1 (en) 1999-02-11
AU8594498A (en) 1999-02-22
DE69819347T2 (de) 2004-07-22
EP1010062A4 (de) 2001-11-21

Similar Documents

Publication Publication Date Title
DE69819347D1 (de) Bootstrap prozessorauswahl in einem multiprozessorsystem
DE69716663D1 (de) Prozesszuweisung in einem Mehrrechnersystem
DE69706440D1 (de) Schutzmittel in einem verteilten rechnersystem
DE69727407D1 (de) Verteilte Ausführung von modusungeeigneten Befehlen in Multiprozessorsysteme
DE19983330T1 (de) Computerprozessor mit einem Wiederholsystem
DE69825350D1 (de) Verzweigungsvorhersage in Rechnersystem
BR9506405A (pt) Estrutura de suporte alongada numa primeria direçao
DE69527499D1 (de) Schaltung zum Wiederzuweisen des Einschaltsprozessors in einem Mehrprozessorensystem
DE69715967D1 (de) Quorummechanismus in einem verteilten Zweiknotenrechnersystem
DE69811295D1 (de) Fahrradcomputer
DE69804548D1 (de) Computergehäuse
ID24808A (id) Prosesor data
DE69628984D1 (de) Computergehäuse
EP0970427A4 (de) Neues verteiltes vielfachprozessor-speichersystem sowwie schaltkreis und verfahren dafür
DE69734303D1 (de) Pipeline-Befehlszuteilungseinheit in einem superskalaren Prozessor
DE69816523D1 (de) Entwicklungsgerät
DE69817170D1 (de) Emulation von unterbrechungsmechanismus in einem multiprozessorsystem
GB2329984B (en) A Multi-Processor Computer System
DE69829987D1 (de) E/a bus mit schnellen 16-bit zerteilten transaktionen
IT1304675B1 (it) Procedimento per simulare un dispositivo di memoria di elaboratore.
DE69616680D1 (de) Entwicklungsgerät
DE69614582D1 (de) Entwicklungsgerät
DE69802290D1 (de) Gemeinsame unterbrechungsverarbeitung in einem datenverarbeitungssystem
DE69819235D1 (de) Entwicklungsgerät
DE69824055D1 (de) Entwicklungsgerät

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806

8339 Ceased/non-payment of the annual fee