DE69636613D1 - Synchronisation von Paritätsbits zur Fehlervermeidung beim Umschalten zwischen einem aktiven und einem stand-by Prozessor - Google Patents

Synchronisation von Paritätsbits zur Fehlervermeidung beim Umschalten zwischen einem aktiven und einem stand-by Prozessor

Info

Publication number
DE69636613D1
DE69636613D1 DE69636613T DE69636613T DE69636613D1 DE 69636613 D1 DE69636613 D1 DE 69636613D1 DE 69636613 T DE69636613 T DE 69636613T DE 69636613 T DE69636613 T DE 69636613T DE 69636613 D1 DE69636613 D1 DE 69636613D1
Authority
DE
Germany
Prior art keywords
synchronization
stand
switching
processor
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69636613T
Other languages
English (en)
Other versions
DE69636613T2 (de
Inventor
James Arthur Doubler
Michael Paul Hammer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
AT&T IPM Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp, AT&T IPM Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69636613D1 publication Critical patent/DE69636613D1/de
Publication of DE69636613T2 publication Critical patent/DE69636613T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
  • Time-Division Multiplex Systems (AREA)
DE69636613T 1995-04-28 1996-04-17 Synchronisation von Paritätsbits zur Fehlervermeidung beim Umschalten zwischen einem aktiven und einem stand-by Prozessor Expired - Fee Related DE69636613T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/430,627 US5838698A (en) 1995-04-28 1995-04-28 Alignment of parity bits to eliminate errors in switching from an active to a standby processing circuit
US430627 1995-04-28

Publications (2)

Publication Number Publication Date
DE69636613D1 true DE69636613D1 (de) 2006-11-23
DE69636613T2 DE69636613T2 (de) 2007-08-09

Family

ID=23708364

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69636613T Expired - Fee Related DE69636613T2 (de) 1995-04-28 1996-04-17 Synchronisation von Paritätsbits zur Fehlervermeidung beim Umschalten zwischen einem aktiven und einem stand-by Prozessor

Country Status (6)

Country Link
US (1) US5838698A (de)
EP (1) EP0740435B1 (de)
JP (1) JP3263307B2 (de)
CA (1) CA2171225C (de)
DE (1) DE69636613T2 (de)
ES (1) ES2271949T3 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100233458B1 (ko) * 1997-05-19 1999-12-01 윤종용 원격 다중 가입자의 호처리 이중화 방법
US6738935B1 (en) * 2000-02-07 2004-05-18 3Com Corporation Coding sublayer for multi-channel media with error correction
US6972683B2 (en) * 2001-07-20 2005-12-06 Hill-Rom Services, Inc. Badge for a locating and tracking system
US7385929B1 (en) * 2001-09-25 2008-06-10 Atheros Communications, Inc. Method and system for detecting false packets in wireless communications systems
WO2010076835A1 (en) * 2008-12-31 2010-07-08 Christophe Laurent Error correction code for unidirectional memory
JP5649855B2 (ja) * 2010-06-01 2015-01-07 富士通株式会社 伝送装置およびパリティ演算方法
US10734110B2 (en) 2018-12-05 2020-08-04 Hill-Rom Services, Inc. Caregiver locating tag having advanced functionality
US11411584B2 (en) * 2020-09-28 2022-08-09 Western Digital Technologies, Inc. Data storage device channel encoding current data using redundancy bits generated over preceding data

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546475A (en) * 1982-12-06 1985-10-08 At&T Bell Laboratories Parity checking arrangement
US4543651A (en) * 1983-09-12 1985-09-24 At&T Bell Laboratories Duplicated time division switching system
JPH03198544A (ja) * 1989-12-27 1991-08-29 Nec Corp パリティ計数回路
US5392424A (en) * 1992-06-11 1995-02-21 Allen-Bradley Company, Inc. Apparatus for detecting parity errors among asynchronous digital signals
DE4226599C2 (de) * 1992-08-11 1994-08-04 Siemens Ag Verfahren zur Fehlererkennung in digitalen Kommunikationssystemen
FI96078C (fi) * 1994-05-09 1996-04-25 Nokia Telecommunications Oy Menetelmä yksikönvaihdon suorittamiseksi pakettimuotoista dataa välittävässä tietoliikennesolmussa

Also Published As

Publication number Publication date
US5838698A (en) 1998-11-17
EP0740435B1 (de) 2006-10-11
DE69636613T2 (de) 2007-08-09
CA2171225C (en) 1999-12-28
ES2271949T3 (es) 2007-04-16
EP0740435A2 (de) 1996-10-30
JPH0983497A (ja) 1997-03-28
CA2171225A1 (en) 1996-10-29
EP0740435A3 (de) 2000-02-23
JP3263307B2 (ja) 2002-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee