DE69320229D1 - DRAM mit geringem Leistungsverbrauch - Google Patents

DRAM mit geringem Leistungsverbrauch

Info

Publication number
DE69320229D1
DE69320229D1 DE69320229T DE69320229T DE69320229D1 DE 69320229 D1 DE69320229 D1 DE 69320229D1 DE 69320229 T DE69320229 T DE 69320229T DE 69320229 T DE69320229 T DE 69320229T DE 69320229 D1 DE69320229 D1 DE 69320229D1
Authority
DE
Germany
Prior art keywords
dram
power consumption
low power
low
consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69320229T
Other languages
English (en)
Other versions
DE69320229T2 (de
Inventor
Sheffield S Eaton Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UMC Japan Co Ltd
United Memories Inc
Original Assignee
Nippon Steel Semiconductor Corp
United Memories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Semiconductor Corp, United Memories Inc filed Critical Nippon Steel Semiconductor Corp
Publication of DE69320229D1 publication Critical patent/DE69320229D1/de
Application granted granted Critical
Publication of DE69320229T2 publication Critical patent/DE69320229T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69320229T 1992-03-30 1993-01-26 DRAM mit geringem Leistungsverbrauch Expired - Lifetime DE69320229T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/859,670 US5317538A (en) 1992-03-30 1992-03-30 Low power DRAM

Publications (2)

Publication Number Publication Date
DE69320229D1 true DE69320229D1 (de) 1998-09-17
DE69320229T2 DE69320229T2 (de) 1999-04-01

Family

ID=25331460

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69320229T Expired - Lifetime DE69320229T2 (de) 1992-03-30 1993-01-26 DRAM mit geringem Leistungsverbrauch

Country Status (5)

Country Link
US (1) US5317538A (de)
EP (1) EP0563521B1 (de)
JP (1) JPH0628855A (de)
KR (1) KR930020456A (de)
DE (1) DE69320229T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100214462B1 (ko) * 1995-11-27 1999-08-02 구본준 반도체메모리셀의 라이트 방법
KR0170903B1 (ko) * 1995-12-08 1999-03-30 김주용 하위 워드 라인 구동 회로 및 이를 이용한 반도체 메모리 장치
KR0180781B1 (ko) * 1995-12-29 1999-04-15 김주용 비트라인 센스 앰프 구동 회로
US5717644A (en) * 1996-10-09 1998-02-10 International Business Machines Corporation Apparatus for varying the refresh rate for a DRAM in response to variation in operating voltages and method thereof
KR19990013146A (ko) * 1997-07-31 1999-02-25 윤종용 리프레시 동작모드시 소비되는 동작전류를 감소시키기 위한 반도체 메모리 장치
KR100507701B1 (ko) 2001-12-06 2005-08-09 주식회사 하이닉스반도체 부스트랩 회로
KR100512369B1 (ko) 2003-05-30 2005-09-02 주식회사 하이닉스반도체 센스 엠프 선택 회로 및 센스엠프 선택 방법
US10438646B1 (en) * 2018-07-03 2019-10-08 Micron Technology, Inc. Apparatuses and methods for providing power for memory refresh operations

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506351A (en) * 1982-06-23 1985-03-19 International Business Machines Corporation One-device random access memory having enhanced sense signal
JP3037377B2 (ja) * 1990-08-27 2000-04-24 沖電気工業株式会社 半導体記憶装置

Also Published As

Publication number Publication date
EP0563521A2 (de) 1993-10-06
EP0563521B1 (de) 1998-08-12
EP0563521A3 (en) 1994-09-21
KR930020456A (ko) 1993-10-19
JPH0628855A (ja) 1994-02-04
US5317538A (en) 1994-05-31
DE69320229T2 (de) 1999-04-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: FIENER, J., PAT.-ANW., 87719 MINDELHEIM

8330 Complete disclaimer