DE69220644T2 - Herstellung von Dielektrika in Halbleitervorrichtungen - Google Patents

Herstellung von Dielektrika in Halbleitervorrichtungen

Info

Publication number
DE69220644T2
DE69220644T2 DE69220644T DE69220644T DE69220644T2 DE 69220644 T2 DE69220644 T2 DE 69220644T2 DE 69220644 T DE69220644 T DE 69220644T DE 69220644 T DE69220644 T DE 69220644T DE 69220644 T2 DE69220644 T2 DE 69220644T2
Authority
DE
Germany
Prior art keywords
insulating layer
layer
parts
exposed
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69220644T
Other languages
German (de)
English (en)
Other versions
DE69220644D1 (de
Inventor
Ji-Hyun Process Developme Choi
Chang-Gyu Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE69220644D1 publication Critical patent/DE69220644D1/de
Application granted granted Critical
Publication of DE69220644T2 publication Critical patent/DE69220644T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
DE69220644T 1991-10-10 1992-10-08 Herstellung von Dielektrika in Halbleitervorrichtungen Expired - Lifetime DE69220644T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910017740A KR950002948B1 (ko) 1991-10-10 1991-10-10 반도체 장치의 금속층간 절연막 형성방법

Publications (2)

Publication Number Publication Date
DE69220644D1 DE69220644D1 (de) 1997-08-07
DE69220644T2 true DE69220644T2 (de) 1998-01-15

Family

ID=19321006

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220644T Expired - Lifetime DE69220644T2 (de) 1991-10-10 1992-10-08 Herstellung von Dielektrika in Halbleitervorrichtungen

Country Status (6)

Country Link
US (1) US5352630A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0537001B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH0777219B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR950002948B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69220644T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW278216B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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JP2795029B2 (ja) * 1992-02-24 1998-09-10 日本電気株式会社 多層配線の形成方法
JP3158749B2 (ja) * 1992-12-16 2001-04-23 ヤマハ株式会社 半導体装置
JPH0770534B2 (ja) * 1993-01-11 1995-07-31 日本電気株式会社 半導体装置の製造方法
JP2629579B2 (ja) * 1993-10-14 1997-07-09 日本電気株式会社 半導体装置の製造方法及び製造装置
JPH088209A (ja) * 1994-01-10 1996-01-12 Cypress Semiconductor Corp 半導体装置の製造のための除去されるポストの処理方法
US5488015A (en) * 1994-05-20 1996-01-30 Texas Instruments Incorporated Method of making an interconnect structure with an integrated low density dielectric
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
KR950034755A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1994-05-27 1995-12-28
JPH0855913A (ja) * 1994-06-07 1996-02-27 Texas Instr Inc <Ti> サブミクロン相互接続の選択的空隙充填方法
JP3015717B2 (ja) * 1994-09-14 2000-03-06 三洋電機株式会社 半導体装置の製造方法および半導体装置
US5482900A (en) * 1994-09-16 1996-01-09 United Microelectronics Corporation Method for forming a metallurgy system having a dielectric layer that is planar and void free
US5652084A (en) * 1994-12-22 1997-07-29 Cypress Semiconductor Corporation Method for reduced pitch lithography
US5496776A (en) * 1995-04-27 1996-03-05 United Microelectronics Corporation Spin-on-glass planarization process with ion implantation
US5489553A (en) * 1995-05-25 1996-02-06 Industrial Technology Research Institute HF vapor surface treatment for the 03 teos gap filling deposition
KR0179838B1 (ko) * 1995-09-02 1999-04-15 문정환 반도체 소자의 절연막 구조 및 절연막 평탄화 방법
US20010048147A1 (en) * 1995-09-14 2001-12-06 Hideki Mizuhara Semiconductor devices passivation film
US6268657B1 (en) 1995-09-14 2001-07-31 Sanyo Electric Co., Ltd. Semiconductor devices and an insulating layer with an impurity
US5599740A (en) * 1995-11-16 1997-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Deposit-etch-deposit ozone/teos insulator layer method
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
US5817571A (en) * 1996-06-10 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multilayer interlevel dielectrics using phosphorus-doped glass
US5792705A (en) * 1996-06-28 1998-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Optimized planarization process for SOG filled vias
DE19629766C2 (de) * 1996-07-23 2002-06-27 Infineon Technologies Ag Herstellverfahren von Shallow-Trench-Isolationsbereiche in einem Substrat
DE19631743C2 (de) * 1996-08-06 2002-05-29 Infineon Technologies Ag Herstellverfahren für eine als Intermetalldielektrikum fungierende Isolatorschicht
KR100383498B1 (ko) 1996-08-30 2003-08-19 산요 덴키 가부시키가이샤 반도체 장치 제조방법
US6288438B1 (en) 1996-09-06 2001-09-11 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US5888897A (en) * 1996-10-31 1999-03-30 Intel Corporation Process for forming an integrated structure comprising a self-aligned via/contact and interconnect
JP3015767B2 (ja) * 1996-12-25 2000-03-06 三洋電機株式会社 半導体装置の製造方法及び半導体装置
JP2975934B2 (ja) 1997-09-26 1999-11-10 三洋電機株式会社 半導体装置の製造方法及び半導体装置
US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6794283B2 (en) 1998-05-29 2004-09-21 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
US6071826A (en) * 1999-02-12 2000-06-06 Taiwan Semiconductor Manufacturing Company Method of manufacturing CMOS image sensor leakage free with double layer spacer
US6306561B1 (en) * 1999-03-04 2001-10-23 National Semiconductor Corporation Double metal pixel array for light valve utilizing lateral sublithographic spacer isolation
US6303273B1 (en) * 1999-03-04 2001-10-16 National Semiconductor Corporation Single metal pixel array for light valve utilizing lateral sublithographic spacer isolation
DE19944740C2 (de) * 1999-09-17 2001-10-25 Infineon Technologies Ag Abscheidung verschiedener Untergrundschichten für selektives Schichtwachstum in der Halbleiterfertigung
JP3479010B2 (ja) * 1999-11-04 2003-12-15 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
KR100358069B1 (ko) * 1999-12-27 2002-10-25 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
US6287952B1 (en) 1999-12-28 2001-09-11 Agere Systems Guardian Corp. Method of etching self-aligned vias to metal using a silicon nitride spacer
US6511923B1 (en) * 2000-05-19 2003-01-28 Applied Materials, Inc. Deposition of stable dielectric films
US6917110B2 (en) * 2001-12-07 2005-07-12 Sanyo Electric Co., Ltd. Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer
KR100935251B1 (ko) * 2003-07-11 2010-01-06 매그나칩 반도체 유한회사 반도체 소자의 나노 스페이스 제조 방법
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KR102304724B1 (ko) * 2014-12-19 2021-09-27 삼성디스플레이 주식회사 박막트랜지스터 기판, 이를 포함하는 디스플레이 장치, 박막트랜지스터 기판 제조방법 및 이를 이용한 디스플레이 장치 제조방법

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Also Published As

Publication number Publication date
EP0537001B1 (en) 1997-07-02
US5352630A (en) 1994-10-04
DE69220644D1 (de) 1997-08-07
JPH0777219B2 (ja) 1995-08-16
TW278216B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1996-06-11
KR950002948B1 (ko) 1995-03-28
EP0537001A1 (en) 1993-04-14
JPH05206128A (ja) 1993-08-13

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