DE69028836D1 - Data processing system with direct memory access control and method for bus master change using interruptions with given priority - Google Patents
Data processing system with direct memory access control and method for bus master change using interruptions with given priorityInfo
- Publication number
- DE69028836D1 DE69028836D1 DE69028836T DE69028836T DE69028836D1 DE 69028836 D1 DE69028836 D1 DE 69028836D1 DE 69028836 T DE69028836 T DE 69028836T DE 69028836 T DE69028836 T DE 69028836T DE 69028836 D1 DE69028836 D1 DE 69028836D1
- Authority
- DE
- Germany
- Prior art keywords
- interruptions
- data processing
- processing system
- access control
- memory access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
- G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/457,647 US5072365A (en) | 1989-12-27 | 1989-12-27 | Direct memory access controller using prioritized interrupts for varying bus mastership |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69028836D1 true DE69028836D1 (en) | 1996-11-14 |
DE69028836T2 DE69028836T2 (en) | 1997-04-10 |
Family
ID=23817586
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69028836T Expired - Fee Related DE69028836T2 (en) | 1989-12-27 | 1990-12-13 | Data processing system with direct memory access control and method for bus master change using interruptions with given priority |
Country Status (5)
Country | Link |
---|---|
US (1) | US5072365A (en) |
EP (1) | EP0435092B1 (en) |
JP (1) | JP3284311B2 (en) |
DE (1) | DE69028836T2 (en) |
HK (1) | HK1003803A1 (en) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9018992D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Internal bus for work station interfacing means |
GB9019001D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Work station including a direct memory access controller and interfacing means to microchannel means |
US5287523A (en) * | 1990-10-09 | 1994-02-15 | Motorola, Inc. | Method for servicing a peripheral interrupt request in a microcontroller |
US5289583A (en) * | 1990-10-19 | 1994-02-22 | International Business Machines Corporation | Bus master with antilockup and no idle bus cycles |
JPH05165762A (en) * | 1991-12-13 | 1993-07-02 | Toshiba Corp | Dma controller |
US5590380A (en) * | 1992-04-22 | 1996-12-31 | Kabushiki Kaisha Toshiba | Multiprocessor system with processor arbitration and priority level setting by the selected processor |
US5517624A (en) * | 1992-10-02 | 1996-05-14 | Compaq Computer Corporation | Multiplexed communication protocol between central and distributed peripherals in multiprocessor computer systems |
US5664224A (en) * | 1993-07-23 | 1997-09-02 | Escom Ag | Apparatus for selectively loading data blocks from CD-ROM disks to buffer segments using DMA operations |
US6018785A (en) * | 1993-12-30 | 2000-01-25 | Cypress Semiconductor Corp. | Interrupt-generating hardware semaphore |
US5619726A (en) * | 1994-10-11 | 1997-04-08 | Intel Corporation | Apparatus and method for performing arbitration and data transfer over multiple buses |
JP2996183B2 (en) * | 1996-08-16 | 1999-12-27 | 日本電気株式会社 | Data processing device with DMA function |
JPH10133998A (en) * | 1996-11-05 | 1998-05-22 | Canon Inc | Data processing method and recorder using the method |
US6816934B2 (en) * | 2000-12-22 | 2004-11-09 | Hewlett-Packard Development Company, L.P. | Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol |
US6738845B1 (en) * | 1999-11-05 | 2004-05-18 | Analog Devices, Inc. | Bus architecture and shared bus arbitration method for a communication device |
US6775727B2 (en) | 2001-06-23 | 2004-08-10 | Freescale Semiconductor, Inc. | System and method for controlling bus arbitration during cache memory burst cycles |
JP2003050774A (en) * | 2001-08-08 | 2003-02-21 | Matsushita Electric Ind Co Ltd | Data processor and data transfer method |
KR100456696B1 (en) * | 2002-05-21 | 2004-11-10 | 삼성전자주식회사 | Bus arbiter for integrated circuit systems |
US7013357B2 (en) * | 2003-09-12 | 2006-03-14 | Freescale Semiconductor, Inc. | Arbiter having programmable arbitration points for undefined length burst accesses and method |
KR102225249B1 (en) * | 2014-06-28 | 2021-03-08 | 인텔 코포레이션 | Sensor bus interface for electronic devices |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4023143A (en) * | 1975-10-28 | 1977-05-10 | Cincinnati Milacron Inc. | Fixed priority interrupt control circuit |
US4067059A (en) * | 1976-01-29 | 1978-01-03 | Sperry Rand Corporation | Shared direct memory access controller |
US4035780A (en) * | 1976-05-21 | 1977-07-12 | Honeywell Information Systems, Inc. | Priority interrupt logic circuits |
US4257095A (en) * | 1978-06-30 | 1981-03-17 | Intel Corporation | System bus arbitration, circuitry and methodology |
US4200912A (en) * | 1978-07-31 | 1980-04-29 | Motorola, Inc. | Processor interrupt system |
US4240140A (en) * | 1978-12-26 | 1980-12-16 | Honeywell Information Systems Inc. | CRT display terminal priority interrupt apparatus for generating vectored addresses |
US4443848A (en) * | 1979-09-10 | 1984-04-17 | Nixdorf Computer Corporation | Two-level priority circuit |
US4470111A (en) * | 1979-10-01 | 1984-09-04 | Ncr Corporation | Priority interrupt controller |
JPS58222361A (en) * | 1982-06-18 | 1983-12-24 | Fujitsu Ltd | Control system of priority decision for access request in data processing system |
US4494192A (en) * | 1982-07-21 | 1985-01-15 | Sperry Corporation | High speed bus architecture |
JPS61125670A (en) * | 1984-11-24 | 1986-06-13 | Olympus Optical Co Ltd | Data transfer device |
US4802087A (en) * | 1986-06-27 | 1989-01-31 | Honeywell Bull Inc. | Multiprocessor level change synchronization apparatus |
DE3782335T2 (en) * | 1987-04-22 | 1993-05-06 | Ibm | MEMORY CONTROL SYSTEM. |
JPS63296139A (en) * | 1987-05-27 | 1988-12-02 | Fujitsu Ltd | Interruption control circuit |
JPH01277928A (en) * | 1988-04-30 | 1989-11-08 | Oki Electric Ind Co Ltd | Printer |
-
1989
- 1989-12-27 US US07/457,647 patent/US5072365A/en not_active Expired - Lifetime
-
1990
- 1990-12-13 DE DE69028836T patent/DE69028836T2/en not_active Expired - Fee Related
- 1990-12-13 EP EP90124104A patent/EP0435092B1/en not_active Expired - Lifetime
- 1990-12-26 JP JP41819390A patent/JP3284311B2/en not_active Expired - Lifetime
-
1998
- 1998-04-01 HK HK98102728A patent/HK1003803A1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69028836T2 (en) | 1997-04-10 |
HK1003803A1 (en) | 1998-11-06 |
US5072365A (en) | 1991-12-10 |
JPH04211855A (en) | 1992-08-03 |
EP0435092A2 (en) | 1991-07-03 |
JP3284311B2 (en) | 2002-05-20 |
EP0435092A3 (en) | 1991-11-27 |
EP0435092B1 (en) | 1996-10-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |