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Synchronisationsbefehl für Mehrprozessornetz.

Info

Publication number
DE69022709D1
DE69022709D1 DE1990622709 DE69022709A DE69022709D1 DE 69022709 D1 DE69022709 D1 DE 69022709D1 DE 1990622709 DE1990622709 DE 1990622709 DE 69022709 A DE69022709 A DE 69022709A DE 69022709 D1 DE69022709 D1 DE 69022709D1
Authority
DE
Grant status
Grant
Patent type
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1990622709
Other languages
English (en)
Other versions
DE69022709T2 (de )
Inventor
Diane Lacey Knipfer Di Knipfer
Lynn Allen Mcmahon
Charlotte Bennett Metgzer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformations of program code
    • G06F8/41Compilation
    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/458Synchronisation, e.g. post-wait, barriers, locks
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/80Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
DE1990622709 1990-01-17 1990-12-12 Synchronisationsbefehl für Mehrprozessornetz. Expired - Fee Related DE69022709D1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US46653890 true 1990-01-17 1990-01-17

Publications (1)

Publication Number Publication Date
DE69022709D1 true DE69022709D1 (de) 1995-11-02

Family

ID=23852143

Family Applications (2)

Application Number Title Priority Date Filing Date
DE1990622709 Expired - Lifetime DE69022709T2 (de) 1990-01-17 1990-12-12 Synchronisationsbefehl für Mehrprozessornetz.
DE1990622709 Expired - Fee Related DE69022709D1 (de) 1990-01-17 1990-12-12 Synchronisationsbefehl für Mehrprozessornetz.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE1990622709 Expired - Lifetime DE69022709T2 (de) 1990-01-17 1990-12-12 Synchronisationsbefehl für Mehrprozessornetz.

Country Status (4)

Country Link
US (1) US5307483A (de)
JP (1) JPH07101410B2 (de)
DE (2) DE69022709T2 (de)
EP (1) EP0438021B1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69130630T2 (de) * 1990-09-14 1999-09-09 Hitachi Ltd Synchrones Verfahren und Gerät für Prozessoren
US5442772A (en) * 1991-03-29 1995-08-15 International Business Machines Corporation Common breakpoint in virtual time logic simulation for parallel processors
US5423044A (en) * 1992-06-16 1995-06-06 International Business Machines Corporation Shared, distributed lock manager for loosely coupled processing systems
JPH06110846A (ja) * 1992-09-25 1994-04-22 Fujitsu Ltd 排他制御方式
US5522029A (en) * 1993-04-23 1996-05-28 International Business Machines Corporation Fault tolerant rendezvous and semaphore for multiple parallel processors
CA2137046C (en) * 1994-03-31 2000-01-18 Seungyoon P. Song Processing system and method of operation
US5550973A (en) * 1995-03-15 1996-08-27 International Business Machines Corporation System and method for failure recovery in a shared resource system having a moving write lock
JPH10149285A (ja) * 1996-11-18 1998-06-02 Hitachi Ltd 命令実行制御方法および情報処理装置
US6295601B1 (en) * 1997-05-30 2001-09-25 Sun Micro Systems, Inc. System and method using partial trap barrier instruction to provide trap barrier class-based selective stall of instruction processing pipeline
GB9804111D0 (en) * 1998-02-27 1998-04-22 Lucas Ind Plc Distributed data processing system
US6088792A (en) * 1998-04-30 2000-07-11 International Business Machines Corporation Avoiding processor serialization after an S/390 SPKA instruction
US6088791A (en) * 1998-04-30 2000-07-11 International Business Machines Corporation Computer processor system for implementing the ESA/390 STOSM and STNSM instructions without serialization or artificially extending processor execution time
US6542985B1 (en) * 1999-09-23 2003-04-01 Unisys Corporation Event counter
US6823355B1 (en) 2000-05-31 2004-11-23 International Business Machines Corporation Synchronous replication of transactions in a distributed system
US7178137B1 (en) 2001-04-05 2007-02-13 Network Appliance, Inc. Automatic verification of scheduling domain consistency
US7694302B1 (en) * 2001-04-05 2010-04-06 Network Appliance, Inc. Symmetric multiprocessor synchronization using migrating scheduling domains
US7373640B1 (en) 2003-07-31 2008-05-13 Network Appliance, Inc. Technique for dynamically restricting thread concurrency without rewriting thread code
US8171480B2 (en) * 2004-01-27 2012-05-01 Network Appliance, Inc. Method and apparatus for allocating shared resources to process domains according to current processor utilization in a shared resource processor
US8347293B2 (en) * 2005-10-20 2013-01-01 Network Appliance, Inc. Mutual exclusion domains to perform file system processes on stripes
US8627331B1 (en) 2010-04-30 2014-01-07 Netapp, Inc. Multi-level parallelism of process execution in a mutual exclusion domain of a processing system
US8688880B2 (en) * 2010-06-23 2014-04-01 International Business Machines Corporation Centralized serialization of requests in a multiprocessor system
CN102880585B (zh) * 2012-09-28 2015-05-06 无锡江南计算技术研究所 用于具有多个处理器核心的处理器系统的同步器
US8972767B2 (en) * 2012-11-16 2015-03-03 Oracle International Corporation Method and apparatus for synchronizing the time reference of a dynamically activated processor to the system time reference

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810119A (en) * 1971-05-04 1974-05-07 Us Navy Processor synchronization scheme
FR2253418A5 (de) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
US4344133A (en) * 1978-07-31 1982-08-10 Motorola, Inc. Method for synchronizing hardware and software
US4409653A (en) * 1978-07-31 1983-10-11 Motorola, Inc. Method of performing a clear and wait operation with a single instruction
US4412303A (en) * 1979-11-26 1983-10-25 Burroughs Corporation Array processor architecture
US4891749A (en) * 1983-03-28 1990-01-02 International Business Machines Corporation Multiprocessor storage serialization apparatus
JPH0120466B2 (de) * 1983-10-07 1989-04-17 Nippon Electric Co
US4709326A (en) * 1984-06-29 1987-11-24 International Business Machines Corporation General locking/synchronization facility with canonical states and mapping of processors
US4783736A (en) * 1985-07-22 1988-11-08 Alliant Computer Systems Corporation Digital computer with multisection cache
US4809169A (en) * 1986-04-23 1989-02-28 Advanced Micro Devices, Inc. Parallel, multiple coprocessor computer architecture having plural execution modes
US4809168A (en) * 1986-10-17 1989-02-28 International Business Machines Corporation Passive serialization in a multitasking environment
US4816990A (en) * 1986-11-05 1989-03-28 Stratus Computer, Inc. Method and apparatus for fault-tolerant computer system having expandable processor section
US4926320A (en) * 1987-04-07 1990-05-15 Nec Corporation Information processing system having microprogram-controlled type arithmetic processing unit
JP2519798B2 (ja) * 1989-05-30 1996-07-31 富士通株式会社 多重プロセッサシステムにおけるシリアライズ機能の検証方式

Also Published As

Publication number Publication date Type
US5307483A (en) 1994-04-26 grant
EP0438021A2 (de) 1991-07-24 application
JPH07101410B2 (ja) 1995-11-01 grant
JP2061691C (de) grant
EP0438021A3 (en) 1991-12-04 application
DE69022709T2 (de) 1996-05-02 grant
JPH03222057A (en) 1991-10-01 application
EP0438021B1 (de) 1995-09-27 grant

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee