DE68923468T2 - Process for the production of multilayer circuits. - Google Patents

Process for the production of multilayer circuits.

Info

Publication number
DE68923468T2
DE68923468T2 DE68923468T DE68923468T DE68923468T2 DE 68923468 T2 DE68923468 T2 DE 68923468T2 DE 68923468 T DE68923468 T DE 68923468T DE 68923468 T DE68923468 T DE 68923468T DE 68923468 T2 DE68923468 T2 DE 68923468T2
Authority
DE
Germany
Prior art keywords
production
multilayer circuits
multilayer
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923468T
Other languages
German (de)
Other versions
DE68923468D1 (en
Inventor
Joseph Richard Rellick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EIDP Inc
Original Assignee
EI Du Pont de Nemours and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EI Du Pont de Nemours and Co filed Critical EI Du Pont de Nemours and Co
Application granted granted Critical
Publication of DE68923468D1 publication Critical patent/DE68923468D1/en
Publication of DE68923468T2 publication Critical patent/DE68923468T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H05K3/4667Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06Lamination
    • H05K2203/068Features of the lamination press or of the lamination process, e.g. using special separator sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107Using laser light
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10Methods of surface bonding and/or assembly therefor
    • Y10T156/1052Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056Perforating lamina
    • Y10T156/1057Subsequent to assembly of laminae
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49163Manufacturing circuit on or in base with sintering of base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base
DE68923468T 1988-03-04 1989-03-02 Process for the production of multilayer circuits. Expired - Fee Related DE68923468T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/164,452 US4806188A (en) 1988-03-04 1988-03-04 Method for fabricating multilayer circuits

Publications (2)

Publication Number Publication Date
DE68923468D1 DE68923468D1 (en) 1995-08-24
DE68923468T2 true DE68923468T2 (en) 1996-03-21

Family

ID=22594544

Family Applications (2)

Application Number Title Priority Date Filing Date
DE68923468T Expired - Fee Related DE68923468T2 (en) 1988-03-04 1989-03-02 Process for the production of multilayer circuits.
DE68929012T Expired - Fee Related DE68929012T2 (en) 1988-03-04 1989-03-02 Process for the production of multilayer circuits

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE68929012T Expired - Fee Related DE68929012T2 (en) 1988-03-04 1989-03-02 Process for the production of multilayer circuits

Country Status (6)

Country Link
US (1) US4806188A (en)
EP (2) EP0631303B1 (en)
JP (1) JPH0634451B2 (en)
KR (1) KR920004039B1 (en)
DE (2) DE68923468T2 (en)
MY (1) MY105814A (en)

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US5006182A (en) * 1989-11-17 1991-04-09 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
US5379515A (en) * 1989-12-11 1995-01-10 Canon Kabushiki Kaisha Process for preparing electrical connecting member
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US5217550A (en) * 1990-09-28 1993-06-08 Dai Nippon Printing Co., Ltd Alignment transfer method
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US5296735A (en) * 1991-01-21 1994-03-22 Mitsubishi Denki Kabushiki Kaisha Power semiconductor module with multiple shielding layers
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US5293025A (en) * 1991-08-01 1994-03-08 E. I. Du Pont De Nemours And Company Method for forming vias in multilayer circuits
US5209798A (en) * 1991-11-22 1993-05-11 Grunman Aerospace Corporation Method of forming a precisely spaced stack of substrate layers
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US5292624A (en) * 1992-09-14 1994-03-08 International Technology Research Institute Method for forming a metallurgical interconnection layer package for a multilayer ceramic substrate
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JP3570447B2 (en) * 1994-12-21 2004-09-29 セイコーエプソン株式会社 Laminated inkjet recording head, method of manufacturing the same, and recording apparatus
JP3077543B2 (en) * 1995-01-13 2000-08-14 セイコーエプソン株式会社 Coated conductor, method of manufacturing the same, and electronic component and electronic device using the same
US5655209A (en) * 1995-03-28 1997-08-05 International Business Machines Corporation Multilayer ceramic substrates having internal capacitor, and process for producing same
US5821846A (en) * 1995-05-22 1998-10-13 Steward, Inc. High current ferrite electromagnetic interference suppressor and associated method
US5855995A (en) * 1997-02-21 1999-01-05 Medtronic, Inc. Ceramic substrate for implantable medical devices
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Also Published As

Publication number Publication date
KR890015390A (en) 1989-10-30
DE68929012T2 (en) 1999-10-21
EP0631303A2 (en) 1994-12-28
EP0331161A1 (en) 1989-09-06
EP0631303B1 (en) 1999-06-02
JPH0634451B2 (en) 1994-05-02
JPH01282890A (en) 1989-11-14
MY105814A (en) 1995-01-30
DE68923468D1 (en) 1995-08-24
EP0331161B1 (en) 1995-07-19
EP0631303A3 (en) 1995-08-16
US4806188A (en) 1989-02-21
DE68929012D1 (en) 1999-07-08
KR920004039B1 (en) 1992-05-22

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