DE60025789T2 - Logical Built-In Self Test (LBIST) Control circuits, systems and methods with automatic determination of the maximum scan chain length - Google Patents

Description

BACKGROUND THE INVENTION

The present embodiments refer to the self-examination for integrated Circuits and are directed in particular to a test control unit, the easily adaptable to several different integrated circuit designs is.

The complexity Modern integrated circuit applications have a strong need elevated, These devices thoroughly to consider, when they have been constructed. This exam will be typical at the beginning executed the life cycle of the device, wherein the device then, if they meet the test criteria successfully fulfilled, to the eventual Use in an application. To this test too facilitate, in the integrated circuit often a test circuit arrangement recorded, with the use of such circuitry usually as a self-examination ("BIST") is called. How later further explained will, contains the BIST circuitry is common numerous memory registers that are interconnected to forming something called a scan chain in the field, where each register in the chain is commonly referred to as a flip-flop is implemented. To take an exam perform, become test samples written to the scan chain registers while the state of the integrated Circuit is determined to evaluate whether the state is going out from the test samples properly reflects the appropriate operation of the integrated circuit. Furthermore, in this regard before the appearance of BIST systems as described above scan chains used um using one opposite the integrated circuit external tester to test the various test patterns to generate, then for the exam were scanned into the scan chain (s) of the integrated circuit. However, in recent years Time the BIST developed, eliminating many of today's integrated circuits on-chip BIST control units which themselves contain the test samples which greatly reduces the need for an off-chip controller is reduced. Furthermore BIST has several related technologies, such as Logic BIST or ("LBIST") for the examination of Combinatorics logic or memory BIST for testing memory circuits.

When another background is yet another recent feature in the art the LBIST systems that an architecture is added to the LBIST, which in the area is denoted by their acronym STUMPS, which the terms "self-examination under Using MISR / parallel SRSG ", where MISR is a abbreviation for multiple input signature registers and SRSG a shortcut for shift register sequence generator is. How later is further investigated a STUMPS architecture several different scan paths, which are referred to as "channels", wherein each channel in turn using multiple interconnected Memory register such as flip-flops is formed. In a sampling mode, one loads LBIST control unit the multiple channels with respective test patterns, whereupon the device is switched to its functional mode and for one or more clock cycles, which causes the state probably at many of the nodes of the circuit changes. The state changes contain changes, which affect what is in one or more of the scan channel registers is stored. Subsequently the device is reset to the sampling mode, the data being in the scan channels be pushed out and evaluated to determine if the expected Result has been generated, causing either the correct device operation approved or a problem with the device becomes visible. Except the Evaluation of the scan channel data can other device states and signals (such as over Output pins of the integrated circuit) are evaluated, to determine if the device is correct in response to the test has worked.

Although the STUMPS architecture has made considerable progress in terms of the effectiveness of the BIST and the LBIST, the inventors have recognized that it has a significant drawback. More specifically, in conjunction with the multiple scan channels in a STUMPS architecture, the fact that the channels typically have a different number of scan registers (or "cells") also arises. In the field, it is said that this number of cells forms the length of each scan channel, thus, using this terminology to the foregoing, it can be determined that the scan channels have different lengths. From this aspect, the LBIST controller must be aware of the length of the longest scan channel in any case so that it can properly load the channels with scan test patterns and properly control the LBIST test when the test patterns have been loaded. In the prior art and to accommodate this requirement, the length of the longest scan channel at the time the controller is designed and formed is hard-coded into the LBIST controller. However, when a value is hard-coded into an integrated circuit, as with other aspects of the circuit design, it limits the flexibility of the circuit with respect to that value. For example, once LBIST has been formed and hard-coded in this manner, it is limited for use with a STUMPS architecture having a longest scan channel equal to the hard-coded value. As another example, if during the development of the integrated circuit Also, care must be taken to ensure that the planned hard-coded value is also changed to achieve the correct operation of the LBIST controller.

US 4,503,537 discloses a parallel path self-test system. This system allows for self-testing of a number of chips on a substrate, with each of these logic circuit chips containing an LSSD scan path. Connected to each of the chips is a parallel random pattern generator contained on the substrate. In addition, each of the chips is connected to a multiple input signature register. Thus, the respective scan paths on the respective chips are tested in parallel. Each chip may contain a different number of shift register stages. The number of shift clock cycles required in the test mode is equal to the number of shift registers in the longest shift register train scan path on any of the logic chips. US 4,503,537 does not disclose a method for determining the number of stages in the longest scan path.

US 5,333,139 refers to Boundary Scan test circuitry and discloses a method for determining the number of integrated circuits contained in a Boundary Scan chain. For this purpose, the boundary scan chain is first put into the test mode by a test mode select signal. The circuits included in the boundary scan each have an identification register. If a circuit provides an identification number, the identification register has a length of 12 bits while the identification register is a single bit long if no identification number is supplied. A sequence of bits is shifted through the chain, with a zero output for each circuit without an identification number at the output, while the identification number is output with a prefix one when the circuit provides an identification number. Thus, the total number of circuits included in the boundary scan chain is obtained.

outgoing From the foregoing, the inventors set forth a preferred one below embodiment for LBIST STUMPS architectures reduce and treat the disadvantages set out above potentially eliminate.

SUMMARY THE INVENTION

In a preferred embodiment There is an integrated circuit that uses combinatorial circuitry includes. Furthermore, the integrated circuit comprises a plurality of scan channels. Everyone the multiple scan channels includes a number of sensing elements. For each of the multiple scan channels with one Number of scanning elements that is larger than an element includes the scan channel includes a first element in the scan channel and a last element in the scanning channel. For each of the multiple scan channels with a number of scanning elements equal to one element, the one element is both a first element and a last element Element in the scanning channel. Further, selected elements of the sensing elements coupled to the operation of the combinatorial circuitry to influence. The integrated circuit is characterized in that it further comprises a LBIST control unit associated with the first Element of each of the multiple scan channels and with the last element of each the multiple scan channels connected is. The LBIST controller includes a pattern generator to a predetermined pattern in the first element of each of the several scan channels couple. Further contains a pattern change detector, around the given pattern in the last element of each of the several scan channels and a state machine responsive to the pattern change detector the pattern generator signals a signal. The state machine includes a counter that in response to the pattern change detector the number of samples in a longest of the plurality of scan channels counts.

Further The invention provides a method for operating an integrated Circuit having the features of claim 20. Further embodiments the integrated circuit and the method are included in the dependent claims.

SUMMARY THE MULTIPLE VIEWS OF THE DRAWING

1 illustrates a circuit diagram of an integrated circuit 10 with a scanning core 12 with a number of scanning channels.

2 illustrates a block diagram of the LBIST controller 20 out 1 in that blocks are implemented to achieve the methodology of the preferred embodiment.

3 illustrates a flow chart of the preferred methodology of the LBIST controller 20 out 2 for determining the length of the longest STUMPS scan channel in the scan kernel 12 ,

DETAILED DESCRIPTION OF THE INVENTION

1 illustrates a generally with 10 designated integrated circuit product. In the preferred embodiment, the integrated circuit product 10 one of several types of circuits, such as a microprocessor, one application specific integrated circuit ("ASIC"), a digital signal processor ("DSP") or other device in which it is desired to have LBIST capability using a STUMPS or comparable architecture. It is noted that the integrated circuit product 10 may contain numerous circuits, connections, and signals, not shown, to simplify the present discussion. Instead, the integrated circuit product demonstrates 10 just enough detail to demonstrate the concept of LBIST operations as opposed to all typical operations. In any case, there is something in it 1 Shown in the LBIST area, but further improved as discussed below.

The integrated circuit 10 contains a sensing core 12 which is known in the area. The sensing core 12 contains a number of scan channels, generally designated by the abbreviation "SC" (for "scan channel"). Furthermore, the scanning kernel contains 12 exemplarily four such scan channels. To distinguish these scan channels from each other for further discussion, each is identified by combining a number with the abbreviation SC; z. For example, a first scan channel is shown as SC1, a second scan channel is shown as SC2, and so on. Each scan channel contains a number of registers or memory elements which, as previously mentioned, are typically flip flops, with the output of a flip flop in one channel connected to the SC1 Input of a next succeeding flip-flops is connected in the channel. For discussion, each memory element is in 1 identified by the abbreviation "E" (for element), where the abbreviation is followed by the channel abbreviation identifying the scan channel to which the element belongs. For example, each element shown as EC1 is one element in scan channel SC1, each element EC2 is an element in scan channel SC2, etc. Further, for each scan channel, the elements contain an index which identifies the order of the element along its channel and thereby also by examining the element Index for the last element in a channel identifies the total number of elements in a channel. For example, in scan channel SC1 it contains elements EC1 ₁ through EC1 ₅ , indicating that scan channel SC1 contains a total of five (from the index "5" in EC1 ₅ ) elements. It should also be noted in this regard that it is often the case that the scan channels do not all have the same number of memory elements. Thus, by way of example, in the scanning kernel 12 the scan channel SC1 has five memory elements, the scan channel SC2 has eight memory elements, the scan channel SC3 has six memory elements, and the scan channel SC4 has four memory elements. It should be noted that these numbers of elements are merely exemplary, while the numbers of memory elements in a scanning channel may in reality range from one to several hundred.

Before proceeding, it is noted that the scan channel elements have been simplified for clarity of illustration 1 not explicitly shown connected to other circuitry. However, the use of these elements to test such further circuitry is well known, with several different elements connected for testing to a plurality of different nodes or operational circuits. To illustrate this connection and relationship in a simplified way, it is shown that the integrated circuit 10 a combinatorial logic block 13 contains only general with the sensing core 12 Of course, multiple scan channel elements in various ways with the block 13 can be connected, so that when the integrated circuit 10 in a functional mode, the states stored by one or more of the elements are the circuitry in the block 13 while this circuitry may affect the states stored by one or more of the elements. As its name suggests, the combinatorial logic block contains 13 Combinatorics logic, and may also include other types of circuitry associated with the sense core 12 being checked. In any case, as will be seen later, each sample channel operates as a shift register in a sample mode, shifting a bit loaded into a first element in a sample channel into a next subsequent element in the channel, etc. for the remaining elements per Channel, so that there may be another check bit in each scan channel. Below is the integrated circuit 10 switched to a functional mode and operated for one or more clock cycles. During this time, the combination of the scan channel elements and the block will work 13 as a functional circuit arrangement. Further, the functional mode operation is likely to change the state of many of the nodes of the combinatorial logic block 13 , The state changes include changes that affect what is stored in one or more of the scan channel elements. Subsequently, the integrated circuit 10 is reset to the sampling mode, with the data in the scan channels being shifted out and evaluated to determine if the expected results are being generated, thereby confirming either the proper device operation or a problem with the functional circuitry (ie, the sensing core 12 and the combinatorial logic block 13 ) of the integrated circuit 10 becomes visible. In addition to evaluating the scan channel data, other device states and signals (such as via integrated circuit output pins) may be evaluated to determine if the integrated circuit 10 in reaction worked correctly on the exam.

Before proceeding, it is noted that the scan channel elements are off 1 are described above by way of example only as normal flip-flops. Thus, within the scope of the present invention, other types of scanning channel elements are also contemplated, the elements having in common the formation of scan chains as described above. For example, another sampling channel element type as known in the art is a multiplexer sampling flip-flop in which the memory device consists of a flip-flop preceded by a multiplexer. As another example, another sampling channel element type as known in the art is a clocked sampled flip-flop in which the flip-flop operates in response to two different clocks, one being a sample clock for clocking data into the flip-flop, while another is a functional clock for operating the clock Flip-flops during the functional mode. As a final example of a scan channel element, as is known in the art and can be implemented using the present teachings of the invention, there is an LSSD configuration consisting of two latches per element, the latches responding to a master clock, a Test clock and a slave clock work. Other examples may be ascertained by those skilled in the art.

Turning now to additional aspects of the integrated circuit as known in the art 10 It also contains additional BIST-related circuits, referred to as an embodiment as a pseudo-random pattern generator block ("PRPG" block). 14 , as an XOR gate block 16 and as a multiple input signature register block ("MISR" block) 18 are shown. However, in alternative embodiments, each of these blocks may be replaced by other BIST executing circuits. In any case, each of the blocks 14 . 16 and 18 through a LBIST control unit 20 controlled, with the LBIST control unit 20 As will be described in more detail below, not only does it include circuitry and methodology for controlling these prior art devices, but it also operates in a preferred inventive manner. To the similarities and differences of the integrated circuit 10 To further illustrate with the prior art, first follows a discussion of the blocks 14 . 16 and 18 in relation to the prior art, followed by the remaining discussion, in which the inventive preferred embodiment is explained in detail.

The LBIST control unit 20 delivers one or more seeds to the PRPG block 14 , and the PRPG block 14 In response, outputs parallel streams of pseudorandom sequences of bits. Finally, those from the PRPG block 14 output bits are translated into bits in the scan channels of the scan kernel 12 be used. More specifically, these bit sequences are from the PRPG block 14 to the XOR gate block 16 which further manipulates these bits and then, as will be described in more detail below, applies them to the scan channels of the scan kernel 12 supplies.

The XOR gate block 16 is included to account for a portion of the correlation between adjacent bitstreams from the PRPG block 14 to remove. If adjacent streams of bits from the PRPG block 14 More specifically, those skilled in the art could be more specific about the pseudo-random operation of the PRPG block 14 identify a significant correlation level between the streams. Accordingly, the XOR gate block decorrels 16 these streams using a set of XOR gates (sometimes referred to in the art as a cloud of XOR gates or as a phase shifter). In addition, the XOR gate block contains 16 often an operation of shifting the bitstreams by a number of shifts, which is the maximum length of the scan channels in the scan kernel 12 exceeds. Finally, it is noted that the XOR gate block 16 is also operable to allow a level of fanouts if the number of scan channels equals the number of blocks through the PRPG block 14 exceeds provided outputs. In any case, these are the outputs of the XOR gate block 16 (via multiplexers discussed later) to the inputs of the scan channels in the scan core 12 coupled.

The MISR block 18 provides an additional level of efficiency for processing the output of the scan channels. First, it will be remembered from the earlier discussion that the outputs of the scan channels are examined to determine if the device (here the integrated circuit 10 ) has worked correctly from an input scan test. Further, the MISR block compresses 18 in this regard, the data it receives as outputs from each of the scan channels. More specifically, the compression methodology generates what is referred to as a "signature" that represents the data output from the scan channels. This edition is in 1 illustrated in the way that they are generally external to the integrated circuit 10 The illustration is intended to show in this way that the signatures can then be examined to determine the result of the test. It is also recalled in this regard that 1 is simplified in various respects, so that it does not illustrate other circuits and the like that are included in the integrated circuit 10 could be included. Such a further circuit may refer to a different scan test type common in the art fig. is referred to as a boundary scan test and may also include an IEEE 1149.1 Boundary Scan control unit. This aspect is mentioned here because of the MISR block 18 issued signatures can be used in conjunction with this test and this Boundary Scan control unit.

The discussion now turns the remaining in 1 in terms of the integrated circuit 10 to illustrated aspects, which aspects are related to the preferred embodiment of the invention and shown to work in a particular relationship with the elements already discussed. These additional aspects relate to the paths for data input and output to the sense core 12 and also to the operation (and circuitry for performing this operation) of the LBIST controller 20 , The following describes each of these aspects.

In terms of data input to the scanning core 12 are between the outputs of the XOR gate block 16 and the respective inputs coupled to the scan channels are a set of multiplexers, each partially identified by the abbreviation "M"; hence there is for each output of the XOR gate block 16 and for each input to a scan channel, a corresponding multiplexer having an input connected to receive data from the XOR gate block 16 and with an output connected to a scan channel input. For reference purposes, each multiplexer identifier is also followed by a number that is the same as the number identifier used by its corresponding scan channel. For example, M1 corresponds to the multiplexer the scan channel SC1, the multiplexer M2 corresponds to scan channel SC2, etc. In addition to the previously described compounds having each multiplexer M1 to M4 a second input which is coupled so that it receives data by a bus DB _1, wherein the LBIST control unit 20 this data to the data bus DB ₁ as described later. There is also the LBIST control unit 20 a 4-bit control signal, here referred to as MUX CONTROL, which signal is coupled to a control bus CB which includes four control conductors for connecting each of the four bits of MUX CONTROL to a respective one of the control inputs of the multiplexers M1 to M4. Based on these connections and according to a preferred methodology described in detail later, the LBIST controller reports 20 the MUX CONTROL in different states, whereby the multiplexers M1 to M4 are controlled so that at certain times all the multiplexers M1 to M4 the data from the XOR gate block 16 passed to the scan channels, while at other times all multiplexers M1 to M4 pass the data from the data bus DB ₁ to the scan channels. It is noted that, because of this preferred approach, the control bus CB could actually alternatively be an initiator bus giving the same state to each of the multiplexers M1 to M4, causing each to operate in the same way as the others.

In terms of the sensing core 12 output data is noted that each scan channel output except that it is with the MISR block 18 is connected, further connected to a data bus DB ₂ . The data bus DB ₂ is connected to the LBIST control unit 20 connected. Thus, and for reasons more particularly described below, the data output is by the sense core 12 on request for processing by the LBIST control unit 20 available.

2 illustrates a block diagram of the LBIST controller 20 out 1 , but note that the blocks are off 2 only those relating to the implementation of the methodology of the preferred embodiment. Thus, the LBIST control unit 20 Many other aspects, such as the control features required to provide the control signals to the PRPG block, are included 14 and to the MISR block 18 to deliver, since these compounds in 1 are shown. However, these additional aspects are neither illustrated nor described to simplify the illustration and the discussion that remains. Also, as an introduction, note that the following 3 the preferred operation of the blocks 2 however, those skilled in the art will be able to identify numerous alternatives for implementing each such block from this discussion. Further, the blocks in this regard are shown only as logical illustrations of the functionality, thus the actual hardware / software implementing this functionality may be such that the blocks are unified or further subdivided according to a given implementation.

Looking at the in 2 Blocks shown contains the LBIST control unit 20 a state machine 22 generally related to as below 3 controls the procedure described in more detail. It also contains the state machine 22 a counter 23 which is shown monitoring a count referred to herein as SCAN_COUNT. As will be described in more detail below, SCAN_COUNT finally identifies, as the goal of the preferred embodiment is, the length of the longest scan channel in the scan kernel 12 , The state machine 22 provides as an output the signals MUX_CONTROL for controlling the bus CB which, as described above, controls the multiplexers M1 to M4 in such a way that either data from the XOR gate block 16 or data from the data bus DB ₁ are coupled to the scan channels. As further described below, the state machine has 22 a second output coupled to send a PATTERN_CONTROL signal to a pattern generator block 24 supplies.

The pattern generator block 24 operates to output one of two different patterns of bits to the N (eg, N = 4) lines of the DB ₁ database. In the preferred embodiment, a first of the two patterns is one in which all bits are in a first logic state (e.g., all binary zeroes) while the second of the two patterns is one in which all bits are in a second logic state. which is complementary to the first logic state (eg, all are binary ones). Finally, the selection of which of the two patterns is output to the data bus DB ₁ is made in response to the pattern generator block 24 from the state machine 22 received signal PATTERN_CONTROL.

It also contains the LBIST control unit 20 a pattern change detector block 26 which receives the bits output by the scan channels connected as to the data bus DB ₂ . As will be described in more detail below, the pattern change detector block examines 26 these bits to detect a particular type of change in the received bits. When this change is detected, the pattern change detector block reports 26 to the state machine 22 a CHANGE_DETECTED signal that advances the methodology described in more detail below. The particular through the block 26 Implemented pattern capture type is also described below, and in light of this discussion, a preferred circuit implementation for detecting such a pattern is also discussed.

3 illustrates a flowchart of a preferred method 30 the operation of the LBIST control unit 20 for determining the length of the longest STUMPS scan channel in the scan kernel 12 the integrated circuit 10 , As will be apparent from the remaining discussion, the procedure will proceed 30 generally by the state machine 22 with additional functionality from the other blocks in 2 controlled. The procedure 30 starts with one step 32 in which the state machine sets the PATTERN_CONTROL in a first state to the pattern generator block 24 reports. The pattern generator block 24 In response to the signal PATTERN_CONTROL, it begins to output its first of two patterns of bits, assuming, for example, that all of this pattern consists of binary zeroes. These zeros are thus connected to the data bus DB ₁ . At the same time the state machine reports 22 the signal MUX_CONTROL to a first state, so that each of the multiplexers M1 to M4 connects the zeros of the data bus DB ₁ with the inputs of the scan channels SC1 to SC4. From the foregoing, it will be understood that a pattern of all binary zeros is shifted into the first element of each of the scan paths SC1 to SC4 (i.e., elements EC1 ₁ , EC2 ₁ , EC3 _1, and EC4 _1, respectively). In addition, the state machine stops 22 during the step 32 for an integer number N of clock cycles, maintain the same control so that an integer number N of cases of the first pattern is connected to the scan channels, causing each preceding case of the first pattern to be shifted in the direction of a subsequent element in each scan channel , In the preferred embodiment, the integer N is chosen to be a number sufficiently larger than that which could realistically be expected as the length of the longest scan channel. For example, it is recalled that it has previously been mentioned that scan channels typically consist of one to several hundred elements. Accordingly, starting from these numbers, N is preferably set to a larger number, so that it is assumed by way of example that N is equal to 1000. Accordingly, the completion of step 32 for 1000 clock cycles, a pattern of all zeros through the elements of all scan channels in the scan kernel 12 pushed. Since N is sufficiently larger than the longest scan channel in the scan kernel 12 In addition, save by completing step 32 all elements in all scan channels have a value of binary zero. The following is the procedure 30 in step 34 continued.

In step 34 clears the state machine 22 the value of SCAN_COUNT in the counter 23 , In addition, the state machine controls 22 the pattern change detector block 26 such that it starts to evaluate the pattern received by the data bus DB ₂ , ie the pattern output by all the scan channels SC1 to SC4. In particular, and for reasons that will become clearer below, the pattern change detector block begins 26 to evaluate the data on the data bus DB ₂ to detect when they represent a second pattern of bits different from that in step 32 differentiates into the first pattern loaded in the scan channels. In the preferred embodiment, the second pattern consists of bits that are complementary to the first pattern, although, as discussed later, alternative approaches are considered. In any case, the pattern detector block starts 26 for the present example, in which the in step 32 the first patterns loaded into the scan channels were all binary zeros, then to evaluate the data on the data bus DB ₂ to detect when that data represents a second pattern all of binary zeroes. In this regard, it is noted that a logic circuit implementation achieving this detection is a multiple Gates AND gates (as formed using multiple AND gates), the output of this gate sending the signal CHANGE_DETECTED to the state machine 22 supplies. As is known in the art, such a logic gate only changes its output from a logic low to a logic high when all inputs to the gate are logic highs. Thus, the state of the CHANGE_DETECTED signal transitions and notifies the state machine 22 about the change when the pattern change detector 26 detects that all outputs of the scan channels SC1 to SC4 are high. It is further noted that the use of an AND gate is merely a logical illustration, whereas a more practical implementation may involve the use of a logical NAND gate, since the NAND logic gate is constructed using fewer transistors than its AND gates. Counterpart can be constructed.

In step 36 reports the state machine 22 the PATTERN_CONTROL in a second state to the pattern generator block 24 , The pattern generator block 24 starts outputting its second of the two patterns of bits in response to the signal PATTERN_CONTROL; as above with respect to step 34 has been introduced, it is recalled that in one embodiment the second pattern consists of bits that are complementary to the first pattern, so that this second pattern all consists of binary ones, starting from the current example. These ones are thus connected to the data bus DB ₁ and thus transferred via the multiplexers M1 to M4 to the first element of each of the scan paths SC1 to SC4 (ie to the elements EC1 ₁ to EC4 ₁ ). In addition, the state machine increments 22 in step 36 for this first set of binary ones connected to the scan channels, the value SCAN_COUNT in the counter 23 , Assuming that at this point only a set of binary ones has been connected to the scan chains, it is noted that the value of SCAN_COUNT is now equal to one. The following is the procedure 30 with step 38 continued.

step 38 represents the determination by the pattern change detector 26 whether the output of the scan channels has been completely changed from the first pattern (eg, binary zeroes) to the second pattern (eg, binary ones). If this change did not occur, the procedure returns 30 from step 38 to step 36 back; on the other hand, if the pattern change has changed from binary zeros to binary ones, then the method becomes 30 from step 38 to step 40 continued. Each of these alternatives will be discussed separately below.

An example is illustrated in which the method 38 by applying the present application of the method 30 on the in 2 illustrated scan channels the process of step 38 to step 36 returns. In this regard, it is noted that in each case of step 38 the in step 38 evaluated data with the pattern change detector block 26 coupled data, ie the data values stored in the last element of each scan channel (ie in elements EC1 ₅ , EC2 ₈ , EC3 ₆ and EC4 ₄ ). Because these elements were previously (from step 32 ) have been loaded with binary zeroes, and since only a set of binary ones have been shunted into the elements EC1 ₁ , EC2 ₁ , EC3 ₁ and EC4 ₁ , the values in elements EC1 ₅ , EC2 ₈ , EC3 ₆ and EC4 _{4 are} all As a result, the CHANGE_DETECTED signal at this point does not indicate that the pattern change detector block 26 received patterns are all binary ones. As a result, the procedure of the method returns 30 to step 36 back.

When the step 36 is reached a subsequent time, he performs the same operation as previously described. To understand the result of this operation, however, the discussion of the example of the four scan channels in the scan kernel becomes 12 out 2 continued. Specifically causes step 36 at this point in the example, a second set of binary ones is sampled into the first elements of the scan channels SC1 through SC4, shifting the previously existing values in the scan channels. As a result, this second set of binary ones shifts the first set of binary ones (which in the previous instance of step 36 sampled into the first elements of the scan channels) so as to advance to the second element in each of the scan channels. Thus, at this point, both the first and second elements in each of the scan channels SC1 to SC4 store the values of binary ones, while all other scan channel elements store binary zeros. In addition, SCAN_COUNT is incremented again and thus now stores a value of two. As described above, the method becomes 30 with step 38 continued when the step 36 is completed.

The step 38 operates as described above, wherein the pattern change detector 26 determines whether the last element in each of the scan channels stores a value from the second pattern (eg, a logical one). As noted in the previous paragraph, however, at the current point in the example, each of these last elements stores a binary zero value. Thus, the state of CHANGE_DETECTED does not change, with the procedure returning to step 36 returns.

It will be apparent to those skilled in the art from the above that the steps 36 and 38 many more times be repeated. It is further noted in this regard that the value of SCAN_COUNT is equal to four when step 36 has occurred four times. In addition, at this time, a binary one has reached the last element in the scan channel SC4, ie the element EC4 ₄ . However, also at this time, the element at the end of scan channel SC1, the four elements at the end of scan channel SC2 and the last two elements at the end of scan channel SC3 further store the binary zero values. As a result, the pattern change detector block 26 if after the fourth occurrence of the step 36 the step 38 is reached, three inputs of a binary zero and a binary one input, causing no change in CHANGE_DETECTED. As a result, the process returns to step 36 back.

Further, an understanding of the present embodiment is obtained by the fifth, sixth, and seventh occurrences of the step 36 in the present example. When the step 36 occurs a fifth time, store all elements of the scan channels SC1 and SC4 binary ones. In contrast, the last three elements of scan channel SC2 (ie EC2 ₆ , EC2 ₇ and EC2 ₈ ) and the last element of scan channel SC3 (ie EC3 ₆ ) store binary zeroes. Thus, the process returns 30 to step 36 back. When the step 36 For a sixth time, all elements of the scan channels SC1 and SC4 continue to store binary ones, while at that point all elements of the scan channel SC3 also store binary ones. In contrast, the last two elements of scan channel SC2 (ie EC2 ₇ and EC2 ₈ ) continue to store binary zeros. Thus, the process returns 30 for a seventh occurrence of this step again to step 36 which causes a binary one to reach the penultimate element of the scan channel SC2, the method 30 for an eighth appearance of this step again to step 36 returns.

The eighth appearance of step 36 again passes a set of binary ones to the inputs of all scan channels, it being clear from the preceding states of these elements that this eighth occurrence results in a binary one reaching the last element of scan channel SC2, ie element EC2 ₈ . Further, the previous appearances of the step 36 also causes the elements to also store all other scan channels SC1, SC3 and SC4 binary ones. Thus, at this point, all four outputs of the sample kernel pass 12 Values of a binary one on the data bus DB ₂ and thus on the pattern change detector 26 , The following is the procedure 30 once again with step 38 continued.

If, in the present example and after eight appearances of step 36, step 38 is reached, the value of SCAN_COUNT is equal to eight, and the data bus DB _{2 is} all binary ones to the pattern change detector 26 passes. The pattern change detector 26 detects, in response to the full set of binary ones, that the second pattern has been detected. It will be recalled that in the present example, this detection occurs because of the logical AND operation that causes a positive transition in the CHANGE_DETECTED signal in response to the input of all logic highs. This signal transition indicates that from this time all the last elements in the scan channels output the second pattern, so that the method 30 in step 40 will continue.

step 40 represents the completion of the procedure 30 , At this point, the value of SCAN_COUNT is equal to the length of the longest scan channel in the scan kernel 12 , Thus, it is noted that the method 30 by step 40 has electronically determined the length of the longest scan channel. As a result, the value can be used in various ways, as the person skilled in the art wishes. For example, this value is required for additional BIST operations, and in the preferred embodiment is actually used to define how many times the scan verify data during the scan mode by successive elements in the scan kernel 12 that is, the number of shifts, starting from the first pushing in of the Abtastprüfmusters in the first scanning element in each channel and then continuing with the successive shifts on successive elements of the scan channels. By those skilled in the art, additional uses of the length of the longest scan channel can be determined. In any case, it is clear that the length of the longest scanning channel by step 40 automatically determined without him in the LBIST control unit 22 needs to be hard-coded or otherwise provided in solid form for this device. Although this in 3 is not shown, it is finally noted that the MUX_CONTROL is switched to a second state, so that the multiplexers M1 to M4 data from the XOR gate block 16 to the sensing core 12 pass when the longest scanning channel in the scanning core 12 has been determined and it is desired to perform LBIST operations.

From the above, it is clear that the above embodiments provide an improved circuit system and circuit methodology by which an integrated circuit can automatically determine the longest channel in its sensing core. Such access has, in particular in contrast to the disadvantages of the prior art access for hard coding this Length parameters in the integrated circuit, numerous advantages. As an advantage, it should be noted that while an integrated circuit design is changed, the present system may be early integrated with the device design without the need to later redesign or change the design based on a pre-existing hard-coded length parameter , As another advantage, the process can 30 may be used in various LBIST controllers for various circuit designs without requiring any change in these designs based on the different maximum length scan channel in these designs. Yet further advantages may be ascertained by those skilled in the art. Indeed, yet another advantage is that, although the present embodiments have been described in detail, various substitutions, alterations, or alterations could be made to the descriptions set forth above without departing from the scope of the invention as defined by the claims. Although z. B. the method 30 have shown different separate steps, some of these steps can be combined or further subdivided into additional sub-steps. While the preceding example illustrates a case in which the in step 32 used first patterns of all zeros while in step 36 (and in repeated appearances of the step 36 As a further example, if the second patterns used are all ones, these patterns could be interchanged as a further example, causing the step 32 a pattern all of ones used during the step 36 a pattern is used all zeros. As can be determined by those skilled in the art, the particular circuitry would be for detecting the latter pattern in the pattern change detector block 26 course, in this latter case, require a modification. Although the preferred embodiment uses a first and a second pattern, which are all the same binary state, as yet another example, a more complicated implementation may involve the use of other patterns and require a more complicated detection circuit to determine a time when the second pattern completely all scan channels in the scan core 12 has gone through. As yet another example, various changes may be made to the circuits shown to accomplish the BIST operations - e.g. B. instead of the PRPG block 14 another type of pattern generator may be used and / or instead of the MISR 18 another type of response analysis circuit could be used. Thus, these and other examples further illustrate the scope of the invention as defined by the following claims.

Claims (23)

Integrated circuit, comprising: combinatorial circuitry ( 13 ); a plurality of scan channels (SC1-SC4); wherein each of the plurality of scan channels (SC1-SC4) comprises a number of scan elements (EC1 ₁ -EC4 ₅ ); wherein for each of the plurality of scan channels (SC1-SC4) having a number of scan elements (EC1 ₁ -EC4 ₄ ) larger than an element, the scan channel comprises a first element in the scan channel and a last element in the scan channel; wherein for each of the scan channels (SC1-SC4) having a number of scan elements (EC1 ₁ -EC4 ₄ ) equal to one element, that one element is both a first element and a last element in the scan channel; and wherein selected elements of the sensing elements (EC1 ₁ -EC4 ₄ ) are coupled to perform the operation of the combinatorial circuitry (12). 13 ) to influence; characterized in that the integrated circuit further comprises: an LBIST control unit ( 20 ) connected to the first element (EC1 ₁ , EC2 ₁ , EC3 ₁ , EC4 ₁ ) of each of the plurality of scan channels and to the last element (EC1 ₅ , EC2 ₈ , EC3 ₆ , EC4 ₄ ) of each of the plurality of scan channels the LBIST control unit ( 20 ) comprises a pattern generator ( 24 ) to inject a predetermined pattern into the first element of each of the plurality of scan channels; a pattern change detector ( 26 ) to detect the predetermined pattern in the last element of each of the plurality of scan channels; and a state machine ( 22 ) in response to the pattern change detector ( 26 ) the pattern generator ( 24 ) reports a signal, the state machine ( 22 ) a counter ( 23 ) in response to the pattern change detector ( 26 ) is incremented to count the number of samples in the longest of the plurality of scan channels (SC1-SC4). The integrated circuit of claim 1, further a circuit arrangement comprises before the operation of the circuit arrangement for coupling a predetermined pattern into a first element each the multiple scan channels all values in all elements of each of the multiple scan channels to one set predetermined state. Integrated circuit according to claim 2: in the the predetermined state comprises a first binary state; and at the predetermined pattern comprises a second binary state that belongs to the first binary State complementary is. An integrated circuit according to claim 3, wherein the predetermined state is a binary zero includes; and wherein the predetermined pattern comprises a binary one. An integrated circuit according to claim 4, wherein the pattern change detector ( 26 ) comprises circuitry for performing a logical AND operation on values output from the last sampling element (EC 1 ₅ , EC 2 ₈ , EC 3 ₆ , EC _{4 4} ) in each of the plurality of sampling channels (SC1, SC2, SC3, SC4) , The integrated circuit of claim 5, further comprising: one Pattern generator to generate a pattern of bits; and one A response analysis circuit coupled to receive a bit state of each receives the last elements of the scan channels. An integrated circuit according to claim 6, wherein the pattern generator generates a pseudo-random pattern generator ( 14 ) to generate a pseudorandom pattern of bits; and further comprising: a gate circuit ( 16 ) generated with the pseudo-random pattern generator ( 14 ) to decorrelate the pseudorandom pattern of bits to provide an output set of check bits; and circuitry (M1, M2, M3, M4) for coupling the output set of check bits to corresponding first elements of the scan channels during a test mode. An integrated circuit according to claim 7, wherein the Circuit arrangement (M1, M2, M3, M4) for coupling the output quantity of check bits with corresponding first elements of the scan channels during one test mode to the predetermined number of samples in the longest of the plurality scan channels responds. An integrated circuit according to claim 6, wherein the response analysis circuit comprises a multiple input signature register (12). 18 ). The integrated circuit of claim 3, further comprising: one Pattern generator to generate a pattern of bits; and one A response analysis circuit coupled to receive a bit state of each receives the last elements of the scan channels. An integrated circuit according to claim 10, wherein the pattern generator generates a pseudo-random pattern generator ( 14 ) to generate a pseudorandom pattern of bits; and further comprising a gate circuit ( 16 ) generated with the pseudo-random pattern generator ( 14 ) and decorrelates the pseudorandom pattern of bits to provide an output set of check bits; and circuitry (M1, M2, M3, M4) for coupling the output set of check bits to corresponding first elements of the scan channels during a test mode. An integrated circuit according to claim 10, wherein the response analysis circuit comprises a multiple input signature register (10). 18 ). The integrated circuit of claim 1, further comprising circuitry for setting all values in all elements of each of the plurality of scan channels to a predetermined state prior to the operation of the circuitry to couple a predetermined pattern into a first element of each of the plurality of scan channels; wherein the number of sampling elements (EC1 ₁ -EC4 ₄ ) in the longest of the plurality of sampling channels consists of an estimated integer number M of sampling elements; wherein said means for setting all values comprises circuitry for successively sampling the predetermined state into the first elements of the scan channels an integer number of times X times; and where X is greater than M. Integrated circuit according to claim 13, at the predetermined state comprises a binary zero; and at the predetermined pattern comprises a binary one. An integrated circuit according to claim 14, wherein the pattern change detector ( 26 ) comprises circuitry for performing a logical AND operation on values output from the last sampling element (EC1 ₅ , EC2 ₈ , EC3 ₆ , EC4 ₄ ) in each of the plurality of sampling channels (SC1, SC2, SC3, SC4). The integrated circuit of claim 15, further comprising one Pattern generator to generate a pattern of bits; and one Response analysis circuit coupled to have a bit state from each of the last elements of the scan channels. An integrated circuit according to claim 16, wherein the pattern generator generates a pseudo-random pattern generator (16). 14 ) to generate a pseudorandom pattern of bits; and further comprising: a gate circuit ( 16 ) generated with the pseudo-random pattern generator ( 14 ) is coupled and the Pseudo-random pattern of bits decorrelated to provide an output set of check bits; and circuitry (M1, M2, M3, M4) for coupling the output set of check bits to corresponding first elements of the scan channels during a test mode. An integrated circuit according to claim 16, wherein the response analysis circuit comprises a multiple input signature register (16). 18 ). An integrated circuit according to claim 1, wherein selected sensing elements are coupled so that they are the operation of the circuit additionally affect the combinatorial circuitry. A method of operating an integrated circuit having a plurality of scanning channels (SC1-SC4), each of which includes a number of sensing elements (EC1 ₁ -EC4 ₄ ), comprising the steps of: a) coupling a predetermined pattern into a first element (EC1 ₁ -EC4 ₁ ) each of the plurality of scan channels (SC1-SC4); wherein for each of the plurality of scan channels (SC1-SC4) having a number of scan elements larger than an element, the scan channel comprises a first element in the scan channel and a last element in the scan channel; wherein for each of the plurality of scan channels having a number of scan elements equal to one element, that one element is both the first element and the last element in the scan channel; characterized in that the method further comprises the steps of: b) incrementing a counter ( 23 ); c) detecting the pattern in the last element (EC1 ₅ , EC2 ₈ , EC3 ₆ , EC4 ₄ ) of each of the plurality of scan channels; d) determining whether the detected patterns are the predetermined pattern and repeating steps a) to d) if they are not the predetermined pattern; e) determining the number of sampling elements in the longest of the plurality of sampling channels by a counter value of the counter ( 23 ). The method of claim 20, further comprising the step of setting all the values in the first element (EC1 ₁ -EC4 ₁ ) of each of the plurality of scan channels (SC1-SC4) prior to the step of coupling a predetermined pattern to a first element of each of the plurality of scan channels includes a predetermined state. The method of claim 21, further comprising the step of, during a test mode, coupling an output set of check bits to corresponding first elements (EC1 ₁ -EC4 ₁ ) of the scan channels in response to the predetermined number of samples in the longest of the plurality of scan channels. The method of claim 22, further comprising the step includes, during which a sampling mode in response to the predetermined number of sampling elements in the longest the multiple scan channels, which is equal to an integer N, an initial set of check bits corresponding first elements of the scan channels N times is coupled.