DE60025067D1 - Cmos Halbleiter integrierte Schaltung - Google Patents

Cmos Halbleiter integrierte Schaltung

Info

Publication number
DE60025067D1
DE60025067D1 DE60025067T DE60025067T DE60025067D1 DE 60025067 D1 DE60025067 D1 DE 60025067D1 DE 60025067 T DE60025067 T DE 60025067T DE 60025067 T DE60025067 T DE 60025067T DE 60025067 D1 DE60025067 D1 DE 60025067D1
Authority
DE
Germany
Prior art keywords
integrated circuit
semiconductor integrated
cmos semiconductor
cmos
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60025067T
Other languages
English (en)
Other versions
DE60025067T2 (de
Inventor
Heiji Ikoma
Yoshitsugu Inagaki
Hiroyuki Konishi
Koji Oka
Akira Matsuzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE60025067D1 publication Critical patent/DE60025067D1/de
Publication of DE60025067T2 publication Critical patent/DE60025067T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE60025067T 1999-05-06 2000-05-03 Cmos Halbleiter integrierte Schaltung Expired - Lifetime DE60025067T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP12578199 1999-05-06
JP12578199 1999-05-06
JP25524899 1999-09-09
JP25524899 1999-09-09

Publications (2)

Publication Number Publication Date
DE60025067D1 true DE60025067D1 (de) 2006-02-02
DE60025067T2 DE60025067T2 (de) 2006-06-22

Family

ID=26462109

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60025067T Expired - Lifetime DE60025067T2 (de) 1999-05-06 2000-05-03 Cmos Halbleiter integrierte Schaltung

Country Status (6)

Country Link
US (1) US6310492B1 (de)
EP (1) EP1050968B1 (de)
KR (1) KR100626931B1 (de)
CN (1) CN1173405C (de)
DE (1) DE60025067T2 (de)
TW (1) TW465045B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3609003B2 (ja) 2000-05-02 2005-01-12 シャープ株式会社 Ｃｍｏｓ半導体集積回路
US6940304B2 (en) * 2001-03-14 2005-09-06 Micron Technology, Inc. Adaptive threshold logic circuit
US6559704B1 (en) * 2001-06-19 2003-05-06 Lsi Logic Corporation Inverting level shifter with start-up circuit
US6768339B2 (en) * 2002-07-12 2004-07-27 Lsi Logic Corporation Five volt tolerant input scheme using a switched CMOS pass gate
KR100521370B1 (ko) * 2003-01-13 2005-10-12 삼성전자주식회사 파워 검출부를 구비하여 누설 전류 경로를 차단하는 레벨쉬프터
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US7102380B2 (en) * 2004-07-07 2006-09-05 Kao Richard F C High speed integrated circuit
US7679396B1 (en) 2004-07-07 2010-03-16 Kao Richard F C High speed integrated circuit
US7378896B2 (en) * 2005-05-13 2008-05-27 O2Micro International Ltd. Single pin for multiple functional control purposes
JP4638802B2 (ja) * 2005-10-27 2011-02-23 トヨタ自動車株式会社 離型剤又は鋳造方法
JP4772480B2 (ja) * 2005-11-30 2011-09-14 株式会社東芝 半導体集積装置
US7394291B2 (en) * 2005-12-26 2008-07-01 Stmicroelectronics Pvt. Ltd. High voltage tolerant output buffer
US7492207B2 (en) * 2006-12-08 2009-02-17 Infineon Technologies Ag Transistor switch
WO2008117247A2 (en) 2007-03-28 2008-10-02 Nxp B.V. Electronic device with a high voltage tolerant unit
US7583126B2 (en) * 2007-05-24 2009-09-01 Nvidia Corporation Apparatus and method for preventing current leakage when a low voltage domain is powered down
US7745890B2 (en) * 2007-09-28 2010-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid metal fully silicided (FUSI) gate
KR100894106B1 (ko) * 2008-03-17 2009-04-20 주식회사 하이닉스반도체 전원전압 레벨다운 회로
US7973569B1 (en) * 2010-03-17 2011-07-05 Microchip Technology Incorporated Offset calibration and precision hysteresis for a rail-rail comparator with large dynamic range
US9933477B2 (en) * 2014-03-28 2018-04-03 Intel Corporation Semiconductor chip having transistor degradation reversal mechanism
CN104716940B (zh) * 2014-12-30 2017-07-18 宁波大学 一种晶体管级低功耗cmos and/xor门电路
KR101689159B1 (ko) 2015-07-10 2016-12-23 울산과학기술원 3진수 논리회로
CN108667449A (zh) * 2017-03-27 2018-10-16 中芯国际集成电路制造(上海)有限公司 电子系统及其上、下电状态检测电路
CN109150148A (zh) * 2017-06-28 2019-01-04 华大半导体有限公司 低漏电流模拟开关电路
US10715115B2 (en) * 2018-09-28 2020-07-14 Qualcomm Incorporated Circuits and methods for preventing bias temperature instability
TWI730822B (zh) * 2020-06-22 2021-06-11 瑞昱半導體股份有限公司 應用在多個電源域的電路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5004936A (en) 1989-03-31 1991-04-02 Texas Instruments Incorporated Non-loading output driver circuit
JP3253389B2 (ja) * 1992-03-31 2002-02-04 株式会社東芝 半導体集積回路装置
US5338978A (en) * 1993-02-10 1994-08-16 National Semiconductor Corporation Full swing power down buffer circuit with multiple power supply isolation
US5341034A (en) * 1993-02-11 1994-08-23 Benchmarq Microelectronics, Inc. Backup battery power controller having channel regions of transistors being biased by power supply or battery
US5644266A (en) 1995-11-13 1997-07-01 Chen; Ming-Jer Dynamic threshold voltage scheme for low voltage CMOS inverter
JPH09172362A (ja) 1995-12-20 1997-06-30 Seiko Epson Corp 出力バッファ回路
WO1997032399A1 (fr) 1996-02-29 1997-09-04 Seiko Epson Corporation Dispositif de circuit integre a semi-conducteur
US5844425A (en) * 1996-07-19 1998-12-01 Quality Semiconductor, Inc. CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations
JP3732914B2 (ja) * 1997-02-28 2006-01-11 株式会社ルネサステクノロジ 半導体装置
KR100268923B1 (ko) * 1997-09-29 2000-10-16 김영환 반도체소자의이중게이트형성방법
US5926056A (en) * 1998-01-12 1999-07-20 Lucent Technologies Inc. Voltage tolerant output buffer

Also Published As

Publication number Publication date
US6310492B1 (en) 2001-10-30
KR100626931B1 (ko) 2006-09-20
EP1050968B1 (de) 2005-12-28
KR20000077151A (ko) 2000-12-26
TW465045B (en) 2001-11-21
DE60025067T2 (de) 2006-06-22
CN1273437A (zh) 2000-11-15
CN1173405C (zh) 2004-10-27
EP1050968A1 (de) 2000-11-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP