DE59510258D1 - Integrated semiconductor memory device with redundancy circuitry - Google Patents

Integrated semiconductor memory device with redundancy circuitry

Info

Publication number
DE59510258D1
DE59510258D1 DE59510258T DE59510258T DE59510258D1 DE 59510258 D1 DE59510258 D1 DE 59510258D1 DE 59510258 T DE59510258 T DE 59510258T DE 59510258 T DE59510258 T DE 59510258T DE 59510258 D1 DE59510258 D1 DE 59510258D1
Authority
DE
Germany
Prior art keywords
memory cell
memory device
semiconductor memory
integrated semiconductor
redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE59510258T
Other languages
German (de)
Inventor
Johann Rieger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE59510258D1 publication Critical patent/DE59510258D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage

Abstract

The memory device has a semiconductor substrate incorporating memory cells arranged in blocks and redundant memory cells (6) arranged in a redundant memory cell field (7), addressed by a redundancy circuit (2). The latter has a redundancy selection circuit (15), for selecting a redundant memory cell for replacement of a defective memory cell within one of the memory cell blocks. The redundancy selection circuit is positioned in the semiconductor substrate which is spatially separated from each individual memory cell block.
DE59510258T 1995-08-09 1995-08-09 Integrated semiconductor memory device with redundancy circuitry Expired - Lifetime DE59510258D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95112549A EP0758112B1 (en) 1995-08-09 1995-08-09 Integrated semiconductor memory device having redundancy circuit arrangement

Publications (1)

Publication Number Publication Date
DE59510258D1 true DE59510258D1 (en) 2002-08-08

Family

ID=8219509

Family Applications (1)

Application Number Title Priority Date Filing Date
DE59510258T Expired - Lifetime DE59510258D1 (en) 1995-08-09 1995-08-09 Integrated semiconductor memory device with redundancy circuitry

Country Status (7)

Country Link
US (1) US5675543A (en)
EP (1) EP0758112B1 (en)
JP (1) JPH0955095A (en)
KR (1) KR100409114B1 (en)
AT (1) ATE220228T1 (en)
DE (1) DE59510258D1 (en)
TW (1) TW364114B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5996096A (en) * 1996-11-15 1999-11-30 International Business Machines Corporation Dynamic redundancy for random access memory assemblies
US6021512A (en) * 1996-11-27 2000-02-01 International Business Machines Corporation Data processing system having memory sub-array redundancy and method therefor
US5996106A (en) 1997-02-04 1999-11-30 Micron Technology, Inc. Multi bank test mode for memory devices
CA2202692C (en) * 1997-04-14 2006-06-13 Mosaid Technologies Incorporated Column redundancy in semiconductor memories
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
US5835431A (en) * 1997-09-05 1998-11-10 Integrated Device Technology, Inc. Method and apparatus for wafer test of redundant circuitry
US5970013A (en) * 1998-02-26 1999-10-19 Lucent Technologies Inc. Adaptive addressable circuit redundancy method and apparatus with broadcast write
US6011733A (en) * 1998-02-26 2000-01-04 Lucent Technologies Inc. Adaptive addressable circuit redundancy method and apparatus
JPH11317091A (en) * 1998-04-30 1999-11-16 Nec Corp Semiconductor storage device
US6137735A (en) * 1998-10-30 2000-10-24 Mosaid Technologies Incorporated Column redundancy circuit with reduced signal path delay
JP4439683B2 (en) * 1999-06-03 2010-03-24 三星電子株式会社 Flash memory device having redundancy selection circuit and test method
US6438672B1 (en) 1999-06-03 2002-08-20 Agere Systems Guardian Corp. Memory aliasing method and apparatus
US6385071B1 (en) 2001-05-21 2002-05-07 International Business Machines Corporation Redundant scheme for CAMRAM memory array
US6584023B1 (en) * 2002-01-09 2003-06-24 International Business Machines Corporation System for implementing a column redundancy scheme for arrays with controls that span multiple data bits
US20040061990A1 (en) * 2002-09-26 2004-04-01 Dougherty T. Kirk Temperature-compensated ferroelectric capacitor device, and its fabrication
US20050027932A1 (en) * 2003-07-31 2005-02-03 Thayer Larry J. Content addressable memory with redundant stored data

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246087A (en) * 1989-03-20 1990-10-01 Hitachi Ltd Semiconductor storage device, redundant system thereof, and layout system
KR910005601B1 (en) * 1989-05-24 1991-07-31 삼성전자주식회사 Semiconductor memory device having redundunt block
JP3019869B2 (en) * 1990-10-16 2000-03-13 富士通株式会社 Semiconductor memory
JPH05166396A (en) * 1991-12-12 1993-07-02 Mitsubishi Electric Corp Semiconductor memory device
US5377146A (en) * 1993-07-23 1994-12-27 Alliance Semiconductor Corporation Hierarchical redundancy scheme for high density monolithic memories

Also Published As

Publication number Publication date
EP0758112A1 (en) 1997-02-12
ATE220228T1 (en) 2002-07-15
KR970012708A (en) 1997-03-29
US5675543A (en) 1997-10-07
JPH0955095A (en) 1997-02-25
EP0758112B1 (en) 2002-07-03
TW364114B (en) 1999-07-11
KR100409114B1 (en) 2004-04-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE