DE4211999C2 - LDD-Transistor und Verfahren zu dessen Herstellung - Google Patents

LDD-Transistor und Verfahren zu dessen Herstellung

Info

Publication number
DE4211999C2
DE4211999C2 DE4211999A DE4211999A DE4211999C2 DE 4211999 C2 DE4211999 C2 DE 4211999C2 DE 4211999 A DE4211999 A DE 4211999A DE 4211999 A DE4211999 A DE 4211999A DE 4211999 C2 DE4211999 C2 DE 4211999C2
Authority
DE
Germany
Prior art keywords
conductivity type
dopant
doped
diffused
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4211999A
Other languages
German (de)
English (en)
Other versions
DE4211999A1 (de
Inventor
Lee Yeun Hwang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MagnaChip Semiconductor Ltd
Original Assignee
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of DE4211999A1 publication Critical patent/DE4211999A1/de
Application granted granted Critical
Publication of DE4211999C2 publication Critical patent/DE4211999C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/605—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having significant overlap between the lightly-doped extensions and the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE4211999A 1991-04-10 1992-04-09 LDD-Transistor und Verfahren zu dessen Herstellung Expired - Fee Related DE4211999C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910005714A KR920020594A (ko) 1991-04-10 1991-04-10 Ldd 트랜지스터의 구조 및 제조방법

Publications (2)

Publication Number Publication Date
DE4211999A1 DE4211999A1 (de) 1992-10-15
DE4211999C2 true DE4211999C2 (de) 1999-06-10

Family

ID=19313084

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4211999A Expired - Fee Related DE4211999C2 (de) 1991-04-10 1992-04-09 LDD-Transistor und Verfahren zu dessen Herstellung

Country Status (4)

Country Link
JP (1) JP2547690B2 (enrdf_load_stackoverflow)
KR (1) KR920020594A (enrdf_load_stackoverflow)
DE (1) DE4211999C2 (enrdf_load_stackoverflow)
TW (1) TW268136B (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5518945A (en) * 1995-05-05 1996-05-21 International Business Machines Corporation Method of making a diffused lightly doped drain device with built in etch stop
US6339005B1 (en) * 1999-10-22 2002-01-15 International Business Machines Corporation Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET
US7732285B2 (en) * 2007-03-28 2010-06-08 Intel Corporation Semiconductor device having self-aligned epitaxial source and drain extensions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6143477A (ja) * 1984-08-08 1986-03-03 Hitachi Ltd Ｍｏｓトランジスタの製造方法
JPH06105715B2 (ja) * 1985-03-20 1994-12-21 株式会社日立製作所 半導体集積回路装置の製造方法
JPH01309376A (ja) * 1988-06-07 1989-12-13 Mitsubishi Electric Corp 半導体装置の製造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ibid, Vol. 11, No. 5, 1990, pp. 221-223 *
IEDM, 1985, pp. 234-237 *
IEEE El. Dev. Lett., Vol. 9, No. 8, Aug. 1988, pp. 408-410 *
IEEE Tr. o. El. Dev., Vol. 36, No. 6, June 1989, pp. 1125-1132 *

Also Published As

Publication number Publication date
KR920020594A (ko) 1992-11-21
JP2547690B2 (ja) 1996-10-23
JPH0629308A (ja) 1994-02-04
DE4211999A1 (de) 1992-10-15
TW268136B (enrdf_load_stackoverflow) 1996-01-11

Similar Documents

Publication Publication Date Title
DE69209678T2 (de) Halbleiteranordnung für Hochspannungsverwendung und Verfahren zur Herstellung
DE4344285B4 (de) Verfahren zur Herstellung eines Transistors
DE4224793C2 (de) Dünnfilmfeldeffektelement und Herstellungsverfahren dafür
DE69029942T2 (de) Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom
DE19749345C2 (de) Halbleitervorrichtung und Verfahren zur Herstellung derselben
DE69512021T2 (de) DMOS-Anordnung-Struktur und Verfahren zur Herstellung
DE69032937T2 (de) Verfahren zur Herstellung einer N-Kanal-EPROM-Zelle mit einer einzigen Polysiliziumschicht
DE2547828A1 (de) Halbleiter-speicherelement und verfahren zur herstellung desselben
DE2512373A1 (de) Sperrschicht-oberflaechen-feldeffekt- transistor
DE4229574A1 (de) Feldeffekttransistor und verfahren zu dessen herstellung
EP0033003B1 (de) Zweifach diffundierter Metalloxidsilicium-Feldeffekttransistor und Verfahren zu seiner Herstellung
DE10124413A1 (de) Halbleiter-Vorrichtung und Verfahren zur Herstellung derselben
DE3856150T2 (de) Halbleiteranordnung und verfahren zur herstellung
DE4208537A1 (de) Mos-fet-struktur
DE2262943C2 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
DE19711729A1 (de) Horizontal-Feldeffekttransistor und Verfahren zu seiner Herstellung
DE19733974C2 (de) MOSFET-Einrichtung und Verfahren zur Herstellung
DE19517002C2 (de) Halbleitervorrichtung und Verfahren zur Herstellung derselben
DE19620032C2 (de) Halbleiterbauelement mit Kompensationsimplantation und Herstellverfahren
DE112004000495B4 (de) Verfahren zur Herstellung eines Leistungsbauteils als Superjunction-Bauelement
DE4112044A1 (de) Halbleitereinrichtung mit wenigstens zwei feldeffekttransistoren und herstellungsverfahren fuer diese
DE4207913C2 (de) Metall-Oxid-Halbleiter-Feldeffekttransistoren und Verfahren zu ihrer Herstellung
DE4335851C2 (de) Verfahren zum Herstellen eines MOS-Transistors mit LDD-Struktur
DE4211999C2 (de) LDD-Transistor und Verfahren zu dessen Herstellung
DE69619487T2 (de) Isolierschicht-Feldeffekttransistor mit einem diffundierten Kanal

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: H01L 29/78

D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR

8327 Change in the person/name/address of the patent owner

Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR

8339 Ceased/non-payment of the annual fee