DE3787163T2 - Halbleiterspeicher mit einer Speicherstruktur mit vielfachen Pegeln. - Google Patents

Halbleiterspeicher mit einer Speicherstruktur mit vielfachen Pegeln.

Info

Publication number
DE3787163T2
DE3787163T2 DE87311050T DE3787163T DE3787163T2 DE 3787163 T2 DE3787163 T2 DE 3787163T2 DE 87311050 T DE87311050 T DE 87311050T DE 3787163 T DE3787163 T DE 3787163T DE 3787163 T2 DE3787163 T2 DE 3787163T2
Authority
DE
Germany
Prior art keywords
sub
bit lines
potential
data
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87311050T
Other languages
German (de)
English (en)
Other versions
DE3787163D1 (de
Inventor
Thoru Patent Division Furuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3787163D1 publication Critical patent/DE3787163D1/de
Publication of DE3787163T2 publication Critical patent/DE3787163T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
DE87311050T 1986-12-15 1987-12-15 Halbleiterspeicher mit einer Speicherstruktur mit vielfachen Pegeln. Expired - Fee Related DE3787163T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61298398A JPS63149900A (ja) 1986-12-15 1986-12-15 半導体メモリ

Publications (2)

Publication Number Publication Date
DE3787163D1 DE3787163D1 (de) 1993-09-30
DE3787163T2 true DE3787163T2 (de) 1994-02-17

Family

ID=17859185

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87311050T Expired - Fee Related DE3787163T2 (de) 1986-12-15 1987-12-15 Halbleiterspeicher mit einer Speicherstruktur mit vielfachen Pegeln.

Country Status (5)

Country Link
US (1) US4841483A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0273639B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS63149900A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR910006112B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3787163T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2622179B2 (ja) * 1988-12-29 1997-06-18 シャープ株式会社 ダイナミック型半導体記憶装置
JPH02260298A (ja) * 1989-03-31 1990-10-23 Oki Electric Ind Co Ltd 不揮発性多値メモリ装置
JPH0834257B2 (ja) * 1990-04-20 1996-03-29 株式会社東芝 半導体メモリセル
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
JP2528737B2 (ja) * 1990-11-01 1996-08-28 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2573416B2 (ja) * 1990-11-28 1997-01-22 株式会社東芝 半導体記憶装置
US5218569A (en) * 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
JP2564046B2 (ja) * 1991-02-13 1996-12-18 株式会社東芝 半導体記憶装置
DE69222793T2 (de) * 1991-03-14 1998-03-12 Toshiba Kawasaki Kk Halbleiterspeicheranordnung
JP3181311B2 (ja) * 1991-05-29 2001-07-03 株式会社東芝 半導体記憶装置
JP3464803B2 (ja) * 1991-11-27 2003-11-10 株式会社東芝 半導体メモリセル
US5291437A (en) * 1992-06-25 1994-03-01 Texas Instruments Incorporated Shared dummy cell
JPH08180688A (ja) * 1994-12-26 1996-07-12 Nec Corp 半導体記憶装置
US6353554B1 (en) * 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
JP3006510B2 (ja) * 1996-10-24 2000-02-07 日本電気株式会社 半導体メモリ
US6551857B2 (en) * 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
CA2217359C (en) * 1997-09-30 2005-04-12 Mosaid Technologies Incorporated Method for multilevel dram sensing
CA2273122A1 (en) * 1999-05-26 2000-11-26 Gershom Birk Multilevel dram with local reference generation
AU2003255254A1 (en) * 2002-08-08 2004-02-25 Glenn J. Leedy Vertical system integration
EP2006381B1 (en) 2006-03-31 2016-02-03 Chugai Seiyaku Kabushiki Kaisha Method for controlling blood pharmacokinetics of antibodies
DK2047863T3 (da) 2006-06-08 2013-09-16 Chugai Pharmaceutical Co Ltd Middel til forebyggelse eller behandling af inflammatoriske sygdomme
DE102007023653A1 (de) * 2007-05-22 2008-11-27 Qimonda Ag Halbleiterspeicher und Verfahren zum Betreiben eines Halbleiterspeichers
JP2009009641A (ja) * 2007-06-27 2009-01-15 Elpida Memory Inc 半導体記憶装置及びその読み出し方法
JP5334319B2 (ja) 2007-09-26 2013-11-06 中外製薬株式会社 Ｃｄｒのアミノ酸置換により抗体の等電点を改変する方法
CN107469077A (zh) 2008-04-11 2017-12-15 中外制药株式会社 与多个分子的抗原反复结合的抗原结合分子
TWI667257B (zh) 2010-03-30 2019-08-01 中外製藥股份有限公司 促進抗原消失之具有經修飾的ＦｃＲｎ親和力之抗體
KR101989392B1 (ko) * 2010-10-20 2019-06-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 구동 방법
US8933715B2 (en) * 2012-04-08 2015-01-13 Elm Technology Corporation Configurable vertical integration
MY181081A (en) 2013-12-27 2020-12-17 Chugai Pharmaceutical Co Ltd Method for purifying antibody having low isoelectric point
WO2020217138A2 (ja) * 2019-04-26 2020-10-29 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の動作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53144232A (en) * 1977-04-28 1978-12-15 Toshiba Corp Sensor circuit for multi-value signal charge transfer device
JPS5514588A (en) * 1978-07-19 1980-02-01 Toshiba Corp Semiconductor dynamic memory unit
JPS60239994A (ja) * 1984-05-15 1985-11-28 Seiko Epson Corp 多値ダイナミツクランダムアクセスメモリ
KR900005667B1 (ko) * 1984-11-20 1990-08-03 후지쓰 가부시끼가이샤 반도체 기억장치

Also Published As

Publication number Publication date
JPS63149900A (ja) 1988-06-22
EP0273639A3 (en) 1990-05-16
US4841483A (en) 1989-06-20
KR880008337A (ko) 1988-08-30
EP0273639B1 (en) 1993-08-25
DE3787163D1 (de) 1993-09-30
JPH059878B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-02-08
KR910006112B1 (ko) 1991-08-13
EP0273639A2 (en) 1988-07-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee