DE3633266A1 - Method of joining a wafer-type semiconductor body over a large area to a metallic substrate disc - Google Patents
Method of joining a wafer-type semiconductor body over a large area to a metallic substrate discInfo
- Publication number
- DE3633266A1 DE3633266A1 DE19863633266 DE3633266A DE3633266A1 DE 3633266 A1 DE3633266 A1 DE 3633266A1 DE 19863633266 DE19863633266 DE 19863633266 DE 3633266 A DE3633266 A DE 3633266A DE 3633266 A1 DE3633266 A1 DE 3633266A1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor body
- layers
- wafer
- metallic substrate
- substrate disc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000010931 gold Substances 0.000 claims abstract description 8
- 229910052737 gold Inorganic materials 0.000 claims abstract description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000010936 titanium Substances 0.000 claims abstract description 3
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 238000005275 alloying Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/01006—Carbon [C]
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/01015—Phosphorus [P]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01042—Molybdenum [Mo]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
Abstract
Description
Die Erfindung bezieht sich auf ein Verfahren zum großflächigen Verbinden eines scheibenförmigen Halbleiterkörpers mit einer metallischen Substratscheibe nach dem Oberbegriff des Patent anspruchs 1.The invention relates to a method for large-area Connecting a disk-shaped semiconductor body with one metallic substrate wafer according to the preamble of the patent claim 1.
Bei herkömmlichen Verfahren dieser Art wird der scheibenförmige Halbleiterkörper, z. B. aus Silizium, an seiner rückwärtigen Grenzfläche unter Zwischenfügung einer Aluminiumfolie mit einer Substratscheibe aus Molybdän bei einer Temperatur von ca. 700°C im Vakuum zusammenlegiert. Nachteilig ist jedoch, daß die unter schiedlichen thermischen Ausdehnungskoeffizienten von Molybdän und dem verwendeten Halbleitermaterial zwischen den auf diese Weise miteinander verbundenen Teilen beim Abkühlen derselben Spannungen hervorrufen, die zu einem Verbiegen des mit der Substratscheibe versehenen Halbleiterkörpers führen. Wird Silizium als Halbleitermaterial verwendet, so muß die rückwär tige Grenzfläche eine (111)-orientierte Fläche sein. Wegen der hohen Legierungstemperatur muß das Anlegieren der Substrat scheibe vor dem Aufbringen und Strukturieren der Metallisierung auf der Vorderseite des Halbleiterkörpers erfolgen. Eine nach dem Legierungsprozeß vorgesehene Strukturierung von Metall- und/oder Halbleiterschichten auf der Vorderseite des Halblei terkörpers kann jedoch wegen der genannten Verformung des Halb leiterkörpers im allgemeinen nicht mehr mit hoher Genauigkeit erfolgen. Auch muß die anzulegierende Substratscheibe aus einem hochwertigen, porenfreien, gewalzten Blech gefertigt sein. Da das Testen von Bauelementen, die auf dem Halbleiterkörper auf integriert werden, üblicherweise erst nach dem Legierungsprozeß erfolgt, führt der Ausfall der funktionsuntüchtigen Exemplare zum Verlust der jeweils anlegierten Substratscheiben.In conventional methods of this type, the disc-shaped Semiconductor body, e.g. B. made of silicon, on its rear Interface with the interposition of an aluminum foil with a Molybdenum substrate disc at a temperature of approx. 700 ° C alloyed in a vacuum. The disadvantage, however, is that the under different coefficients of thermal expansion of molybdenum and the semiconductor material used between them Parts that are connected to one another when they cool down Tensions that lead to bending of the Guide wafer provided semiconductor body. Becomes Silicon used as a semiconductor material, so the Rückwär interface is a (111) -oriented surface. Because of the high alloy temperature must be the alloying of the substrate before applying and structuring the metallization done on the front of the semiconductor body. One after structuring of metal and / or semiconductor layers on the front side of the semiconductor body can, however, because of the deformation of the half conductor body in general no longer with high accuracy respectively. The substrate wafer to be applied must also consist of one high-quality, non-porous, rolled sheet. There testing components based on the semiconductor body be integrated, usually only after the alloying process occurs, the failure of the inoperative copies leads to the loss of the respective alloyed substrate wafers.
Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren der eingangs genannten Art anzugeben, bei dem diese Nachteile ver mieden werden. Das wird erfindungsgemäß durch eine Ausbildung nach dem Kennzeichen des Patentanspruchs 1 erreicht.The invention has for its object a method of Specify the type mentioned, in which these disadvantages ver be avoided. According to the invention, this is achieved through training achieved according to the characterizing part of patent claim 1.
Der mit der Erfindung erzielbare Vorteil besteht insbesondere darin, daß durch das Aneinanderfügen der beiden Gold-Schichten eine sehr dauerhafte und hochbelastbare Verbindung zwischen dem Halbleiterkörper und der Substratscheibe erzielt wird. Da die Verbindung bei Zimmertemperatur erfolgt und die Gold-Schichten nicht in den Halbleiterkörper einlegiert werden, treten die genannten, bei den herkömmlichen Verfahren vorliegenden Beein trächtigungen nicht auf.The advantage that can be achieved with the invention is in particular in that by joining the two gold layers together a very permanent and heavy-duty connection between the Semiconductor body and the substrate wafer is achieved. Since the Connection is done at room temperature and the gold layers are not alloyed into the semiconductor body, the Legs mentioned in the conventional methods do not show up.
Der Anspruch 2 ist auf bevorzugte Anwendungen des Verfahrens nach der Erfindung gerichtet.Claim 2 is for preferred applications of the method directed according to the invention.
Die Erfindung wird nachfolgend anhand der Zeichnung näher er läutert. Dabei zeigt Fig. 1 in schematischer Darstellung eine Einrichtung, die zur Durchführung des erfindungsgemäßen Ver fahrens geeignet ist. Beispielsweise soll der aus einer n-lei tenden Schicht 1 und einer p-leitenden Schicht 2 bestehende Silizium-Halbleiterkörper 3 einer Hochleistungsdiode, der be reits mit einer kathodenseitigen Elektrode E versehen ist, mit einer Substratscheibe 4 aus Molybdän verbunden werden. Dies geschieht in einer Vakuumanlage, bestehend aus einem Gehäuse 5, das mit einem Deckel 6 verschließbar ist und über ein Absaugrohr 7 mit einer Vakuumpumpe 8 in Verbindung steht. Der Halbleiterkörper 3 hat vorzugsweise die Form einer sehr flachen kreisförmigen Scheibe, deren in vertikaler Richtung gemessene Dicke wesentlich kleiner ist als der in lateraler Richtung gemessene Scheibendurchmesser. In Fig. 1 sind die lateralen Abmessungen des Halbleiterkörpers aus Gründen einer einfachen Darstellung stark verkürzt dargestellt. The invention is explained in more detail with reference to the drawing. Here, FIG. 1 is a schematic representation showing a device which is suitable for performing the driving Ver invention. For example, the silicon semiconductor body 3 of a high-performance diode consisting of an n-conductive layer 1 and a p-conductive layer 2 , which is already provided with a cathode-side electrode E , is to be connected to a substrate wafer 4 made of molybdenum. This takes place in a vacuum system, consisting of a housing 5 , which can be closed with a cover 6 and is connected to a vacuum pump 8 via a suction pipe 7 . The semiconductor body 3 preferably has the shape of a very flat circular disk, the thickness of which is measured in the vertical direction is substantially smaller than the disk diameter measured in the lateral direction. In Fig. 1, the lateral dimensions of the semiconductor body are shown in a greatly shortened form for reasons of a simple representation.
Beim erfindungsgemäßen Verfahren werden zunächst die Rückseite 9 des Halbleiterkörpers und die Vorderseite 10 der Substrat scheibe 4 außerhalb der Vakuumanlage in herkömmlicher Weise so weit poliert, daß sehr glatte Oberflächen entstehen, die im In terferenzbild jeweils nur wenige Newton-Ringe aufweisen. An schließend werden die Teile 3 und 4 in das Gehäuse 5 einge bracht, in dem sich ein Tiegel 11 befindet, der ein Haftgrund material, z.B. Titan, enthält. Dabei wird der Halbleiterkörper 3 von einer federnden Klammer 12 gehalten, die an einem Arm 13 befestigt ist, welcher mittels einer Hülse 14 auf einer durch 5 nach außen geführten Achse 15 drehbar gelagert ist. Eine weite re, entsprechend gelagerte Hülse ist mit einem Arm 16 verbun den. Dieser weist eine endseitige, federnde Klammer 17 auf, die die Substratscheibe 4 hält. Durch Verdrehen der beiden Hülsen können die Teile 3 und 4 gegeneinander verschwenkt werden, wobei sich ihre Flächen 9 und 10 einander weitgehend annähern. Nach dem Evakuieren des Gehäuses 5 wir die elektrische Heizung 18 des Tiegels 11 eingeschaltet, so daß sich das Haftgrundma terial auf eine Temperatur von etwa 1700°C erhitzt. Dabei ver dampft das Haftgrundmaterial, so daß in der gezeichneten Stellung der Arme 13 und 16 eine Haftgrundschicht 19 von etwa 40 Å Dicke auf der Fläche 9 des Halbleiterkörpers 3 und eine entsprechende Schicht 20 auf der Vorderseite 10 der Substrat scheibe aufgedampft werden. Anschließend wird ein weiterer Tiegel 21, der im Gehäuse 5 angeordnet ist und Gold enthält, unter Aufrechterhaltung des Vakuums mittels einer elektrischen Heizung 22 auf eine Temperatur von etwa 1100°C erhitzt. Dabei werden auf den Schichten 19 und 20 jeweils Goldschichten 23 und 24 von z.B. 60 Å Dicke aufgedampft. Die so beschichteten Flächen 9 und 10 werden bei Zimmertemperatur durch Schwenken der Arme 13 und 16 mit geringem Druck aufeinandergelegt. Dabei gehen die Goldschichten 23 und 24 eine so innige Verbindung miteinander ein, daß eine hochbelastbare Verbindung des scheibenförmigen Halbleiterkörpers 3 mit der Substratscheibe 4 entsteht. Der zuletzt genannte Schritt des Aufeinanderlegens der Schichten 23 und 24 erfolgt im Inneren des evakuierten Gehäuses 5. In the method according to the invention, the back 9 of the semiconductor body and the front 10 of the substrate 4 are first polished outside the vacuum system in a conventional manner to such an extent that very smooth surfaces are formed which each have only a few Newton rings in the interference image. At closing, the parts 3 and 4 are brought into the housing 5 , in which there is a crucible 11 which contains an adhesive base material, for example titanium. The semiconductor body 3 is held by a resilient bracket 12 which is fastened to an arm 13 which is rotatably mounted by means of a sleeve 14 on an axis 15 guided through 5 to the outside. A wide re, appropriately mounted sleeve is with an arm 16 verbun the. This has an end resilient clamp 17 which holds the substrate wafer 4 . By rotating the two sleeves, parts 3 and 4 can be pivoted against one another, their surfaces 9 and 10 largely approaching one another. After evacuating the housing 5, we turned on the electric heater 18 of the crucible 11 , so that the Haftgrundma material heated to a temperature of about 1700 ° C. This evaporates the adhesive base material, so that in the drawn position of the arms 13 and 16, an adhesive base layer 19 of about 40 Å thickness on the surface 9 of the semiconductor body 3 and a corresponding layer 20 on the front 10 of the substrate wafer are evaporated. A further crucible 21 , which is arranged in the housing 5 and contains gold, is then heated to a temperature of approximately 1100 ° C. by means of an electrical heater 22 while maintaining the vacuum. Gold layers 23 and 24, for example 60 Å thick, are deposited on layers 19 and 20, respectively. The surfaces 9 and 10 coated in this way are placed on one another at room temperature by pivoting the arms 13 and 16 with low pressure. The gold layers 23 and 24 form such an intimate connection with one another that a heavy-duty connection of the disk-shaped semiconductor body 3 to the substrate disk 4 is produced. The last-mentioned step of stacking the layers 23 and 24 takes place inside the evacuated housing 5 .
Da die Verbindung der Schichten 23 und 24 bei Zimmertemperatur erfolgt und ein Eindringen der Schichten 19, 20, 23, 24 in das Silizium nicht stattfindet, ist das erfindungsgemäße Verfahren nicht mit den Nachteilen der herkömmlichen Legierungsverfahren behaftet. Die Substratscheibe 4 stellt die anodenseitige Elek trode der Leistungsdiode dar und gibt dem Halbleiterkörper 3 zusätzlich die notwendige Biegefestigkeit.Since the layers 23 and 24 are connected at room temperature and the layers 19 , 20 , 23 , 24 do not penetrate into the silicon, the method according to the invention is not burdened with the disadvantages of the conventional alloying methods. The substrate wafer 4 represents the anode-side electrode of the power diode and also gives the semiconductor body 3 the necessary flexural strength.
Anstelle einer Leistungsdiode kann z.B. auch ein Leistungstran sistor unter Verwendung des erfindungsgemäßen Verfahrens mit der Substratscheibe 4 verbunden werden. Bei einem solchen weist der Halbleiterkörper 3 zusätzlich eine in die Schicht 2 einge fügte, n-leitende Schicht 25 auf, die durch einen gestrichelten pn-Übergang 26 von 2 getrennt ist. Die Schichten 25 und 2 sind dabei jeweils mit einer Emitterelektrode E und einer Basiselek trode B versehen. Die Substratscheibe 4 bildet dann die Kollek torelektrode.Instead of a power diode, for example, can also be a Leistungstran sistor using the method according to the invention with the substrate wafer 4 are connected. In such a case, the semiconductor body 3 additionally has an n-type layer 25 inserted into the layer 2, which is separated from FIG. 2 by a dashed pn junction 26 . The layers 25 and 2 are each provided with an emitter electrode E and a base electrode B. The substrate wafer 4 then forms the collector gate electrode.
In Fig. 2 ist ein Leistungsthyristor dargestellt, dessen Halb leiterkörper aus einem p-Emitter 27, einer n-Basis 28, einer p-Basis 29 und einem n-Emitter 30 besteht. Auch hier kann das erfindungsgemäße Verfahren verwendet werden, um die anodensei tige Elektrode 31 mit dem p-Emitter 27 zu verbinden. Dabei sind die Schichten 30 und 29 bereits vor dem Einbringen des Halblei terkörpers in das Gehäuse 5 jeweils mit der kathodenseitigen Elektrode 32 und der Zündelektrode 33 versehen. FIG. 2 shows a power thyristor whose semiconductor body consists of a p-emitter 27 , an n-base 28 , a p-base 29 and an n-emitter 30 . The method according to the invention can also be used here to connect the anode-side electrode 31 to the p-emitter 27 . The layers 30 and 29 are already provided with the cathode-side electrode 32 and the ignition electrode 33 before the introduction of the semiconductor body into the housing 5 .
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19863633266 DE3633266A1 (en) | 1986-09-30 | 1986-09-30 | Method of joining a wafer-type semiconductor body over a large area to a metallic substrate disc |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19863633266 DE3633266A1 (en) | 1986-09-30 | 1986-09-30 | Method of joining a wafer-type semiconductor body over a large area to a metallic substrate disc |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3633266A1 true DE3633266A1 (en) | 1988-03-31 |
Family
ID=6310719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19863633266 Withdrawn DE3633266A1 (en) | 1986-09-30 | 1986-09-30 | Method of joining a wafer-type semiconductor body over a large area to a metallic substrate disc |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE3633266A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0715351A1 (en) | 1994-12-02 | 1996-06-05 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Semiconductor power component |
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1986
- 1986-09-30 DE DE19863633266 patent/DE3633266A1/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0715351A1 (en) | 1994-12-02 | 1996-06-05 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Semiconductor power component |
| US6054727A (en) * | 1994-12-02 | 2000-04-25 | Eupec Europaische Gesellschaft fuer Leistungshalbleiter mbH & Co. KG | Power semiconductor component |
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