DE3584854D1 - Verfahren zum bezeichnen elektrischer verbindungen auf einem integrierten produkt und das resultierende produkt. - Google Patents

Verfahren zum bezeichnen elektrischer verbindungen auf einem integrierten produkt und das resultierende produkt.

Info

Publication number
DE3584854D1
DE3584854D1 DE8585105713T DE3584854T DE3584854D1 DE 3584854 D1 DE3584854 D1 DE 3584854D1 DE 8585105713 T DE8585105713 T DE 8585105713T DE 3584854 T DE3584854 T DE 3584854T DE 3584854 D1 DE3584854 D1 DE 3584854D1
Authority
DE
Germany
Prior art keywords
product
electrical connections
integrated
designating
resulting product
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585105713T
Other languages
English (en)
Inventor
Ralph Linsker
Roger Sherman Rutter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3584854D1 publication Critical patent/DE3584854D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
DE8585105713T 1984-06-04 1985-05-10 Verfahren zum bezeichnen elektrischer verbindungen auf einem integrierten produkt und das resultierende produkt. Expired - Fee Related DE3584854D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/616,869 US4571451A (en) 1984-06-04 1984-06-04 Method for routing electrical connections and resulting product

Publications (1)

Publication Number Publication Date
DE3584854D1 true DE3584854D1 (de) 1992-01-23

Family

ID=24471310

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585105713T Expired - Fee Related DE3584854D1 (de) 1984-06-04 1985-05-10 Verfahren zum bezeichnen elektrischer verbindungen auf einem integrierten produkt und das resultierende produkt.

Country Status (4)

Country Link
US (1) US4571451A (de)
EP (1) EP0163978B1 (de)
JP (1) JPH0750817B2 (de)
DE (1) DE3584854D1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4689441A (en) * 1985-04-05 1987-08-25 International Business Machines Corporation Routing method and pattern for reducing cross talk noise problems on printed interconnection boards
US4831497A (en) * 1986-09-11 1989-05-16 General Electric Company Reduction of cross talk in interconnecting conductors
JPH0290368A (ja) * 1988-09-28 1990-03-29 Fujitsu Ltd Ｓｍｄ部品端子の自動引出し配線データ作成方法
US5224022A (en) * 1990-05-15 1993-06-29 Microelectronics And Computer Technology Corporation Reroute strategy for high density substrates
US5220490A (en) * 1990-10-25 1993-06-15 Microelectronics And Computer Technology Corporation Substrate interconnect allowing personalization using spot surface links
JP2759573B2 (ja) * 1992-01-23 1998-05-28 株式会社日立製作所 回路基板の配線パターン決定方法
JPH06196563A (ja) * 1992-09-29 1994-07-15 Internatl Business Mach Corp <Ibm> Ｖｌｓｉの配線設計に対するコンピュータ実施可能な過密領域配線方法
US6256769B1 (en) 1999-09-30 2001-07-03 Unisys Corporation Printed circuit board routing techniques
US7441220B2 (en) * 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US7594196B2 (en) * 2000-12-07 2009-09-22 Cadence Design Systems, Inc. Block interstitching using local preferred direction architectures, tools, and apparatus
CN1333044C (zh) 2003-09-28 2007-08-22 中国石油化工股份有限公司 一种烃油裂化方法
US7347930B2 (en) 2003-10-16 2008-03-25 China Petroleum & Chemical Corporation Process for cracking hydrocarbon oils
US7340711B2 (en) * 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
US7412682B2 (en) * 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
EP1756741A4 (de) * 2004-06-04 2007-09-05 Cadence Design Systems Inc Routen mit lokaler bevorzugter richtung und layout-erzeugung
US7707537B2 (en) * 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8250514B1 (en) 2006-07-13 2012-08-21 Cadence Design Systems, Inc. Localized routing direction

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3567914A (en) * 1964-12-31 1971-03-02 Sperry Rand Corp Automated manufacturing system
NL159822B (nl) * 1969-01-02 1979-03-15 Philips Nv Halfgeleiderinrichting.
US4202007A (en) * 1978-06-23 1980-05-06 International Business Machines Corporation Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers
JPS5849654Y2 (ja) * 1978-07-31 1983-11-12 東芝テック株式会社 両面パタ−ン付印刷配線板
US4295198A (en) * 1979-04-02 1981-10-13 Cogit Systems, Inc. Automatic printed circuit dimensioning, routing and inspecting apparatus
US4320438A (en) * 1980-05-15 1982-03-16 Cts Corporation Multi-layer ceramic package
US4458297A (en) * 1981-01-16 1984-07-03 Mosaic Systems, Inc. Universal interconnection substrate
EP0069762B1 (de) * 1981-01-16 1989-02-08 JOHNSON, Robert Royce Ein universelles substrat zur wechselseitigen elektrischen verbindung von chips
JPS5918880A (ja) * 1982-07-21 1984-01-31 モルザ株式会社 建具

Also Published As

Publication number Publication date
EP0163978A3 (en) 1987-03-25
US4571451A (en) 1986-02-18
EP0163978B1 (de) 1991-12-11
EP0163978A2 (de) 1985-12-11
JPS60263491A (ja) 1985-12-26
JPH0750817B2 (ja) 1995-05-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee