DE3568911D1 - A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters - Google Patents

A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters

Info

Publication number
DE3568911D1
DE3568911D1 DE19853568911 DE3568911A DE3568911D1 DE 3568911 D1 DE3568911 D1 DE 3568911D1 DE 19853568911 DE19853568911 DE 19853568911 DE 3568911 A DE3568911 A DE 3568911A DE 3568911 D1 DE3568911 D1 DE 3568911D1
Authority
DE
Grant status
Grant
Patent type
Prior art keywords
memory
pair
inverters
device
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19853568911
Other languages
English (en)
Inventor
Fujio C O Patent Divis Masuoka
Kiyofumi C O Patent Divi Ochii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1104Static random access memory structures the load element being a MOSFET transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53271Conductive materials containing semiconductor material, e.g. polysilicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903FET configuration adapted for use as static memory cell
DE19853568911 1984-04-27 1985-04-25 A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters Expired DE3568911D1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP8561784A JPH0648722B2 (ja) 1984-04-27 1984-04-27 半導体記憶装置
JP8561884A JPH0648723B2 (ja) 1984-04-27 1984-04-27 半導体記憶装置
JP25302784A JPS61131547A (en) 1984-11-30 1984-11-30 Semiconductor device
JP25302684A JPS61131558A (en) 1984-11-30 1984-11-30 Semiconductor device

Publications (1)

Publication Number Publication Date
DE3568911D1 true DE3568911D1 (en) 1989-04-20

Family

ID=27467140

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853568911 Expired DE3568911D1 (en) 1984-04-27 1985-04-25 A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters

Country Status (4)

Country Link
US (1) US4710897A (de)
EP (1) EP0163132B1 (de)
KR (1) KR890004458B1 (de)
DE (1) DE3568911D1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975756A (en) * 1985-05-01 1990-12-04 Texas Instruments Incorporated SRAM with local interconnect
JPS62169472A (en) * 1986-01-22 1987-07-25 Hitachi Ltd Semiconductor integrated circuit device
KR890002812B1 (ko) * 1986-11-28 1989-07-31 강진구 씨모오스 디램에서 레이아웃이 최적화된 감지증폭기
JPH0415618B2 (de) * 1986-12-16 1992-03-18 Sharp Kk
JP2681887B2 (ja) * 1987-03-06 1997-11-26 シ−メンス、アクチエンゲゼルシヤフト 3次元1トランジスタメモリセル構造とその製法
US4835458A (en) * 1987-11-09 1989-05-30 Intel Corporation Signature analysis technique for defect characterization of CMOS static RAM cell failures
JPH01186655A (en) * 1988-01-14 1989-07-26 Fujitsu Ltd Semiconductor integrated circuit
US4918510A (en) * 1988-10-31 1990-04-17 Motorola, Inc. Compact CMOS device structure
US5227649A (en) * 1989-02-27 1993-07-13 Texas Instruments Incorporated Circuit layout and method for VLSI circuits having local interconnects
US5194752A (en) * 1989-05-23 1993-03-16 Kabushiki Kaisha Toshiba Semiconductor memory device
US5254874A (en) * 1990-05-02 1993-10-19 Quality Semiconductor Inc. High density local interconnect in a semiconductor circuit using metal silicide
EP0527194A4 (en) * 1990-05-02 1993-04-14 Quality Semiconductor, Inc. High density local interconnect in a semiconductor circuit using metal silicide
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JPH0541378A (ja) * 1991-03-15 1993-02-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5298782A (en) * 1991-06-03 1994-03-29 Sgs-Thomson Microelectronics, Inc. Stacked CMOS SRAM cell with polysilicon transistor load
US5416034A (en) * 1993-06-30 1995-05-16 Sgs-Thomson Microelectronics, Inc. Method of making resistor with silicon-rich silicide contacts for an integrated circuit
US5654915A (en) * 1993-08-19 1997-08-05 Cypress Semiconductor Corp. 6-bulk transistor static memory cell using split wordline architecture
JP3807836B2 (ja) 1997-11-28 2006-08-09 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法
JPH11185476A (ja) * 1997-12-18 1999-07-09 Toshiba Corp 半導体記憶装置
KR100290903B1 (ko) * 1998-02-25 2001-03-07 김영환 반도체소자 및 이의 제조방법
JP3985735B2 (ja) * 2003-06-11 2007-10-03 セイコーエプソン株式会社 半導体記憶装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6124830B2 (de) * 1977-11-21 1986-06-12 Tokyo Shibaura Electric Co
US4333099A (en) * 1978-02-27 1982-06-01 Rca Corporation Use of silicide to bridge unwanted polycrystalline silicon P-N junction
JPS647508B2 (de) * 1979-01-23 1989-02-09 Nippon Electric Co
CA1142261A (en) * 1979-06-29 1983-03-01 Siegfried K. Wiedmann Interconnection of opposite conductivity type semiconductor regions
JPS5661158A (en) * 1979-10-25 1981-05-26 Seiko Epson Corp Cmos random access memory
WO1981002222A1 (en) * 1980-01-21 1981-08-06 Mostek Corp Composit gate interconnect structure
JPS6046547B2 (de) * 1980-07-16 1985-10-16 Tokyo Shibaura Electric Co
JPS57152161A (en) * 1981-03-16 1982-09-20 Seiko Epson Corp Manufacture of semiconductor device
US4613886A (en) * 1981-07-09 1986-09-23 Intel Corporation CMOS static memory cell
JPS594067A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date Type
US4710897A (en) 1987-12-01 grant
EP0163132A1 (de) 1985-12-04 application
KR890004458B1 (ko) 1989-11-04 grant
EP0163132B1 (de) 1989-03-15 grant

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licenses declared (paragraph 23)