DE3486064D1 - Logische schaltung mit eingebauter selbsttestfunktion. - Google Patents

Logische schaltung mit eingebauter selbsttestfunktion.

Info

Publication number
DE3486064D1
DE3486064D1 DE8484112567T DE3486064T DE3486064D1 DE 3486064 D1 DE3486064 D1 DE 3486064D1 DE 8484112567 T DE8484112567 T DE 8484112567T DE 3486064 T DE3486064 T DE 3486064T DE 3486064 D1 DE3486064 D1 DE 3486064D1
Authority
DE
Germany
Prior art keywords
built
self
logical circuit
test function
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484112567T
Other languages
English (en)
Other versions
DE3486064T2 (de
Inventor
Shojiro C O Patent Divisi Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3486064D1 publication Critical patent/DE3486064D1/de
Publication of DE3486064T2 publication Critical patent/DE3486064T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
DE8484112567T 1983-10-20 1984-10-18 Logische schaltung mit eingebauter selbsttestfunktion. Expired - Fee Related DE3486064T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58196767A JPS6088370A (ja) 1983-10-20 1983-10-20 論理回路

Publications (2)

Publication Number Publication Date
DE3486064D1 true DE3486064D1 (de) 1993-03-18
DE3486064T2 DE3486064T2 (de) 1993-07-15

Family

ID=16363279

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484112567T Expired - Fee Related DE3486064T2 (de) 1983-10-20 1984-10-18 Logische schaltung mit eingebauter selbsttestfunktion.

Country Status (4)

Country Link
US (1) US4682331A (de)
EP (1) EP0151694B1 (de)
JP (1) JPS6088370A (de)
DE (1) DE3486064T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4739250A (en) * 1985-11-20 1988-04-19 Fujitsu Limited Semiconductor integrated circuit device with test circuit
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
CA1306496C (en) * 1987-04-13 1992-08-18 Joseph L. Ardini, Jr. Method and apparatus for high accuracy measurement of vlsi components
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
JPH03211481A (ja) * 1990-01-17 1991-09-17 Nec Corp Ｌｓｉテスト回路
JPH06295599A (ja) * 1993-04-09 1994-10-21 Nec Corp 半導体記憶装置
US5960009A (en) * 1996-08-09 1999-09-28 Lucent Technologies Inc. Built in shelf test method and apparatus for booth multipliers
US20050050422A1 (en) * 2003-08-27 2005-03-03 Noriko Jo Semiconductor integrated circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3559167A (en) * 1968-07-25 1971-01-26 Ibm Self-checking error checker for two-rail coded data
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
US4001818A (en) * 1975-10-22 1977-01-04 Storage Technology Corporation Digital circuit failure detector
US4176258A (en) * 1978-05-01 1979-11-27 Intel Corporation Method and circuit for checking integrated circuit chips
US4242751A (en) * 1978-08-28 1980-12-30 Genrad, Inc. Automatic fault-probing method and apparatus for checking electrical circuits and the like
US4271515A (en) * 1979-03-23 1981-06-02 John Fluke Mfg. Co., Inc. Universal analog and digital tester
US4328583A (en) * 1980-09-08 1982-05-04 Rockwell International Corporation Data bus fault detector
US4412327A (en) * 1981-02-25 1983-10-25 Western Electric Company, Inc. Test circuit for checking memory output state continuously during time window
US4541090A (en) * 1981-06-09 1985-09-10 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks

Also Published As

Publication number Publication date
US4682331A (en) 1987-07-21
EP0151694A2 (de) 1985-08-21
JPS6088370A (ja) 1985-05-18
EP0151694B1 (de) 1993-02-03
DE3486064T2 (de) 1993-07-15
EP0151694A3 (en) 1988-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee