DE3483659D1 - Verfahren zur herstellung von polycide-strukturen. - Google Patents

Verfahren zur herstellung von polycide-strukturen.

Info

Publication number
DE3483659D1
DE3483659D1 DE8484105540T DE3483659T DE3483659D1 DE 3483659 D1 DE3483659 D1 DE 3483659D1 DE 8484105540 T DE8484105540 T DE 8484105540T DE 3483659 T DE3483659 T DE 3483659T DE 3483659 D1 DE3483659 D1 DE 3483659D1
Authority
DE
Germany
Prior art keywords
producing
polycide structures
polycide
structures
producing polycide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484105540T
Other languages
German (de)
English (en)
Inventor
Stanley Roberts
Francis Roger White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3483659D1 publication Critical patent/DE3483659D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/202—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials for lift-off processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/058—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by depositing on sacrificial masks, e.g. using lift-off
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/084—Ion implantation of compound devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off
DE8484105540T 1983-05-23 1984-05-16 Verfahren zur herstellung von polycide-strukturen. Expired - Lifetime DE3483659D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/497,372 US4470189A (en) 1983-05-23 1983-05-23 Process for making polycide structures

Publications (1)

Publication Number Publication Date
DE3483659D1 true DE3483659D1 (de) 1991-01-10

Family

ID=23976595

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484105540T Expired - Lifetime DE3483659D1 (de) 1983-05-23 1984-05-16 Verfahren zur herstellung von polycide-strukturen.

Country Status (4)

Country Link
US (1) US4470189A (https=)
EP (1) EP0126424B1 (https=)
JP (1) JPS59217328A (https=)
DE (1) DE3483659D1 (https=)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
FR2571177B1 (fr) * 1984-10-02 1987-02-27 Thomson Csf Procede de realisation de grilles en siliciure ou en silicium pour circuit integre comportant des elements du type grille - isolant - semi-conducteur
US4612258A (en) * 1984-12-21 1986-09-16 Zilog, Inc. Method for thermally oxidizing polycide substrates in a dry oxygen environment and semiconductor circuit structures produced thereby
US4663191A (en) * 1985-10-25 1987-05-05 International Business Machines Corporation Salicide process for forming low sheet resistance doped silicon junctions
US4796562A (en) * 1985-12-03 1989-01-10 Varian Associates, Inc. Rapid thermal cvd apparatus
US4709655A (en) * 1985-12-03 1987-12-01 Varian Associates, Inc. Chemical vapor deposition apparatus
JPS6362356A (ja) * 1986-09-03 1988-03-18 Mitsubishi Electric Corp 半導体装置
GB8710359D0 (en) * 1987-05-01 1987-06-03 Inmos Ltd Semiconductor element
US4974056A (en) * 1987-05-22 1990-11-27 International Business Machines Corporation Stacked metal silicide gate structure with barrier
JPH01120818A (ja) * 1987-09-23 1989-05-12 Siemens Ag 低伝達抵抗オーム接触の形成方法
JP2624797B2 (ja) * 1988-09-20 1997-06-25 株式会社日立製作所 アクティブマトリクス基板の製造方法
US4978637A (en) * 1989-05-31 1990-12-18 Sgs-Thomson Microelectronics, Inc. Local interconnect process for integrated circuits
US5077236A (en) * 1990-07-02 1991-12-31 Samsung Electronics Co., Ltd. Method of making a pattern of tungsten interconnection
KR920015622A (ko) * 1991-01-31 1992-08-27 원본미기재 집적 회로의 제조방법
US5334545A (en) * 1993-02-01 1994-08-02 Allied Signal Inc. Process for forming self-aligning cobalt silicide T-gates of silicon MOS devices
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
JP3045946B2 (ja) * 1994-05-09 2000-05-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスの製造方法
US5847463A (en) * 1997-08-22 1998-12-08 Micron Technology, Inc. Local interconnect comprising titanium nitride barrier layer
JP3209164B2 (ja) * 1997-10-07 2001-09-17 日本電気株式会社 半導体装置の製造方法
KR100269328B1 (ko) * 1997-12-31 2000-10-16 윤종용 원자층 증착 공정을 이용하는 도전층 형성방법
US6235630B1 (en) * 1998-08-19 2001-05-22 Micron Technology, Inc. Silicide pattern structures and methods of fabricating the same
US6214713B1 (en) * 1998-10-19 2001-04-10 Promos Technology, Inc. Two step cap nitride deposition for forming gate electrodes
US6077750A (en) * 1998-10-27 2000-06-20 Lg Semicon Co., Ltd. Method for forming epitaxial Co self-align silicide for semiconductor device
KR100505449B1 (ko) * 1998-12-24 2005-10-14 주식회사 하이닉스반도체 반도체 소자의 폴리사이드 게이트 전극 형성방법
US6251777B1 (en) 1999-03-05 2001-06-26 Taiwan Semiconductor Manufacturing Company Thermal annealing method for forming metal silicide layer
US6475911B1 (en) * 2000-08-16 2002-11-05 Micron Technology, Inc. Method of forming noble metal pattern
DE10121240C1 (de) * 2001-04-30 2002-06-27 Infineon Technologies Ag Verfahren zur Herstellung für eine integrierte Schaltung, insbesondere eine Anti-Fuse, und entsprechende integrierte Schaltung
US7049245B2 (en) * 2003-09-12 2006-05-23 Promos Technologies, Inc. Two-step GC etch for GC profile and process window improvement
US7678704B2 (en) * 2005-12-13 2010-03-16 Infineon Technologies Ag Method of making a contact in a semiconductor device
US20070161246A1 (en) * 2006-01-10 2007-07-12 Texas Instruments Incorporated Process For Selectively Removing Dielectric Material in the Presence of Metal Silicide
WO2008061258A2 (en) * 2006-11-17 2008-05-22 Sachem, Inc. Selective metal wet etch composition and process
JP7036001B2 (ja) * 2018-12-28 2022-03-15 三菱電機株式会社 半導体装置の製造方法
CN110661170B (zh) * 2019-08-13 2021-01-08 深圳市矽赫科技有限公司 一种用于制造半导体器件隔离结构的方法及其半导体器件

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4128670A (en) * 1977-11-11 1978-12-05 International Business Machines Corporation Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
DE3045922A1 (de) * 1980-12-05 1982-07-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus siliziden oder aus silizid-polysilizium bestehenden schichten durch reaktives sputteraetzen
US4352716A (en) * 1980-12-24 1982-10-05 International Business Machines Corporation Dry etching of copper patterns
US4362597A (en) * 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
US4389257A (en) * 1981-07-30 1983-06-21 International Business Machines Corporation Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes
US4378628A (en) * 1981-08-27 1983-04-05 Bell Telephone Laboratories, Incorporated Cobalt silicide metallization for semiconductor integrated circuits
US4398341A (en) * 1981-09-21 1983-08-16 International Business Machines Corp. Method of fabricating a highly conductive structure
US4414057A (en) * 1982-12-03 1983-11-08 Inmos Corporation Anisotropic silicide etching process
US4411734A (en) * 1982-12-09 1983-10-25 Rca Corporation Etching of tantalum silicide/doped polysilicon structures

Also Published As

Publication number Publication date
EP0126424A3 (en) 1988-01-13
JPS59217328A (ja) 1984-12-07
EP0126424A2 (en) 1984-11-28
JPH0412612B2 (https=) 1992-03-05
EP0126424B1 (en) 1990-11-28
US4470189A (en) 1984-09-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee