DE3439018A1 - Verfahren zur herstellung von halbleiterelementen - Google Patents

Verfahren zur herstellung von halbleiterelementen

Info

Publication number
DE3439018A1
DE3439018A1 DE19843439018 DE3439018A DE3439018A1 DE 3439018 A1 DE3439018 A1 DE 3439018A1 DE 19843439018 DE19843439018 DE 19843439018 DE 3439018 A DE3439018 A DE 3439018A DE 3439018 A1 DE3439018 A1 DE 3439018A1
Authority
DE
Germany
Prior art keywords
wafer
heat treatment
atmosphere
oxygen
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19843439018
Other languages
German (de)
English (en)
Other versions
DE3439018C2 (https=
Inventor
Tadashi Itami Hyogo Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3439018A1 publication Critical patent/DE3439018A1/de
Application granted granted Critical
Publication of DE3439018C2 publication Critical patent/DE3439018C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films

Landscapes

  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE19843439018 1983-12-21 1984-10-25 Verfahren zur herstellung von halbleiterelementen Granted DE3439018A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58243263A JPS60133734A (ja) 1983-12-21 1983-12-21 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3439018A1 true DE3439018A1 (de) 1985-07-04
DE3439018C2 DE3439018C2 (https=) 1990-12-06

Family

ID=17101262

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843439018 Granted DE3439018A1 (de) 1983-12-21 1984-10-25 Verfahren zur herstellung von halbleiterelementen

Country Status (3)

Country Link
US (1) US4661166A (https=)
JP (1) JPS60133734A (https=)
DE (1) DE3439018A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3837270A1 (de) * 1987-11-18 1989-06-01 Intersil Inc Integrierte cmos-schaltung und verfahren zum herstellen derselben
DE19609107A1 (de) * 1995-03-09 1996-09-12 Toshiba Ceramics Co Siliciumwafer mit gesteuerter BMD-Konzentration im Innern und mit guter DZ-Schicht sowie Verfahren zu seiner Herstellung
CN113421820A (zh) * 2021-06-22 2021-09-21 捷捷半导体有限公司 一种氧化退火方法

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63198334A (ja) * 1987-02-13 1988-08-17 Komatsu Denshi Kinzoku Kk 半導体シリコンウエ−ハの製造方法
US4843037A (en) * 1987-08-21 1989-06-27 Bell Communications Research, Inc. Passivation of indium gallium arsenide surfaces
US4868133A (en) * 1988-02-11 1989-09-19 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
US4981549A (en) * 1988-02-23 1991-01-01 Mitsubishi Kinzoku Kabushiki Kaisha Method and apparatus for growing silicon crystals
US5096839A (en) * 1989-09-20 1992-03-17 Kabushiki Kaisha Toshiba Silicon wafer with defined interstitial oxygen concentration
JPH0472735A (ja) * 1990-07-13 1992-03-06 Mitsubishi Materials Corp 半導体ウエーハのゲッタリング方法
US5066359A (en) * 1990-09-04 1991-11-19 Motorola, Inc. Method for producing semiconductor devices having bulk defects therein
IT1242014B (it) * 1990-11-15 1994-02-02 Memc Electronic Materials Procedimento per il trattamento di fette di silicio per ottenere in esse profili di precipitazione controllati per la produzione di componenti elettronici.
CA2064486C (en) * 1992-03-31 2001-08-21 Alain Comeau Method of preparing semiconductor wafer with good intrinsic gettering
US5401669A (en) * 1993-05-13 1995-03-28 Memc Electronic Materials, Spa Process for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation centers
US5352615A (en) * 1994-01-24 1994-10-04 Motorola, Inc. Denuding a semiconductor substrate
JP2874834B2 (ja) * 1994-07-29 1999-03-24 三菱マテリアル株式会社 シリコンウェーハのイントリンシックゲッタリング処理法
US5478762A (en) * 1995-03-16 1995-12-26 Taiwan Semiconductor Manufacturing Company Method for producing patterning alignment marks in oxide
US5795809A (en) * 1995-05-25 1998-08-18 Advanced Micro Devices, Inc. Semiconductor wafer fabrication process including gettering utilizing a combined oxidation technique
JPH11168106A (ja) * 1997-09-30 1999-06-22 Fujitsu Ltd 半導体基板の処理方法
WO2000012786A1 (en) * 1998-08-31 2000-03-09 Shin-Etsu Handotai Co., Ltd. Method for producing silicon single crystal wafer and silicon single crystal wafer
JP2000294549A (ja) 1999-02-02 2000-10-20 Nec Corp 半導体装置及びその製造方法
US7081422B2 (en) 2000-12-13 2006-07-25 Shin-Etsu Handotai Co., Ltd. Manufacturing process for annealed wafer and annealed wafer
JP2002184779A (ja) * 2000-12-13 2002-06-28 Shin Etsu Handotai Co Ltd アニールウェーハの製造方法及びアニールウェーハ
TW541581B (en) * 2001-04-20 2003-07-11 Memc Electronic Materials Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
JP4617751B2 (ja) * 2004-07-22 2011-01-26 株式会社Sumco シリコンウェーハおよびその製造方法
JP6118765B2 (ja) * 2014-07-03 2017-04-19 信越半導体株式会社 シリコン単結晶ウェーハの熱処理方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997368A (en) * 1975-06-24 1976-12-14 Bell Telephone Laboratories, Incorporated Elimination of stacking faults in silicon devices: a gettering process
JPS5345177A (en) * 1976-10-06 1978-04-22 Fujitsu Ltd Production of semiconductor device
JPS57117245A (en) * 1981-01-12 1982-07-21 Toshiba Corp Manufacture of semiconductor substrate

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
"Appl. Phys. Lett.", Bd. 29, Nr. 3, 1. August 1976S. 136-138 *
"J. of Appl. Phys.", Bd. 48, Nr. 9, Sept. 1977, S. 4001-4003 *
JP-Z: Japanese Journal of Applied Physics, Vol.23,No.1, 1984, S. L9 - L11 *
US-Z: Solid State Technology, Aug.1983, S.137-142 *
US-Z: Solid State Technology, July 1983, H.7, S. 97-101 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3837270A1 (de) * 1987-11-18 1989-06-01 Intersil Inc Integrierte cmos-schaltung und verfahren zum herstellen derselben
DE19609107A1 (de) * 1995-03-09 1996-09-12 Toshiba Ceramics Co Siliciumwafer mit gesteuerter BMD-Konzentration im Innern und mit guter DZ-Schicht sowie Verfahren zu seiner Herstellung
DE19609107B4 (de) * 1995-03-09 2006-07-27 Toshiba Ceramics Co., Ltd. Verfahren zum Herstellen von Siliziumwafern
CN113421820A (zh) * 2021-06-22 2021-09-21 捷捷半导体有限公司 一种氧化退火方法

Also Published As

Publication number Publication date
DE3439018C2 (https=) 1990-12-06
JPH026223B2 (https=) 1990-02-08
US4661166A (en) 1987-04-28
JPS60133734A (ja) 1985-07-16

Similar Documents

Publication Publication Date Title
DE3439018A1 (de) Verfahren zur herstellung von halbleiterelementen
DE69431385T2 (de) Verfahren zur Herstellung von Silizium-Halbleiterplättchen
DE19609107B4 (de) Verfahren zum Herstellen von Siliziumwafern
DE69515189T2 (de) SOI-Substrat und Verfahren zur Herstellung
DE69122796T2 (de) Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kondensator, wobei polykristallines Silizium mit mikrorauher Oberfläche verwendet wird
DE112008003726B4 (de) Oxidation nach Oxidauflösung
DE69126076T2 (de) Verbundswafer und Verfahren zu dessen Herstellung
DE4323964A1 (de) Halbleitersubstrat und Verfahren zu dessen Behandlung
DE3119886A1 (de) Verfahren zur herstellung eines halbleiterbauelements
DE112016001962T5 (de) Verfahren zur Herstellung von Siliziumepitaxialwafern
EP0939430A2 (de) Herstellverfahren für eine polykristalline Siliziumstruktur
DE3901114A1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE2437430A1 (de) Verfahren zur herstellung monokristalliner niedrigtemperatur-epitaxialbereiche durch umwandlung aus einer amorphen schicht
DE2539073B2 (de) Feldeffekt-Transistor mit isolierter Gate-Elektrode und Verfahren zu dessen Herstellung
DE2422138A1 (de) Verfahren zur herstellung von elektroden aus halbleitermaterial
DE112021001085B4 (de) Herstellungsverfahren für Halbleiter-Siliziumwafer
DE602004007940T2 (de) Bildung einer silicium-germanium-auf-isolator-struktur durch oxidation einer vergrabenen porösen siliciumschicht
DE2225374B2 (de) Verfahren zum herstellen eines mos-feldeffekttransistors
DE112010002935B4 (de) Epitaktischer Siliciumwafer und Verfahren zur Herstellung desselben
DE4391302B4 (de) Verfahren zur Herstellung eines Halbleiters mit einer guten Intrinsic-Getterung
DE102007030321B4 (de) Halbleiterbauelement mit Gatestruktur und Herstellungsverfahren des Halbleiterbauelements
DE112021001083B4 (de) Herstellungsverfahren für Halbleitersiliziumwafer
DE3300716A1 (de) Verfahren zum bilden von monokristallinem silicium auf einer maskenschicht
DE112018001919T5 (de) Verfahren zum herstellen eines siliziumepitaxialwafers und siliziumepitaxialwafer
DE102022211609A1 (de) Siliciumwafer und epitaktischer siliciumwafer

Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8110 Request for examination paragraph 44
D2 Grant after examination
8363 Opposition against the patent
8331 Complete revocation