DE3381768D1 - Mikroschaltung und abdichtungsverfahren. - Google Patents

Mikroschaltung und abdichtungsverfahren.

Info

Publication number
DE3381768D1
DE3381768D1 DE8383903467T DE3381768T DE3381768D1 DE 3381768 D1 DE3381768 D1 DE 3381768D1 DE 8383903467 T DE8383903467 T DE 8383903467T DE 3381768 T DE3381768 T DE 3381768T DE 3381768 D1 DE3381768 D1 DE 3381768D1
Authority
DE
Germany
Prior art keywords
sealing method
micro circuit
micro
circuit
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383903467T
Other languages
English (en)
Inventor
Jeremy D Scherer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of DE3381768D1 publication Critical patent/DE3381768D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/16315—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
DE8383903467T 1982-10-12 1983-10-12 Mikroschaltung und abdichtungsverfahren. Expired - Lifetime DE3381768D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/433,792 US4477828A (en) 1982-10-12 1982-10-12 Microcircuit package and sealing method
PCT/US1983/001582 WO1984001666A1 (en) 1982-10-12 1983-10-12 Microcircuit package and sealing method

Publications (1)

Publication Number Publication Date
DE3381768D1 true DE3381768D1 (de) 1990-08-30

Family

ID=23721546

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383903467T Expired - Lifetime DE3381768D1 (de) 1982-10-12 1983-10-12 Mikroschaltung und abdichtungsverfahren.

Country Status (4)

Country Link
US (1) US4477828A (de)
EP (1) EP0123689B1 (de)
DE (1) DE3381768D1 (de)
WO (1) WO1984001666A1 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701573A (en) * 1985-09-26 1987-10-20 Itt Gallium Arsenide Technology Center Semiconductor chip housing
US4801765A (en) * 1986-01-06 1989-01-31 American Telephone And Telegraph Company, At&T Bell Laboratories Electronic component package using multi-level lead frames
JPS62217645A (ja) * 1986-03-19 1987-09-25 Fujitsu Ltd 半導体装置の製造方法
JPS6363426A (ja) * 1986-09-04 1988-03-19 オリンパス光学工業株式会社 電子内視鏡
US5032692A (en) * 1989-05-09 1991-07-16 Avx Corporation Process for manufactoring hermetic high temperature filter packages and the products produced thereby
US5258647A (en) * 1989-07-03 1993-11-02 General Electric Company Electronic systems disposed in a high force environment
US5058265A (en) * 1990-05-10 1991-10-22 Rockwell International Corporation Method for packaging a board of electronic components
US5051869A (en) * 1990-05-10 1991-09-24 Rockwell International Corporation Advanced co-fired multichip/hybrid package
US5227661A (en) * 1990-09-24 1993-07-13 Texas Instruments Incorporated Integrated circuit device having an aminopropyltriethoxysilane coating
US5451550A (en) 1991-02-20 1995-09-19 Texas Instruments Incorporated Method of laser CVD seal a die edge
US5302553A (en) * 1991-10-04 1994-04-12 Texas Instruments Incorporated Method of forming a coated plastic package
US5323051A (en) * 1991-12-16 1994-06-21 Motorola, Inc. Semiconductor wafer level package
US5336928A (en) * 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
CA2398713A1 (en) * 2000-02-02 2001-08-09 Rutgers, The State University Of New Jersey Programmable surface acoustic wave (saw) filter
AU2002313631A1 (en) * 2001-06-08 2002-12-23 The Regents Of The University Of Michigan A circuit encapsulation technique utilizing electroplating
JP2005500638A (ja) * 2001-08-10 2005-01-06 シーゲイト テクノロジー エルエルシー 集積相互接続とその製造方法
US7723162B2 (en) * 2002-03-22 2010-05-25 White Electronic Designs Corporation Method for producing shock and tamper resistant microelectronic devices
GB2392555A (en) * 2002-09-02 2004-03-03 Qinetiq Ltd Hermetic packaging
US8394679B2 (en) * 2004-05-28 2013-03-12 Stellarray, Inc. Nano-structured gasket for cold weld hermetic MEMS package and method of manufacture
KR100723032B1 (ko) * 2005-10-19 2007-05-30 삼성전자주식회사 고효율 인덕터, 인덕터의 제조방법 및 인덕터를 이용한패키징 구조
US8710618B2 (en) * 2007-03-12 2014-04-29 Honeywell International Inc. Fibrous laminate interface for security coatings
US8310051B2 (en) 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US20100213588A1 (en) * 2009-02-20 2010-08-26 Tung-Hsien Hsieh Wire bond chip package
US20100213589A1 (en) * 2009-02-20 2010-08-26 Tung-Hsien Hsieh Multi-chip package
DE102010036217B4 (de) * 2010-08-27 2014-02-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur hermetischen Verkapselung eines Mikrosystems
US9269685B2 (en) 2011-05-09 2016-02-23 Infineon Technologies Ag Integrated circuit package and packaging methods
US9105562B2 (en) 2011-05-09 2015-08-11 Infineon Technologies Ag Integrated circuit package and packaging methods
US9425116B2 (en) 2011-05-09 2016-08-23 Infineon Technologies Ag Integrated circuit package and a method for manufacturing an integrated circuit package
JP2014197617A (ja) * 2013-03-29 2014-10-16 日本電波工業株式会社 電子デバイス及びその製造方法
DE112015002947A5 (de) 2014-06-23 2017-03-16 Epcos Ag Gehäuse für ein elektrisches Bauelement und Verfahren zur Herstellung eines Gehäuses für ein elektrisches Bauelement

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271634A (en) * 1961-10-20 1966-09-06 Texas Instruments Inc Glass-encased semiconductor
US3489845A (en) * 1965-12-22 1970-01-13 Texas Instruments Inc Ceramic-glass header for a semiconductor device
US3496427A (en) * 1966-01-13 1970-02-17 Gen Electric Semiconductor device with composite encapsulation
US3622419A (en) * 1969-10-08 1971-11-23 Motorola Inc Method of packaging an optoelectrical device
US3706840A (en) * 1971-05-10 1972-12-19 Intersil Inc Semiconductor device packaging
US4198444A (en) * 1975-08-04 1980-04-15 General Electric Company Method for providing substantially hermetic sealing means for electronic components
DE2619433A1 (de) * 1976-05-03 1977-11-10 Siemens Ag Elektrisches bauelement
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
DE2819499C3 (de) * 1978-05-03 1981-01-29 Siemens Ag, 1000 Berlin Und 8000 Muenchen Gehäuse für eine Halbleiteranordnung
US4218701A (en) * 1978-07-24 1980-08-19 Citizen Watch Co., Ltd. Package for an integrated circuit having a container with support bars
JPS5640264A (en) * 1979-09-10 1981-04-16 Hitachi Ltd Semiconductor device
JPS5658249A (en) * 1979-10-19 1981-05-21 Hitachi Ltd Package for integrated circuit
JPS6015152B2 (ja) * 1980-01-09 1985-04-17 株式会社日立製作所 樹脂封止半導体メモリ装置
US4331258A (en) * 1981-03-05 1982-05-25 Raychem Corporation Sealing cover for an hermetically sealed container

Also Published As

Publication number Publication date
EP0123689A4 (de) 1985-11-11
EP0123689A1 (de) 1984-11-07
US4477828A (en) 1984-10-16
WO1984001666A1 (en) 1984-04-26
EP0123689B1 (de) 1990-07-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee