DE3327960A1 - Semiconductor arrangement in an insulating housing - Google Patents

Semiconductor arrangement in an insulating housing

Info

Publication number
DE3327960A1
DE3327960A1 DE19833327960 DE3327960A DE3327960A1 DE 3327960 A1 DE3327960 A1 DE 3327960A1 DE 19833327960 DE19833327960 DE 19833327960 DE 3327960 A DE3327960 A DE 3327960A DE 3327960 A1 DE3327960 A1 DE 3327960A1
Authority
DE
Grant status
Application
Patent type
Prior art keywords
insulating housing
semiconductor
semiconductor arrangement
insulating
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19833327960
Other languages
German (de)
Inventor
Hans-Peter Eberhardt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Electronic GmbH
Original Assignee
Telefunken Electronic GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]

Abstract

In a semiconductor arrangement in an insulating housing comprising a semiconductor body containing one or more semiconductor components, the semiconductor body has, on its surface or on surface layers, conductor tracks which are coated with an insulating layer. The essence of the invention is that a layer of cured photoresist is situated between the material of the insulating housing and the insulating layer covering the conductor tracks. Preferably, the photoresist layer is the one used to produce the connection bonding vias in the insulating layer covering the conductor track system.
DE19833327960 1983-08-03 1983-08-03 Semiconductor arrangement in an insulating housing Ceased DE3327960A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19833327960 DE3327960A1 (en) 1983-08-03 1983-08-03 Semiconductor arrangement in an insulating housing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833327960 DE3327960A1 (en) 1983-08-03 1983-08-03 Semiconductor arrangement in an insulating housing

Publications (1)

Publication Number Publication Date
DE3327960A1 true true DE3327960A1 (en) 1985-02-14

Family

ID=6205631

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833327960 Ceased DE3327960A1 (en) 1983-08-03 1983-08-03 Semiconductor arrangement in an insulating housing

Country Status (1)

Country Link
DE (1) DE3327960A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0275588A1 (en) * 1986-12-19 1988-07-27 Philips Electronics N.V. Method of fabricating a semiconductor device with reduced packaging stress
EP0349001A2 (en) * 1988-06-30 1990-01-03 Kabushiki Kaisha Toshiba Semiconductor device having a stress relief film protected against cracking

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2401613A1 (en) * 1974-01-14 1975-07-17 Siemens Ag Semiconductor device
DE2548060A1 (en) * 1975-10-27 1977-05-12 Siemens Ag A method of manufacturing a semiconductor device
DE2758890B2 (en) * 1977-01-27 1979-08-30 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa (Japan)
DE3116406A1 (en) * 1980-04-25 1982-06-16 Hitachi Ltd A semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2401613A1 (en) * 1974-01-14 1975-07-17 Siemens Ag Semiconductor device
DE2548060A1 (en) * 1975-10-27 1977-05-12 Siemens Ag A method of manufacturing a semiconductor device
DE2758890B2 (en) * 1977-01-27 1979-08-30 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa (Japan)
DE3116406A1 (en) * 1980-04-25 1982-06-16 Hitachi Ltd A semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0275588A1 (en) * 1986-12-19 1988-07-27 Philips Electronics N.V. Method of fabricating a semiconductor device with reduced packaging stress
EP0349001A2 (en) * 1988-06-30 1990-01-03 Kabushiki Kaisha Toshiba Semiconductor device having a stress relief film protected against cracking
EP0349001A3 (en) * 1988-06-30 1990-08-01 Kabushiki Kaisha Toshiba Semiconductor device having a stress relief film protected against cracking

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Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
OP8 Request for examination as to paragraph 44 patent law
8120 Willingness to grant licences paragraph 23
8131 Rejection