DE3307444A1 - Signal processor for processing digital signals - Google Patents

Abstract

For real-time data processing of signal bandwidths up to the Megahertz range, the signal processor has two separate bus systems, an input/output bus and a data bus for internal connection of the individual modules. Both can be used bidirectionally and independently of one another. The signal processor is programmed in a loop-free and direct fashion.

Description

Signal processor for processing digital signals

The invention relates to a signal processor according to the preamble of claim 1.

The main tasks of signal processors are frequency conversion, Filtering, demodulation and LF processing of communications signals. A universal processing of all algorithms within a processor can be achieved by appropriate programming implemented. The signal bandwidths that go through universally programmable processors or signal processors can be processed can, but are relatively low (several kHz). A digital processing of Signals with greater bandwidth will be indisputable in the future, precisely because of the Advantages of digital technology, to be striven for.

Signal processors currently available for sale or announced, such as B. INTEL292O, AMI S2811, NEC PD7720, TMS 320 or the AMD-29500 family have due to your application goals a freely programmable, flexible and meshed architecture. The areas of application are in particular audio and real-time signal processing up to a maximum of 50 kHz in question. Coherent bus structures and multiple use of the individual function groups only allow processing despite the high clock rates of signals with a low sampling rate. Furthermore, integrated analog-to-digital converters reduce and serial interfaces the input and output data rate and thus also the processed Signal bandwidths. The AMD 29500 family allows through parallel bus structures short processing times, but must be cascaded for larger bus widths. Multiple circuits are generally required for large applications.

Two methods are known for programming processors. That The first method uses the program to be saved in an encrypted format Code that is decrypted via an "instruction decoder" and only then the modules is fed. In the second method, the program memory already contains the decrypted Program. One program column is then each for one control line of the circuit responsible. This method is more expensive in terms of storage space, but it is also considerable more quickly.

The object of the invention is to provide a signal processor for processing of digital signals, which real-time data processing for signal bandwidths up to the megahertz range.

The invention is characterized in claim 1. The others Claims contain advantageous developments and developments of the invention.

The invention is explained in more detail below with reference to the figures.

FIG. 1 shows a block diagram of a signal processor according to the invention in an advantageous design. Two separate bus systems, exclusively for data traffic, connect the components of the circuit with each other.

The control information is taken from the program memory directly via separate Lines fed. The signal processor according to the invention is loop-free and programmed directly.

The input / output bus (I / O bus) connects the multiplexed data inputs and outputs of the circuit with the input branch (RAMI1 PMAC) and the output branch (REG). The data bus ensures the internal connection of the modules (PMAC, RAM2, PALU, REG), unlike the I / O bus (16 bits), it is 32 bits wide. Both bus systems have no direct connection, are bidirectional and can be independent of each other to be used.

The I / O bus takes the input data from the signal processor with a high data rate. Depending on the application, this can be half the clock frequency a few megahertz. The buffer memory RAM1 and the multiplier-accumulator PMAC can record the data both individually and simultaneously. In the time slots between the data acceptance, calculated data can be sent via the output register REG are issued.

After data processing in the PMAC module, the data transferred to the data bus at a reduced data rate depending on the application. All Modules connected to this bus can send the data individually or simultaneously take over.

The multiplier-accumulator PMAC (Pipeline-Multipli.er and Accumulator) is, as the name suggests, a multiplier M with a downstream accumulator (ADD, R3, R4 and feedback loop). To increase the possible clock frequency the data is processed in a pipeline process. FIG. 2 shows a block diagram of FIG Module.

The PMAC is particularly suitable for mixing and filtering tasks. Compared to known multiplier-accumulator circuits, the PMAC has a second register (R4) in the accumulation loop. This enables simple processing of complex signal values. They can be nested in one another, processed in a time division multiplex. The following algorithm can be represented: with h (v) = coefficients x (v) = data y (v) = output.

The subtotals of the real and imaginary parts are located alternately in the accumulation registers R3 and R4.

If only one multiplication is required, the feedback can increase to "Zero" can be set. A pen at 4 bi. S in Direction ~ rust Significant Bit "(MSB) in the parallel shift register SHIFT can be activated by hiding the overflow points increase the accuracy, especially only in the case of multiplications.

Data calculated in the PMAC can be sent to the buffer via the data bus RAM2, and / or the output register R £ G and / or for further calculation to the arithmetic and logic unit PALU.

The arithmetic-logic unit PALU (Pipeline-Arithmetic-Logic-Unit) allows different arithmetic and logical combinations of two data with 32 bit word format. The processing is in turn done through the use of the pipeline technique accelerated. A block diagram of the unit is shown in FIG. 3 shown. The logical one Switching mechanism ALU, the SHIFTER, the limiter Beg and several register blocks Regl bis Reg5 form the function blocks of the PALU. A module-internal bus system with 32 Bit word format connects the modules with one another. The ALU can have the sequence shown in FIG. 3 execute specified functions, the SHIFTER allows a shift of the 32 bit Data word by O - 31 bits in the direction of the "Least Significant Bit" (LSB), the register blocks are used to temporarily store data that is required within a computing cycle will. Output Y and inputs A and B of the ALU are connected via a feedback loop connected with each other.

If the limiter Beg is switched on, the data is then transferred to the largest or smallest number with a Word format limited to 29 bits, if the output value of the ALU exceeds or falls below this format.

The PALU module is particularly suitable for recursive filtering. The multiplications necessary for this are carried out in elementary operations, i. H. Additions, Subtractions and shift operations broken down.

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Claims (7)

Patent claims signal processor for processing digital signals, with multipliers, adders, registers, memories and a program memory, characterized in that two separate bus systems are provided, each of which are bidirectional, have no direct connection with each other and are independent can be used by each other, with the first bus system as an input / output bus (I / O bus) of the signal processor and the second as a data bus (DATA bus) internally the individual Components of the signal processor connects (FIG. 1). 2. Signal processor according to claim 1, characterized in that the individual assemblies control information from the program memory directly via separate Lines are fed. 3. Signal processor according to claim 1, characterized in that it essentially from a buffer memory (RAM1) in the input, an output register (REG), a multiplier-accumulator (PMAC), a buffer (RAM2) and an arithmetic and logic unit (PALU) (FIG. i). 4. Signal processor according to claim 3, characterized in that the Input / output bus (I / O bus) the multiplexed data inputs and outputs of the signal processor with the buffer memory (RAM1), the inputs of the multiplier-accumulator (PMAC) and the outputs of the output register (REG) and that the data bus (DATEN-BUS) the outputs of the multiplier-accumulator (PMAC) with the buffer (RAM2), the arithmetic-logic unit (PALU) and the inputs of the output register (REG) connects (FIG. 1). 5. Signal processor according to claim 3, characterized in that the Multiplier-Accumulator (PMAC) and the arithmetic-logic unit (PALU) according to work the pipeline process. 6. Signal processor according to one of the preceding claims, characterized characterized in that the multiplier-accumulator (PMAC) from the series connection of a multiplier (M) in the inputs of each register (R1, R2) arranged are, an adder (ADD) with an accumulation loop in which one after the other two accumulation registers (R3, R4) are arranged, and a parallel shift register (PIN) (FIG. 2). 7. Signal processor according to one of claims 1 to 5, characterized in that that the arithmetic-logic unit (PALU) with a logic switching unit (ALU) has two inputs A and B and one output Y, in which a limiter (Beg) is arranged that the output Y and the inputs A and B of the logic switching mechanism (ALU) are connected to one another via a feedback loop that in input A several register blocks Regi to Reg5) and in input B a parallel shift register (SHIFTER) are arranged, and that the logic switching unit (ALU) the following links can perform: Y = A + B Y = A-B Y = B-A Y = A Y = -A Y = B Y = -B Y = o (FIG. 3).