DE3279599D1 - Stacked semiconductor memory - Google Patents

Stacked semiconductor memory

Info

Publication number
DE3279599D1
DE3279599D1 DE8282107858T DE3279599T DE3279599D1 DE 3279599 D1 DE3279599 D1 DE 3279599D1 DE 8282107858 T DE8282107858 T DE 8282107858T DE 3279599 T DE3279599 T DE 3279599T DE 3279599 D1 DE3279599 D1 DE 3279599D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
stacked semiconductor
stacked
memory
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282107858T
Other languages
English (en)
Inventor
Masaharu Toyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3279599D1 publication Critical patent/DE3279599D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8282107858T 1981-08-31 1982-08-26 Stacked semiconductor memory Expired DE3279599D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56136399A JPS5837948A (ja) 1981-08-31 1981-08-31 積層半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3279599D1 true DE3279599D1 (en) 1989-05-11

Family

ID=15174249

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282107858T Expired DE3279599D1 (en) 1981-08-31 1982-08-26 Stacked semiconductor memory

Country Status (3)

Country Link
EP (1) EP0073486B1 (de)
JP (1) JPS5837948A (de)
DE (1) DE3279599D1 (de)

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JPS6185858A (ja) * 1984-10-04 1986-05-01 Nec Corp 半導体記憶装置
US4742474A (en) * 1985-04-05 1988-05-03 Tektronix, Inc. Variable access frame buffer memory
JPS62208665A (ja) * 1986-03-07 1987-09-12 Mitsubishi Electric Corp 積層形半導体記憶装置
JPS62219550A (ja) * 1986-03-19 1987-09-26 Sharp Corp 半導体記憶素子
US5515267A (en) * 1986-04-04 1996-05-07 Alsenz; Richard H. Apparatus and method for refrigeration system control and display
US5191643A (en) * 1986-04-04 1993-03-02 Alsenz Richard H Method and apparatus for refrigeration control and display
EP0257987B1 (de) * 1986-08-22 1991-11-06 Fujitsu Limited Halbleiter-Speicheranordnung
JPS63204595A (ja) * 1987-02-20 1988-08-24 Fujitsu Ltd マルチプレ−ンビデオｒａｍ構成方式
JPS63245567A (ja) * 1987-03-31 1988-10-12 Toshiba Corp 画像処理装置
JP2778977B2 (ja) * 1989-03-14 1998-07-23 株式会社東芝 半導体装置及びその製造方法
EP0420339A3 (en) * 1989-09-29 1992-06-03 N.V. Philips' Gloeilampenfabrieken Multi-plane random access memory system
US5099309A (en) * 1990-04-30 1992-03-24 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
EP0516866A1 (de) * 1991-05-03 1992-12-09 International Business Machines Corporation Modulare mehrschichtige Verbindungsstruktur
US5818112A (en) * 1994-11-15 1998-10-06 Siemens Aktiengesellschaft Arrangement for capacitive signal transmission between the chip layers of a vertically integrated circuit
US5701037A (en) * 1994-11-15 1997-12-23 Siemens Aktiengesellschaft Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit
FR2745973B1 (fr) * 1996-03-08 1998-04-03 Thomson Csf Memoire de masse et procede de fabrication de memoire de masse
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6483736B2 (en) 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US8575719B2 (en) 2000-04-28 2013-11-05 Sandisk 3D Llc Silicon nitride antifuse for use in diode-antifuse memory arrays
EP1284017A4 (de) 2000-04-28 2008-10-08 Matrix Semiconductor Inc Dreidimensionales speicherarray und verfahren zur herstellung
CN100358147C (zh) 2000-08-14 2007-12-26 矩阵半导体公司 密集阵列和电荷存储器件及其制造方法
US20030120858A1 (en) 2000-09-15 2003-06-26 Matrix Semiconductor, Inc. Memory devices and methods for use therewith
US6591394B2 (en) 2000-12-22 2003-07-08 Matrix Semiconductor, Inc. Three-dimensional memory array and method for storing data bits and ECC bits therein
US6486065B2 (en) 2000-12-22 2002-11-26 Matrix Semiconductor, Inc. Method of forming nonvolatile memory device utilizing a hard mask
US6486066B2 (en) 2001-02-02 2002-11-26 Matrix Semiconductor, Inc. Method of generating integrated circuit feature layout for improved chemical mechanical polishing
US7352199B2 (en) 2001-02-20 2008-04-01 Sandisk Corporation Memory card with enhanced testability and methods of making and using the same
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6843421B2 (en) 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US6593624B2 (en) 2001-09-25 2003-07-15 Matrix Semiconductor, Inc. Thin film transistors with vertically offset drain regions
US6624485B2 (en) 2001-11-05 2003-09-23 Matrix Semiconductor, Inc. Three-dimensional, mask-programmed read only memory
DE60205569T2 (de) * 2001-12-21 2006-05-18 Kabushiki Kaisha Toshiba MRAM mit gestapelten Speicherzellen
US6731011B2 (en) 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
US6853049B2 (en) 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
US6643159B2 (en) 2002-04-02 2003-11-04 Hewlett-Packard Development Company, L.P. Cubic memory array
US6687147B2 (en) * 2002-04-02 2004-02-03 Hewlett-Packard Development Company, L.P. Cubic memory array with diagonal select lines
US6737675B2 (en) 2002-06-27 2004-05-18 Matrix Semiconductor, Inc. High density 3D rail stack arrays
DE10308323B4 (de) * 2003-02-26 2007-10-11 Infineon Technologies Ag Halbleiterchipanordnung mit ROM
US6879505B2 (en) 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
US7233024B2 (en) 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
WO2004100267A1 (en) * 2003-04-03 2004-11-18 Hewlett-Packard Development Company, L.P. Cubic memory array
US7184289B2 (en) * 2003-11-12 2007-02-27 Intel Corporation Parallel electrode memory
US7272052B2 (en) 2005-03-31 2007-09-18 Sandisk 3D Llc Decoding circuit for non-binary groups of memory line drivers
US7359279B2 (en) 2005-03-31 2008-04-15 Sandisk 3D Llc Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
US7142471B2 (en) 2005-03-31 2006-11-28 Sandisk 3D Llc Method and apparatus for incorporating block redundancy in a memory array
US7054219B1 (en) 2005-03-31 2006-05-30 Matrix Semiconductor, Inc. Transistor layout configuration for tight-pitched memory array lines
US7420832B1 (en) * 2007-04-30 2008-09-02 International Business Machines Corporation Array split across three-dimensional interconnected chips
US8907392B2 (en) * 2011-12-22 2014-12-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device including stacked sub memory cells
US8704221B2 (en) * 2011-12-23 2014-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20150063039A1 (en) * 2013-08-29 2015-03-05 Taiwan Semiconductor Manufacturing Company Ltd. Redundancy in stacked memory structure
US9875789B2 (en) 2013-11-22 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. 3D structure for advanced SRAM design to avoid half-selected issue
US9478495B1 (en) 2015-10-26 2016-10-25 Sandisk Technologies Llc Three dimensional memory device containing aluminum source contact via structure and method of making thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2022895B2 (de) * 1970-05-11 1976-12-02 Siemens AG, 1000 Berlin und 8000 München Stapelfoermige anordnung von halbleiterkoerpern und verfahren zu deren herstellung
DE2806685A1 (de) * 1978-02-16 1979-08-23 Siemens Ag Stapelbauweise fuer halbleiter- speicherbausteine
JPS5852345B2 (ja) * 1978-09-01 1983-11-22 パイオニア株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP0073486A3 (en) 1986-03-26
EP0073486B1 (de) 1989-04-05
JPS5837948A (ja) 1983-03-05
EP0073486A2 (de) 1983-03-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee