DE3279521D1 - Memory circuit - Google Patents

Memory circuit

Info

Publication number
DE3279521D1
DE3279521D1 DE8282109932T DE3279521T DE3279521D1 DE 3279521 D1 DE3279521 D1 DE 3279521D1 DE 8282109932 T DE8282109932 T DE 8282109932T DE 3279521 T DE3279521 T DE 3279521T DE 3279521 D1 DE3279521 D1 DE 3279521D1
Authority
DE
Germany
Prior art keywords
memory circuit
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282109932T
Other languages
German (de)
English (en)
Inventor
Kohichiro Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3279521D1 publication Critical patent/DE3279521D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
DE8282109932T 1981-10-27 1982-10-27 Memory circuit Expired DE3279521D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56171679A JPS5873097A (ja) 1981-10-27 1981-10-27 デコ−ダ−回路

Publications (1)

Publication Number Publication Date
DE3279521D1 true DE3279521D1 (en) 1989-04-13

Family

ID=15927682

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282109932T Expired DE3279521D1 (en) 1981-10-27 1982-10-27 Memory circuit

Country Status (4)

Country Link
US (1) US4520463A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0078502B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5873097A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3279521D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059588A (ja) * 1983-09-12 1985-04-05 Hitachi Ltd 半導体記憶装置
FR2581231B1 (fr) * 1985-04-26 1991-05-03 Eurotechnique Sa Memoire morte programmable electriquement
FR2587531B1 (fr) * 1985-04-26 1991-04-26 Eurotechnique Sa Memoire morte programmable electriquement une seule fois
US4670748A (en) * 1985-08-09 1987-06-02 Harris Corporation Programmable chip select decoder
JPH0715800B2 (ja) * 1987-02-27 1995-02-22 日本電気アイシーマイコンシステム株式会社 記憶回路
JP2603206B2 (ja) * 1987-03-16 1997-04-23 シーメンス、アクチエンゲゼルシヤフト 多段集積デコーダ装置
JPH0766669B2 (ja) * 1988-02-19 1995-07-19 日本電気株式会社 デコーダバッファ回路
JPH029098A (ja) * 1988-06-27 1990-01-12 Nec Corp 読出専用半導体記憶装置
US4954731A (en) * 1989-04-26 1990-09-04 International Business Machines Corporation Wordline voltage boosting circuits for complementary MOSFET dynamic memories
US7613991B1 (en) 2003-08-19 2009-11-03 Altera Corporation Method and apparatus for concurrent calculation of cyclic redundancy checks
US7320101B1 (en) * 2003-08-19 2008-01-15 Altera Corporation Fast parallel calculation of cyclic redundancy checks

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909808A (en) * 1974-12-23 1975-09-30 Ibm Minimum pitch mosfet decoder circuit configuration
US4264828A (en) * 1978-11-27 1981-04-28 Intel Corporation MOS Static decoding circuit
US4447895A (en) * 1979-10-04 1984-05-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4259731A (en) * 1979-11-14 1981-03-31 Motorola, Inc. Quiet row selection circuitry
JPS57117168A (en) * 1981-01-08 1982-07-21 Nec Corp Memory circuit

Also Published As

Publication number Publication date
EP0078502B1 (en) 1989-03-08
JPH026159B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-02-07
JPS5873097A (ja) 1983-05-02
US4520463A (en) 1985-05-28
EP0078502A2 (en) 1983-05-11
EP0078502A3 (en) 1986-01-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee