DE3277265D1 - Procedure for manufacturing integrated circuit devices having sub-micrometer dimension elements, and resulting structure - Google Patents

Procedure for manufacturing integrated circuit devices having sub-micrometer dimension elements, and resulting structure

Info

Publication number
DE3277265D1
DE3277265D1 DE8282111972T DE3277265T DE3277265D1 DE 3277265 D1 DE3277265 D1 DE 3277265D1 DE 8282111972 T DE8282111972 T DE 8282111972T DE 3277265 T DE3277265 T DE 3277265T DE 3277265 D1 DE3277265 D1 DE 3277265D1
Authority
DE
Germany
Prior art keywords
sub
procedure
integrated circuit
circuit devices
resulting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282111972T
Other languages
German (de)
English (en)
Inventor
Robert Charles Dockerty
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3277265D1 publication Critical patent/DE3277265D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/01328—Aspects related to lithography, isolation or planarisation of the conductor by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
DE8282111972T 1981-12-30 1982-12-27 Procedure for manufacturing integrated circuit devices having sub-micrometer dimension elements, and resulting structure Expired DE3277265D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/335,891 US4430791A (en) 1981-12-30 1981-12-30 Sub-micrometer channel length field effect transistor process

Publications (1)

Publication Number Publication Date
DE3277265D1 true DE3277265D1 (en) 1987-10-15

Family

ID=23313652

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282111972T Expired DE3277265D1 (en) 1981-12-30 1982-12-27 Procedure for manufacturing integrated circuit devices having sub-micrometer dimension elements, and resulting structure

Country Status (4)

Country Link
US (1) US4430791A (https=)
EP (1) EP0083784B1 (https=)
JP (1) JPS58118157A (https=)
DE (1) DE3277265D1 (https=)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4532698A (en) * 1984-06-22 1985-08-06 International Business Machines Corporation Method of making ultrashort FET using oblique angle metal deposition and ion implantation
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
US4654119A (en) * 1985-11-18 1987-03-31 International Business Machines Corporation Method for making submicron mask openings using sidewall and lift-off techniques
DE3602461A1 (de) * 1986-01-28 1987-07-30 Telefunken Electronic Gmbh Verfahren zum herstellen eines sperrschicht-feldeffekttransistors
US4689869A (en) * 1986-04-07 1987-09-01 International Business Machines Corporation Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length
US5223914A (en) * 1989-04-28 1993-06-29 International Business Machines Corporation Follow-up system for etch process monitoring
EP0394597A1 (en) * 1989-04-28 1990-10-31 International Business Machines Corporation Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns
USH986H (en) * 1989-06-09 1991-11-05 International Business Machines Corporation Field effect-transistor with asymmetrical structure
JPH0756892B2 (ja) * 1989-06-20 1995-06-14 三菱電機株式会社 半導体装置
US5362662A (en) * 1989-08-11 1994-11-08 Ricoh Company, Ltd. Method for producing semiconductor memory device having a planar cell structure
EP0416141A1 (de) * 1989-09-04 1991-03-13 Siemens Aktiengesellschaft Verfahren zur Herstellung eines FET mit asymmetrisch angeordnetem Gate-Bereich
JPH09116009A (ja) * 1995-10-23 1997-05-02 Sony Corp 接続孔の形成方法
US5801088A (en) * 1996-07-17 1998-09-01 Advanced Micro Devices, Inc. Method of forming a gate electrode for an IGFET
US6040214A (en) * 1998-02-19 2000-03-21 International Business Machines Corporation Method for making field effect transistors having sub-lithographic gates with vertical side walls
US6191446B1 (en) 1998-03-04 2001-02-20 Advanced Micro Devices, Inc. Formation and control of a vertically oriented transistor channel length
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6258679B1 (en) 1999-12-20 2001-07-10 International Business Machines Corporation Sacrificial silicon sidewall for damascene gate formation
US6683337B2 (en) * 2001-02-09 2004-01-27 Micron Technology, Inc. Dynamic memory based on single electron storage
CN100585835C (zh) * 2008-09-12 2010-01-27 西安电子科技大学 基于多层辅助结构制备多晶SiGe栅纳米级CMOS集成电路方法
CN110429030B (zh) * 2019-07-30 2022-04-01 中国电子科技集团公司第十三研究所 纳米栅及纳米栅器件的制备方法
CN119653820B (zh) * 2025-02-14 2025-06-03 清华大学 一种垂直亚1nm栅长场效应晶体管及制备方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4062699A (en) * 1976-02-20 1977-12-13 Western Digital Corporation Method for fabricating diffusion self-aligned short channel MOS device
US4195307A (en) * 1977-07-25 1980-03-25 International Business Machines Corporation Fabricating integrated circuits incorporating high-performance bipolar transistors
US4182023A (en) * 1977-10-21 1980-01-08 Ncr Corporation Process for minimum overlap silicon gate devices
US4128670A (en) * 1977-11-11 1978-12-05 International Business Machines Corporation Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
US4145459A (en) * 1978-02-02 1979-03-20 Rca Corporation Method of making a short gate field effect transistor
US4251571A (en) * 1978-05-02 1981-02-17 International Business Machines Corporation Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
GB2021863B (en) * 1978-05-26 1983-02-02 Rockwell International Corp Method of making integrated circuits
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4201603A (en) * 1978-12-04 1980-05-06 Rca Corporation Method of fabricating improved short channel MOS devices utilizing selective etching and counterdoping of polycrystalline silicon
US4211582A (en) * 1979-06-28 1980-07-08 International Business Machines Corporation Process for making large area isolation trenches utilizing a two-step selective etching technique
JPS56115560A (en) * 1980-02-18 1981-09-10 Toshiba Corp Manufacture of semiconductor device
US4312680A (en) * 1980-03-31 1982-01-26 Rca Corporation Method of manufacturing submicron channel transistors
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices

Also Published As

Publication number Publication date
EP0083784A2 (en) 1983-07-20
EP0083784B1 (en) 1987-09-09
US4430791A (en) 1984-02-14
EP0083784A3 (en) 1985-01-23
JPS6249750B2 (https=) 1987-10-21
JPS58118157A (ja) 1983-07-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee