DE3212945A1 - Semiconductor memory cell comprising two field-effect transistors - Google Patents

Abstract

The invention relates to a semiconductor memory cell comprising two field-effect transistors and an arrangement in which said cells are used. The object of the invention is to provide a semiconductor memory cell having novel qualitative features and thereby make it possible to achieve VLSI semiconductor memories, and to provide a memory cell whose readability is not impaired by a higher degree of integration and which makes it possible to exceed the reading speeds hitherto known. The memory cells are to be arranged to form a semiconductor memory and the advantageous technical implementation of the memory is to be specified. According to the invention, the object is achieved in that a field-effect transistor, transfer transistor (Tt), is equipped with a memory gate for information storage, said memory gate is connected directly to the drain/source region of a second field-effect transistor, the charge transistor (TL), both transistors (Tt and TL) are connected to the bit line, the second electrode of the transistor (Tt) is connected to the operating voltage (UB), and the capacitors (C2 and C2<x>) of the gates of the transistors (Tt and TL) are linked to the word line. <IMAGE>

Description

Title of the invention

Semiconductor memory element with two field effect transistors.

Field of application of the invention The invention relates to a semiconductor memory element with two field effect transistors and an arrangement in which these elements are used will.

These storage elements are used in particular in the field the integrated semiconductor memory for electronic computers and data processing systems.

Characteristics of the known technical solutions Highly integrated dynamic semiconductor memories store the information as charge on a capacity. This basic principle is described in US Pat. No. 3,387,286. In the Polge period this solution was modified several times, but the main ones are still today Features of this principle in all manufactured dynamic semiconductor memory cells and thus the basic building block of highly integrated dynamic semiconductor memories. The advantage of these memory cells is their small footprint and use justified by just one pelde effect transistor for realizing the memory cell.

A further minimization of the memory cell, due to the increasing Degree of integration, inevitably results in a reduction in the stored charge. To read this small charge, high-sensitivity sensor amplifiers are required; at the same time, the time to read the memory cell increases, provided the reading is still clearly possible at all.

In addition, the relative susceptibility to failure increases, e.g. against t, c- Radiation.

OBJECT OF THE INVENTION The object of the invention is to provide a semiconductor memory cell to create with new qualitative features and thereby the realization of highly integrated To enable semiconductor memory.

Statement of the essence of the invention The object of the invention is is to create a memory cell that is characterized by a higher degree of integration readability is not impaired and the exceeding of the previously known Reading speed permitted. It is a mapping of the memory cells to one To fix semiconductor memory and the advantageous technical realization of the Specify memory.

According to the invention the object is achieved in that a selde-effect transistor, Transfer transistor T., equipped with a memory gate for storing information is, this memory gate has a direct connection to the Drain / Sourcogebiwt of a second field effect transistor, the charging transistor TL, has both transistors Tt and TL are connected to the bit line, the second electrode of the transistor Tt is performed on the operating voltage U3, from the gates of the transistor Tt and TL the capacitances C2 and C2X are linked to the word line, furthermore the semiconductor memory cell Controlled, read and written with only one bit line and one word line by connecting both transistors with their drain / source regions to one bit line and with their control gates to which a word line is connected.

The word selection line (word line) is controlled in one Variant through control voltages with 2 levels (high-low) and in another Variant with 3 levels (high-medium-low).

The two capacities C2 and C2X are realized through use of two polycrystalline silicon layers, creating a flexible dimensioning this capacity is possible.

The standard technology of n-channel silicon guest technology is used for production with 7.W9i levels of tolycrystalline silicon layers, applied.

EXEMPLARY EMBODIMENT The invention is intended below using an exemplary embodiment are explained in more detail. The accompanying drawings show: Fig. 1: Circuit of the Memory cell with two field effect transistors Fig. 2: Exemplary embodiments (layouts) in n-channel silicon gate technology with two polycrystalline silicon levels with diffused bit line (variant 1).

3: Exemplary embodiments (layouts) in n-channel silicon gate technology with two polycrystalline silicon levels with metal bit line (variant 2).

The semiconductor memory cell consists of two field effect transistors, 1 to a bit line for inputting and outputting the information, a word line to select the memory cell for reading and writing and the operating voltage UB are connected.

The bit line can have the two binary voltage levels high (UBH) and Assume 1, Low "(UBL). Word line W will have two or three voltage levels controlled, low (UWL> i.e.

the storage cell is not addressed), means (UwM, the storage cell should only be read), high (UwH, the memory cell should be written, read or the content should be refreshed).

The drain / source electrode of transistor 2 is connected to the gate of the Transistor 1 connected. The two transistors 1 and 2 are across the bit line and the memory gate are connected and thus form a feedback that is called internal Current source acts when the word line is reading the information in the memory element is activated. The capacities C2 and C2X, for example, very easily between two Polykristallinen.Siliziurnschichten are realized, are used to adjust the Different switch-on thresholds of the transistors required for the function 1 and 2. The semiconductor memory element is integrated in a matrix, dynamic Read / write Integrated memory with random access. Below the functions of the semiconductor memory element are explained.

The writing of the semiconductor memory element is enabled by a high Voltage level UWH on the word line activated by turning on transistor 2 and transmits the voltage level on the bit line to the gate of transistor 1. If there is a high voltage level UBH on the bit line, the gate of the transistor becomes 1 charged. This corresponds to the binary memory status H. Is on the bit line a low voltage level UBL, the gate of transistor 1 is discharged, whereby the binary storage state L arises.

When reading, the bit line is initially at a low voltage level UBLL discharged. Then the semiconductor memory element is through an intermediate voltage level UWM or a high voltage level UWH (depending on the dimensioning of the components of the memory element according to FIG. 1) activated by turning on transistor 1 when the semiconductor memory element is in the binary memory state H or not turns on when the semiconductor memory element is in the memory state L. In the memory state H, part of the operating voltage is supplied via the transistor 1 that is switched on UB transferred to the bit line, which causes the high read voltage level UBHL there arises.

If the semiconductor memory element was in the state, there is no voltage from U3 to the bit line, since transistor 1 is switched off in this case remain. The bit line remains at a low read voltage level UBL.

In Fig. 2 and Fig. 3 there are two examples of technological implementation with the standard silicon gate technology with polycrystalline silicon layers shown. The two transistors are made with gates in the poly 1 plane. The two capacitances C2 and C2X result from the crossing of the poly 2 plane with the poly 1 - level, whereby by the choice of the surface and oxide thickness ratios the necessary flexibility in the dimensioning of these capacities is made possible. The poly 2 plane also forms the word line. The bit line will either out as a diffused area (Fig. 2) or as a metal layer (Fig. 3). These Possibility can also be used for the UB supply voltage, which is in the Examples out of Fig. 2 and Fig. 3 as a diffused area will.

The variant 1 in Fig. 2 has the advantage that no bit line contact per semiconductor memory element is required. The variant 2 in Fig. 3 has the The advantage is that the area consumption and the RC time constant of the bit line are smaller is.

Result of the preliminary examination a) It was researched GDR, BRD, USA in sections G and H G 11 C 7/00 H 01 L 29/76 8/00 29/78 11/24 11/40 b) The following patent specification was considered: US-PS 338 7286 June 4, 1968 Fielt-effect transistor memory Dennard, R.H.

c) Not applicable d) The most important solution was in the characteristics called the known technical solutions.

e) Highly integrated semiconductor memories in particular using MOS technology dynamic memories for electronic computers.

:) The circuit offers the possibility of the degree of integration and to increase the quality of dynamic semiconductor memories and their readability of memory.

Sensor amplifiers for reading the memory are not required because the memory cell itself acts as a current source in the activated state.

g) Trial results on a practical circuit are still available not before.

Claims (4)

Invention claim 1. Semiconductor memory element with two field effect transistors characterized in that the field effect transistor (1), transfer transistor Tt, is equipped with a memory gate for information storage, this memory gate a direct connection to the drain / source region of the field effect transistor (2), Charging transistor T 1 has both transistors (1) and (2) connected to the bit line are, the second electrode of the transistor (1) to the operating voltage l, out and from the gates of transistors (1) and (2) the capacitances C2 and C2X with the word line are linked, furthermore the semiconductor memory cell with only one '3itleitung and a wordline is controlled, read and written by the transistors (1) and (2) with their drain / source regions to the one bit line and with their gates to which a word line is connected. 2. Semiconductor memory element according to item 1, characterized in that that the control of the word selection line (word line) in a variant by control voltages with 2 levels (high-low) and in another variant with 3 levels (high-medium-low) he follows, 3. Semiconductor memory element according to item 1, characterized in that the Realization of the two capacities C2 and C2X through the use of two polycrystalline ones Silicon layers takes place. 4. Semiconductor memory element according to item 1 to 3, characterized in that that the standard technology of the n-channel silicon gate technology, with two levels of polycrystalline silicon layers, is applied.