DE3147932A1 - "ARRANGEMENT WITH INTEGRATED, HIGH INTEGRATION DENSITY - Google Patents

Description

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Patent attorneys 3U7932 Dipl.-Ing. Dipl.-Chem. G. Quieter Dipl.-Ing. Dr. G. Hauser E. Prince Ernsbergerstrasse 19 8 Munich 60 H

2nd December 1981

COMPAGNIE INTERNATIONAL POUR L'INFORMATIQÜE

CII HONEYWELL BULL

94 Avenue Gambetta

75020 Paris / France

Our reference: C 3309

Arrangement with integrated circuits of high integration density

The invention relates to an arrangement with or from integrated circuits of high integration density, in particular according to the preamble of claim 1.

Arrangements with or from integrated circuits, hereinafter referred to as integrated circuits for short, are customary made of a monolithic "substrate disc", which in Anglo-Saxon usage is called a "slice" or "wafer" and cut from a cylindrical rod of semiconductor material. On one side of the disk, integrated circuits of the same type are formed in a matrix arrangement by diffusion and metallization. The slice is then cut along perpendicular axes that define the matrix around the individual integrated To separate circuits from each other.

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In order to increase the miniaturization of these arrangements, the technique of "large group integration" or integration is used applied with high packing density, referred to in the Anglo-Saxon literature as "Large Scale Integration" (LSI) will. This technique initially consisted of placing each component of an array in a surface of the substrate to form by diffusion and to apply a metallic connecting network in the form of one or more superimposed layers, to connect the components to each other and to the input / output connections of the device. This technique is described, for example, in U.S. Patent 3,484,932.

In a further stage of development, they were then diffused in Elements organized by cells, the cells representing a given logic function. This is for example, in U.S. Patents 3,771,217 and 3,835,530.

With this technique, different types of integrated circuits can be formed from the same diffusion pattern. The different types differ through their connection network, which is formed by a metallization that diffused in different Connect elements of the same circuit together. The cell-by-cell organization enables better localization the elements with a view to the design and implementation of the interconnection network. The fact that at least a part of the cells in the conventional integrated circuits forms a predetermined functional unit and that components of the cells are specific for a predetermined function, however, largely limits the number of Ways of forming different types of circuits from the same diffusion pattern.

The object of the invention is in particular to remedy the deficiency explained above.

An arrangement according to the invention with or from integrated High density circuitry includes a substrate, cells formed in a surface of the substrate, which each contain a group of components, and a metallic interconnection network that is on said surface of the substrate is formed in order to connect the components and / or cells to one another, and is characterized in that that the cells are arranged in the form of a matrix and in each case with regard to the number, characteristics and relative arrangement have the same grouping of components within the cell that the components of one and the same cell as well as possibly from neighboring cells are connected by a first connection sub-network of the metallic network and thus form a block that has a predetermined logic function represents, and that the metallic network contains a second interconnection sub-network to interconnect the blocks connect to. ■,

Further features and advantages of the invention emerge from the following description of exemplary embodiments below Referring to the drawing. In the drawing show:

1 shows a schematic plan view of an exemplary embodiment of the integrated circuit according to the invention with high integration density without their metallic interconnection network;

FIG. 2 is a schematic view of an embodiment showing the composition of a cell of the one shown in FIG Circuit can be recognized;

3 is a schematic plan view of a cell, with an example of the relative arrangement of the available There is shown connection surfaces of a cell containing the components shown in FIG. 2;

Fig. 4 is a plan view of a cell similar to that of Fig. 3, with details of the in Components diffused into the substrate of the cell are shown;

FIGS. 5A and 5B show an application example for the components of a cell according to FIGS. 2, 3 and 4;

6 shows a schematic representation of the matrix division of the cells according to FIG. 1, the respective predetermined Logic functions are shown as blocks, with the various metallic required Connections for producing the arrangement according to the invention;

Figure 7 is a schematic plan view showing the details of the interconnections to form a block in accordance with the principles of the present invention; and

8 shows a schematic plan view of an embodiment of the connections of a metallic network according to FIG the invention.

The exemplary embodiment of an integrated circuit 10 according to the invention with a high integration density shown in FIG. 1 essentially contains an approximately square substrate 11 with a side length of approximately 6 mm, with two adjacent sides defining ^{an orthogonal axis system X 1} X, Y ^{1 Y.} A main surface 12 of the substrate 11 contains the electrical circuit elements of the arrangement or circuit 10. These elements include the input / output terminals 13 of the circuit 10, which are arranged on the circumference of the surface 12 and of which, in the example shown, are provided on each side 40 are, as well as the information

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tion processing unit 1.4. In a conventional manner, this unit 14 works together with the input / output connections 13, either directly to take the supply voltages of the circuits from them, or via buffer circuits 15, which serve as interfaces for the digital signals and form both power amplifiers and impedance adapters. For these reasons, the buffer circuits are aligned in parallel with the terminals 13 and arranged between them and the unit 14 as shown in the drawing. In a practical embodiment, 140 such buffer circuits are provided. The arrangement 10 also contains generator circuits 16 for a predetermined operating voltage V ₀ . In the example shown, the generator circuits 16 are aligned with the buffer circuits 15 and supply these and the other circuits of the unit 14 with a voltage V _Q.

The information processing unit 14 of the arrangement 10 is located within the frame established by the buffer circuits 15 and the generator circuits 16 is formed, and is formed in a conventional manner from cells 17, the each form a group of electronic components that are in the surface 12 of the substrate 11 are diffused. The invention is independent of the respective technology of the processing circuits and is only used as an example the so-called CML technology (Current Mode Logic).

According to the invention, the cells 17 are all identical to one another and arranged in a matrix of the type shown in FIG. In particular, each cell contains 17 with respect to the respective Number, characteristics and relative arrangement within a cell are the same grouping of components. Fig. 2 shows an embodiment of the composition of a cell 17, which is suitable for the CML technology. The cell shown

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17 is inscribed in a square whose side length is 250 ym, and to their devices include bipolar transistors 12 18 (18, ... 18 ^ ₂₎ r eight resistors (19- ,, ... 19g) and four resistors 20 (2O ₁ , ... 2O ₄ ). The twelve transistors 18 are arranged in two rows of six elements each (18 ^, ... 18g and I87, ... 18., ^), which are located on one or the other of the two opposite edges 17a, 17c of the cell 17 adjoin. The eight resistors 19 are arranged in four columns between the transistor rows 18, each consisting of two series-connected resistors that are parallel to the opposite edges. The four resistors 20 are arranged parallel to the other two sides 17b, 17d of the cell at the ends of the same. The resistors 19 and 20 can be completely independent of one another and have the same value (for example 500 ohms). They preferably have different values from one another, for example 500 ohms for each of the resistors 19 and 3500 ohms for each of the resistors 20, especially if the circuits are designed in CML technology, as will be explained in more detail below with reference to FIGS. 5A and 5B.

The pattern shown in FIG. 3 is formed from connecting surfaces through which the structural elements or components 18, 19 and 20 in each cell 17, the design of which is that shown in FIG. 2, are accessible. The transistors 18 are each represented by three connection surfaces 18c, 18e and 18b, of which the first forms the collector electrode, the second the emitter electrode and the third the base electrode of the corresponding transistor. The eight resistors 19 are aligned in pairs and have a common connection which is accessible via a surface 19a, as well as a free connection which is accessible via a surface 19b. The four resistors 20 form two groups 20 ^, 2O ₂ and 2Oo, 20 ^, wherein in each group the resistors have an interconnected connection through a

Surface 20a is shown, and have a free connection / which is accessible via a surface 20b.

Fig. 4 shows a practical embodiment of a cell 17, which corresponds to the training shown in FIG. The hatched zones correspond to the connecting areas, which are shown in Fig. 3 and which protrude from the passivation layer which normally forms the surface 12 of the Substrates 11 of the unit 14 are covered, while the lines delimit components that diffuse into the substrate 11 of the cell 17 are. The surfaces 20a are intended in practice with power supply conductors for the operating voltage V- to be connected as referenced later is explained further on FIG.

It can be seen from FIGS. 2 to 4 that a cell according to the invention does not perform any logic function and that all of its elements are available individually. Furthermore, according to a feature of the invention, all transistors 18 are mutually identical and accessible in the same way and are therefore not reserved for a specific function or application. Another feature of the invention is that the elements of one and the same cell have a symmetrical arrangement with respect to at least one axis of an orthogonal system of axes x'x and y'y which are parallel to the axes X ¹ X and Y ¹ Y, which form the two center lines of the rectangle or square that represents the cell 17. In the embodiment shown in FIGS. 2 to 4, the symmetry is present with respect to both axes. This symmetry has the advantage of optimizing the availability of the elements with regard to their wiring, all the more so since they have identical characteristics. In addition, the matrix or unit 14, which is formed from the cells 17, has at least one axis of symmetry which is parallel to the axis X ¹ X or Y ¹ Y. In the example shown in FIG. 1, the

Cells 17 are each equally spaced from one another in the direction of the axis X ¹ X and in the direction Y ¹ Y, but the distances for the two axes are different.

In a conventional manner, a metallic network 21 (FIGS. 5 to 8) is formed on the surface 12 of the substrate 11, in order to connect the components of the cells to one another in a predetermined manner and to connect the integrated circuit or To give arrangement 10 the desired function. These

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predetermined connection method / according to the invention by certain rules which are explained below.

As an example, FIGS. 5A and 5B first show an application of the components 18, 19 and 20 of a cell 17. In CML technology, the example shown in FIG. 5A consists of a circuit arrangement with an AND circuit that has two inputs A, B and an output S, an AND circuit with the two inputs C, D and an output S ¹ and an OR circuit with two inputs ^{corresponding to the two outputs S and S 1} , and a direct output T and an inverted one Output F. Fig. 5B shows the corresponding connections that must be made between the connection surfaces of the relevant components, as well as the connections required for the power supply. In this circuit arrangement eight transistors are used, namely the transistors 18 « _r 18 ^ / 18g, 18 ₄ , 18 ₇ , 18g, 18 ₉ and 18 _1Q , further four resistors 19-], 19 ₂ r ¹⁹ 3 ^'19 4 and a resistor 20 .., and further five operating voltages are used, the voltage V ₀ is derived from an internal power source 16 of the assembly 10 and the voltages Vi, V ^, Vg and V, are supplied through the terminals 13 of the assembly 10 from the outside. In a well-known manner, transistor 18 forms _{a constant current source with resistors 19g and 19 4} , which have a value of 500 ohms, while transistors 18g and 18g form the lower stage and the other transistors form the upper stage.

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Of the components of the same cell 17, the elements 18/19/20 and the neighboring cells are connected by a first connection sub-network 22 to form a block 23 which represents a predetermined logic function, while the blocks thus defined are interconnected by a second Connection sub-network 24 are connected, which forms the metallic network 21 with the first sub-network 22, which defines the desired puncture of the arrangement 10. The blocks advantageously have a predetermined column arrangement. Fig. 6 shows an example of the subdivision of the matrix 14 in 15 blocks 23 (23- - 23 ₁₅₎ which are arranged in four columns, each having a width of four cells 17. Each block 23 is defined along the axis X ¹ X by four cells and along the axis Y ¹ Y by a variable number of rows of cells (three rows for block 23-j, five rows for block 23 ₂ , ... and seven Lines for block 23- ^). The first sub-network 22 is composed of all block connections 22-, ... 22, by which the various connection areas of the neighboring cells inside a block are connected in order to form a predetermined logic function, while the second sub-network 24 is composed of inter-block connections bindings 24-, ... 24, through which the different surfaces are connected, which are intended to connect different blocks. The blocks 23-23., ^ Shown in the drawing take up the entire matrix 14, but the blocks can of course also only take up a part of the matrix, and they can also have different widths in the X'X direction and from one another be spaced in the directions X ¹ X and Y ^{1 Y.} The advantages resulting from the same breadth are explained with reference to the following description. It can thus be seen that the network 21 contains a sub-network · 25 for supplying the circuits with operating voltages.

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Fig. 7 shows a group of block connections 22 forming a block 23 of two rows of four cells, such as block 23 ₇ in Fig. 6. Fig. 7 also shows how these connections are made in practice.

The metallic connecting network 21 is formed in a conventional manner from a plurality of superimposed metallization layers which are separated from one another by insulating layers and are connected to one another via holes which are made in the insulating layers. As shown in FIG. 8, the metallic connection network 21 in this example contains three metallization layers, namely an inner layer 21a, an intermediate layer 21b and an outer layer 21c. Also conventionally, the network 21 is formed by making use of a number of channels which are provided for this purpose at the level of each metal layer 21a, 21b and 21c. The channels are predetermined paths (shown schematically in the drawing by lines) which the conductors of the metal layers must follow in order to connect two points. According to one feature of the invention, a distinction is made between logic channels that are exclusively reserved for conductors in which logic signals circulate, and supply channels that are exclusively reserved for conductors for operating voltage distribution. In the example shown in FIG. 8, the outer layer 21c contains six logic channels 21c .., ... 26Cg per cell, which are located between two supply _{channels 21c, 7} , 21cg, the intermediate layer 21b contains seventeen channels per cell, namely fourteen logic channels 21b-, ... 21b ₇ and 21b ₁₀ , ... 21b _l6 and three supply channels 21bg, 21b _g , which are between the logic channels 21b ₇ and 2Ib _1n , and 21b- ₇ , which is between two cells 17; the inner layer 21a contains six logical inter-cell channels 21a 1, ... 21a _{, which are arranged between two adjacent cells 17, and thirteen cell channels 21a 7 , ... 21a 1q} , which are parallel to the inter-cell channels (Fig. 7). As can be seen from Fig. 7-

is borrowed, 13 cell channels are also present in the layer 21a, which are perpendicular (and not designated) to the aforementioned channels and the inter-cell channels. In order to form the network 21, all channels of the inner layer 21a and a predetermined part of the channels of the intermediate layer 21b, namely in the example shown in FIG. 7, the channels 21b ₁ , 21b ₂ , 21b ₃ , 21bg, 2Tb ₁₁ , 21b ₁₄ the first connection ünternetzwerks 22 reserved exclusively to the formation of the interconnects within the block, while the other logical channels of the intermediate layer 21b, and all the logical channels of the outer layer 21c excluding the formation of the second connection subnetwork 24 for -, 21b _l5 and 21b ,,. the connections between the blocks are reserved and all supply channels are reserved exclusively for the operating voltage distribution conductors.

Another feature of the invention is to physically separate the logical sub-networks 22 and 24 and the supply sub-network 25 from one another, with overlaps only occurring in exceptional cases if this is absolutely necessary for reasons of saturation to form a logical sub-network. This exclusive channel assignment considerably simplifies the design of the general wiring. Fig. 7 shows an embodiment of a block according to the invention, which has as a predetermined function that of a carry generator for a 4-bit adder, corresponding to the block 23 ^ in Fig. 6 (four cells in direction X ¹ X and two cells in direction Y ¹ Y). The logical subnetwork 22 for the connections within the block thus contains all connections which all channels of the inner layer 21a can occupy (these connections being shown with thin lines), as well as all connections which the channels occupy exclusively to the subnetwork 22 of the intermediate layer 21b, these channels being defined above (and the

corresponding connections are shown with thick lines).

According to a further feature of the invention, each block 23 has logical input / output areas 26 (FIGS. 7 and 8) via which the second or logical sub-network 24 can be formed exclusively to interconnect the blocks, these areas 26 lie at predetermined locations. These locations are preferably arranged symmetrically to at least one axis which is parallel to the axes X ¹ X and Y ¹ Y, respectively. As can be seen from FIG. 7, the symmetry of the cells with respect to at least one axis (namely X ¹ X or Y ¹ Y), with symmetry with respect to both axes being present in the embodiment shown, means that the blocks 23 also maintain this symmetry (symmetry with respect to the axes XOXo, Y'oYo) as well as the surfaces 26. Note that the axes XOXo and Y ¹ OYo shown in the drawing are axes lying between the Cells run because there is an even number of cells in aom block 23y in both directions X ¹ X and Y ¹ Y, while with an odd number of cells in these two directions these axes correspond to axes x'x and y ' y in Fig. 3 would correspond. In this way, in the case under consideration, it is possible to assign the same function to a block by means of one and the same wiring pattern, e.g. the wiring pattern 22 of the block 23 * ^ in FIG. 7, which is then applied to a given number of cells (4x2 cells in 7), which are located at any point in the matrix 14, in a given sense (for example that of FIG. 7), in an arrangement inverted with respect to the axis X'oXo, in an arrangement with respect to the Y'oYo axis inverted and in an inverted arrangement with respect to these two axes. So there are four ways of using the same connection pattern to form a block, the choice being made so that the second or

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logical sub-network 24 as simple and as possible is easy to achieve. This shows the advantage that results from the fact that the cells with respect to the two axes are symmetrical and equally spaced from one another along both axes.

Another feature of the invention is for the Formation of the first connection sub-network 22 to determine a group of different common logic functions and to design an optimal corresponding wiring for each function. In practice this is preferably done manually. In this way, a supply of predetermined blocks 23a, ... 23n is available to produce these functions. This supply is for each user to implement an arrangement 10 according to the invention of any type immediately available. For the other blocks that correspond to special logic functions, the course of the corresponding Connections specifically established, advantageously by so-called automatic wiring methods. This shows the advantages that result from having the blocks of the same width.

As already mentioned and as can be seen from FIG. 8, the supply sub-network 25 is designed in the same way as the other sub-networks 22 and 24, ie using exclusively the special channels, namely 21bg, 21b ₉ , 21b ₁₇ , -21c ₇ and 21cg. According to the invention, all channels are completely occupied by the conductors 27 for the operating voltage supply (with the voltages V _Q , V-, V ~, V ₃ , ...). The conductors 27 forming an orthogonal line pattern thus extend over the entire matrix 14. Each intersection point 28 between a conductor 27 for supplying a given voltage in a given layer and another conductor 27 which is intended for the same operating voltage and in an adjacent one.

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th layer, each systematically corresponds to an electrical connection. In order to perform the operations with reference to FIG. 8 To meet the explained condition, the conductors 27, which have the task, for example, of the supply voltage V ^ systematically connected to all surfaces 20a of the matrix 14.

In order to optimize the advantages achieved by the invention, the buffer circuits 15 and the generator circuits are also used 16 (Fig. 1) advantageously implemented in the same way as a block 23. By the invention therefore, the metallic interconnection network has a minimum for an arrangement or integrated circuit 10 of a given type Required space so that the components can be arranged more densely in the substrate 11 and the size of the substrate can be reduced accordingly.

Claims (9)

Dipl.-Ing. Dipl.-Chem. Dipl.-Ing. E. Prince - Dr. G. Hauser - G. Leiser Ernsbergerstrasse 19 8 Munich 60 2nd December 1981 COMPAGNIE INTERNATIONAL POUR L'INFORMATIQÜE CII HONEYWELL BULL 94, avenue Gambetta 75020 Paris / France Our reference: C 3309 Claims Arrangement with or from integrated circuits of high integration density, with a substrate (11), in a Surface (12) of the substrate formed cells (17), each containing a quantity of components, and a metallic connection network ^: (21), which on the named area of the substrate is formed and connects the components and / or the cells to one another, characterized in that the cells (17) are arranged in the form of a matrix (14) and each the same amount of components (18, 19, 20), which in terms of the respective number, characteristics and Relative arrangement in the cell agree that the components of the same cell and possibly neighboring ones Cells are connected by a first connection sub-network (22) of the metallic connection network (21), to form a block (23) representing a predetermined logic function, and that the metallic connecting network a second interconnection sub-network (24) for interconnecting the blocks. 2. Arrangement according to claim 1, characterized in that the relative arrangement of the components (18, 19, 20) of a cell (17) is symmetrical with respect to at least one axis of an axis system (x'x, y'y) which is parallel to is the axes (X ¹ X, Y ¹ Y) defining the matrix (14). 3. Arrangement according to claim 1 or 2, characterized in that the cells (17) along at least one axis (X ¹ X, Y ¹ Y) of the matrix are evenly spaced and each other with respect to at least one axis of an axis system which is parallel to the axes of the matrix are symmetrical. 4. Arrangement according to one of claims 1 to 3, characterized in that the blocks (23) are each formed starting from a set of cells, the one and the same predetermined number (four in Fig. 6) of cells (17) along a Axis (X ¹ X) of the matrix contains. 5. Arrangement according to claim 4, characterized in that the blocks (23) are arranged along the axis (Y ¹ Y) of the matrix in columns (Fig. 6) which each correspond to the predetermined number. 6. Arrangement according to one of claims 1 to 5, characterized in that that the blocks (23) contain input / output ports (26) arranged at predetermined positions are symmetrical to each other with respect to at least one axis of an axis system that is parallel to the Axes of the matrix and through which the blocks are interconnected by means of the second sub-network (24) are. 7. Arrangement according to one of claims 1 to 6, characterized in that the first and the second sub-network (22, 24) are each formed along channels exclusively assigned to them. 8. Arrangement according to one of claims 1 to 7, characterized in that the connection network (21) is a supply sub-network (25) formed along predetermined channels. 9. Arrangement according to claim 8, characterized in that the supply sub-network (25) is a group of conductors (27) which systematically and completely occupy the predetermined channels, the conductors. (27) a layer belonging to a predetermined voltage, systematically at each node (28) with the corresponding conductors (27) of another layer are connected.