DE3018848A1 - Verfahren zur herstellung monolithisch intetgrierter mos- und bipolar-halbleiteranordnungen fuer den vhf- und den uhf-bereich - Google Patents

Verfahren zur herstellung monolithisch intetgrierter mos- und bipolar-halbleiteranordnungen fuer den vhf- und den uhf-bereich

Info

Publication number
DE3018848A1
DE3018848A1 DE19803018848 DE3018848A DE3018848A1 DE 3018848 A1 DE3018848 A1 DE 3018848A1 DE 19803018848 DE19803018848 DE 19803018848 DE 3018848 A DE3018848 A DE 3018848A DE 3018848 A1 DE3018848 A1 DE 3018848A1
Authority
DE
Germany
Prior art keywords
zone
mos
bipolar transistor
epitaxial layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19803018848
Other languages
German (de)
English (en)
Other versions
DE3018848C2 (https=
Inventor
Wolfgang Dipl.-Phys. Dr. 8011 Vaterstetten Müller
Hansjörg Dipl.-Phys. Dr.rer.nat. 8000 München Reichert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to DE19803018848 priority Critical patent/DE3018848A1/de
Priority to JP7285381A priority patent/JPS5717161A/ja
Publication of DE3018848A1 publication Critical patent/DE3018848A1/de
Application granted granted Critical
Publication of DE3018848C2 publication Critical patent/DE3018848C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE19803018848 1980-05-16 1980-05-16 Verfahren zur herstellung monolithisch intetgrierter mos- und bipolar-halbleiteranordnungen fuer den vhf- und den uhf-bereich Granted DE3018848A1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE19803018848 DE3018848A1 (de) 1980-05-16 1980-05-16 Verfahren zur herstellung monolithisch intetgrierter mos- und bipolar-halbleiteranordnungen fuer den vhf- und den uhf-bereich
JP7285381A JPS5717161A (en) 1980-05-16 1981-05-14 Method of producing mos and bipolar semiconductor integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19803018848 DE3018848A1 (de) 1980-05-16 1980-05-16 Verfahren zur herstellung monolithisch intetgrierter mos- und bipolar-halbleiteranordnungen fuer den vhf- und den uhf-bereich

Publications (2)

Publication Number Publication Date
DE3018848A1 true DE3018848A1 (de) 1981-11-26
DE3018848C2 DE3018848C2 (https=) 1989-02-16

Family

ID=6102649

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19803018848 Granted DE3018848A1 (de) 1980-05-16 1980-05-16 Verfahren zur herstellung monolithisch intetgrierter mos- und bipolar-halbleiteranordnungen fuer den vhf- und den uhf-bereich

Country Status (2)

Country Link
JP (1) JPS5717161A (https=)
DE (1) DE3018848A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719431A (en) * 1994-04-06 1998-02-17 Siemens Aktiengesellschaft Integrated driver circuit configuration for an inductive load element

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994887A (en) * 1987-11-13 1991-02-19 Texas Instruments Incorporated High voltage merged bipolar/CMOS technology
JPH01226172A (ja) * 1988-03-07 1989-09-08 Nippon Telegr & Teleph Corp <Ntt> 半導体装置とその製造方法
JPH07112024B2 (ja) * 1988-11-10 1995-11-29 株式会社東芝 半導体装置

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Bd. 16, 1974, No. 8, S. 2701-2703 *
IBM Technical Disclosure Bulletin, Bd. 16, 1974, No. 8, S. 2719/2720
IBM Technical Disclosure Bulletin, Bd. 17, 1974, No. 1, S. 86/87
IBM Technical Disclosure Bulletin, Bd. 17, 1974, No. 1, S. 86/87, IBM Technical Disclosure Bulletin, Bd. 16, 1974, No. 8, S. 2719/2720 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719431A (en) * 1994-04-06 1998-02-17 Siemens Aktiengesellschaft Integrated driver circuit configuration for an inductive load element

Also Published As

Publication number Publication date
DE3018848C2 (https=) 1989-02-16
JPS5717161A (en) 1982-01-28
JPH0235469B2 (https=) 1990-08-10

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition