DE2950979C2 - Numerical control system - Google Patents

Description

The invention relates to a numerical Control system according to the preamble of the patent demanding 1. Such numerical control System is known from US 4,038,533. Indeed is there only a single processor provided both the function of a numerical control as well as that of a programmable logic Control can make.

Numerical control systems are tooled machines connected to a function of a stored part program the movement of a cutting control tool. The stored program diri yaws the machine tool through a series of Steps. For example, in a milling machine bewe the cutting tool along three separate axes gen to rectilinear or circular in a workpiece Perform cuts. The part program provides one Series of commands or instructions in the form of Digital numbers and codes are stored and specify where the cuts should be made and in which Sequence or order the cuts made who that should. Although with regard to the development of Technique the part programs in magnetic or perforated tapes ge stores and when executed in the form of data blocks were read into the numerical control system Recently, there are numerical control systems that entire partial programs in their random access memories store.

In addition to controlling the movements of a cutting The tools are taken over by the numerical control systems also the control of auxiliary functions on the machine tools,  for example, tool selection and tool change, the speed of the drive spindle, the flow of a cooling by means of pallet selection and pallet change. These Auxiliary functions vary considerably from machine to machine and it was typical that these auxiliary functions were provided by ge disconnected, hardwired logic circuits were executed those who respond to both sensed states or conditions the machine tool as well as commands or instructions match that of selected codes within the part programs are specified. As in the above mentioned US 4,038,533 and US 3,810,104 is, you have recently programmable controllers via interface connections to the processor numeric Control systems connected to the auxiliary functions too control. It can be with these programmable controllers be a separately programmed processor or to be an integral part or integral unit of the Pro of the numerical control system.

The addition of a programmable controller to a numerical control system leads to a series of extremely practical advantages. First, it is not him necessary, the hardware of the programmable controller to change if the numerical control system in under different types of machine tools is involved. Instead, the programmable controller is so program that it is capable of using a special machine to form an interface connection. Second, one is programmable controller, although programmable Interfaces have been based on mini-computers for many years control systems are available, by the user much easier to program what is used on the Instruction set as well as editing or editing possible This is due to a programmable Control unit are available.  

Despite the many advantages of an interface Connection of a programmable controller with a numerical control system, increases such an arrangement the system costs, and in some cases, these can increase costs are not justified. For example In some applications, for example, the machine tool to which the controller can be connected via an interface should, very easily trained, and the task of a ge disconnected logic circuit or relay circuit for operation is to develop and manufacture the individual I / O devices trivial. Thus, it is desirable that a numerical control the interface for a programmable control device as an option instead of an inseparable one Part of the basic numerical control system.

Most in use numerical Control systems are made up of individual digital electronics components or building blocks, such as logical ones Gates, latching switches, flip-flops, and registers. Recently, however, one has mini calculator or Indu computerized computers as described in US Pat. No. 4,038,533 are programmed to have numerical control functions can execute. With the development relatively faster and cost-effective microprocessors and on microprocessors based numerical control systems you also have the economic and technical conditions for the Applicability created.

Numerical control systems contain a Prozes sor, the blocks of program part data in motion commands signals that are connected to the sequential control mechanisms or Servo mechanisms are output at a machine. Dar In addition, codes in the subprogram become logical Signals are converted to the individual I / O devices on the machine control to perform helper functions. Operation of the  Numerical control system is controlled by numerous switches and display devices controlled on a front panel te are attached so that they are for the operator of the Machine are easily accessible. Keyboards and cathodes ray tube viewing devices are also in general mine on the front panel to manually enter Da as well as the preparation or edition of the subprograms to enable them. Between this so-called frontplat tengeräten and the numerical control processor, or the Numerical control system processors are numerous Connections required. The production of such verbin It is very expensive. For practical reasons, it is therefore necessary that the front panel and the numerical control processor as close together as possible are. The result of these considerations is that most numerical control systems in a large cabinet below on the front of which are the front panel Controls are located. The cabinet is always located in a location that is easily accessible to the operator is. The consequence of this is that between the free the cabinet of the numerical control system and the controlling machine requires a considerable amount of wiring is.

While the state of the art after the US 4,038,533 now makes use of a single processor, which gives some flexibility and flexibility Adaptation to be set to various machine tools, is from US 4,064,395 a machine control system with two separate processors known, one data processor with an arithmetic unit and a logical processor with a logic circuit. The logical processor takes the function of a programmable logic controller true and controls the auxiliary over an I / O interface functions of the machine to be controlled. Task of the data Processors are, in conjunction with a digital pre  thrust and motor control the feed rate to control a movable part of the machine. However, for both processors is only one Control program provided in the memory programmable controller parent processor is stored. In addition to this control program, there are no independent workpiece or part program. Hardware are both processors with a and the same address bus and with the same data in addition to being jointly with the I / O interfaces of each Devices are.

The object of the invention is the generic numeri To improve the control system so that the main processor made control of the servo mechanisms the machine tool in cooperation with the operation individual devices of the machine tool is simplified.

This task is characterized by the characterizing Features solved in claim 1. The claimed Solution allows the two processors ko can work ordained.

The programmable interface processor (PI processor) is a separate from the main processor be driven system, although data with the main processor exchanges, but otherwise is not dependent. Data showing the state of the numerical control system and by the system performing auxiliary functions are periodically from the main processor to the pro transmitted programmable interface processor. Likewise, data will be the state of the controlled  Show machine tool periodically from the programmable interface processor to main processor. The main processor can work with continue to perform other functions while the programmable interface processor a ge stores control program, preferably Commands according to the type of a programmable logic controller baren control contains. The programmable cut The processor can also periodically change the data and Occupy the main processor address bus to get data about it from the individual devices of the machine tool and output data to the machine tool. The programmable interface processor can with be connected to a program loader, as in the US 3,813,649 and US 4,070,702 is to load and edit or edit the tax program implemented by him.

The created according to the invention numerical Control system is in terms of system size, the local arrangement and design as well as the System capabilities very flexible. The separately operated Processors allow for minimal changes in hardware and in software features or Features can be added or removed. Switches, display devices, visual vision devices and other parked on the operator I / O devices can be easily added or removed be taken. The main processor with its complex Programs do not need to be disturbed. In similar Way require changes to the machine tool in the general only one change in the control program that from the programmable interface processor leads. Such changes in the control program can by the user using a program console or program miergerätes be made easily. It will be  Edition or treatment method used, the known from programmable controllers forth are.

A trained according to the invention numerical Control system thus contains a main processor, of functions such as interpolation and output of Motion command signals to the servomechanisms of a Machine tool executes. A separate programmer barer interface processor is compatible with the main pro zessor bus arrangement and works like one programmable logic controller to the individual Control devices of the machine tool.

In a development of the invention a direct access circuit is provided which the Data and address bus of the main processor with the ent programmable interfaces talking buses processor connects.

According to another embodiment The invention is another independent processor provided in the form of a front panel processor, although also exchanges data with the main processor, but in the other is not dependent. The front panel processor generally monitors the front panel switches as well the input data blocks from a tape reader, a Teletypewriter (TTY), a magnetic cassette device or other input devices and controls the front panels signal lamps as well as an alpha-numeric display device or a CRT display device on. The front panel processor exchanges with the main processor data preferably via a single communi cation connection, which allows the front plate away from the main processor can. As a result, therefore, the front panel and the associated front panel processor either in the same Cabinet like the main processor or separated in one  smaller, freely available with regard to the location Station be housed, whose place of the machines operator is acceptable.

Other developments are in further Subclaims characterized.

A preferred embodiment of the invention will be described below with reference to drawings. Show it:  

Fig. 1 is a pictorial representation of the numerical control system according to the invention,

Fig. 2 is a schematic diagram of the main processor portion of the control system of FIG. 1,

Fig. 3 is a schematic diagram of the programmable interface processor portion of the control system of FIG. 1,

Fig. 4 is a schematic diagram of the direct memory access circuit (DMA circuit), which forms a part of the processor portion of FIG. 3,

Fig. 5 is a schematic diagram of the front panel processor portion of the control system of Fig. 1,

Fig. 6 is a schematic representation of the main processor operating system,

FIG. 7 is a schematic representation of the contents of a scheduled queue forming part of the operating system of FIG. 6; FIG.

Fig. 8 is a schematic representation of the contents of a process control block of the system part of the operation of FIG. 6,

Fig. 9 is a diagram of a typical opération sequence of the operating system of FIG. 15,

FIG. 10A and 10B a flow chart of contem controlled interrupt process, the drive system is a part of the Be forms of FIG. 15,

FIG. 11 is a flow chart of the front panel monitor forming part of the operating system of FIG. 6; FIG.

FIG. 12A and 12B a flow chart of the operation of systems of the programmable interface processor,

Fig. 13 is a timing diagram illustrating the Paral lelbetriebes the programmable interface processor and the main processor,

Fig. 14 is a schematic representation of the contents of the associated programmable interface Abbil extension panel that forms a part of the system of FIG. 2,

Fig. 15 is a schematic representation of the soft ware system of the front plate processor,

Fig. 16 is an illustration of the state event chalkboard that USAGE in the software system of FIG. 15 is det,

Fig. 17 is a schematic representation of the format of a message that is transmitted via the serial data link via averages,

Fig. 18 is a schematic representation of the data structure associated with the serial data connection.

As shown in FIG. 1, a preferred embodiment of the numerical control system according to the invention in a main housing 1 and a non-stationary control station 2 is housed. A program station (station) 3 is used to load and edit the control program to be executed by the pro grammable interface processor. Station 3 , however, does not form part of the operating system. The construc tion of the main body 1 is tert erläu in DE 28 50 093 A1. The main body 1 includes a back-side base plate 4 and a series of printed circuit boards, which are connected to the base plate 4 and protrude from it to the front.

On the record much of the circuitry described below is accommodated, and include a main processor circuit board 5, a circuit board (interface circuit board) 6 for the programmable interface, a servo interface circuit plate 7 and an input / output interface circuit plate. 8 The main processor circuit board 5 is connected to the non-localized control station 2 via a cable 9 , and the circuit board 6 for the programmable interface or the programmable interface circuit board 6 is connected via a cable 10 to the program pultstation 3 . Similarly, the servomechanism interface circuit board 7 and the I / O interface circuit board 8 are connected via cables 11 and 12 respectively to the machine tool 13 to be controlled. The main housing 1 is typically located in a cabinet attached to the machine tool 13 . The cables 11 , 12 contain numerous conductors which are connected to the equipment in the same cabinet. In contrast, cables 9 , 10 are serial data links that can be up to about 15 meters long.

The untethered control station 2 is mounted in a location acceptable to the machine tool operator, and the control station 2 includes a keyboard or keypad 14 and switch (FP switch set) 15 for manually inputting data. The control station 2 also includes an optional alphanumeric viewer 16 and an optional CRT or CRT viewer 17 . Further, the control station 2 includes a front panel processor circuit board (not shown in the drawings) which is connected to the cable 9 and has circuits to be described hereinafter which process data from the keyboard 14 and the switches 15 and output data to the viewers 16 and 17 submit.

The program console station 3 includes a keyboard or keypad 18 and a viewer 19 . The program station 3 is connected to the programmable interface circuit board 6 via the cable 10 , and serves to load a control program of the type, as it is processed by a programmable controller, and edit or edit. After the loading and edition process is finished, you can separate the program pultsta tion 3 and use for other machines.

Main processor hardware

The main processor of the numerical control system is located on the circuit board 5 and is accordingly formed as shown in FIG. 2 around a 16-bit microprocessor 25 , which is connected to a 15-conductor address bus 26 and a 16-conductor data bus 27 is connected. As a microprocessor 25 , a device type TMS 9900, manufactured by Texas Instruments Incorporated, is used, and this microprocessor 25 is driven by a 3.3-MHz four-phase clock 28 . The address bus 26 and the data bus 27 are also formed in the base plate 4 and connect a series of system elements including a random access memory 29 and a read-only memory 30 . Although the size of the memories 29 , 30 may vary widely depending on the particular needs of the system, the basic system includes a 17-bit x 4K random access memory as memory 29 and a 16-bit x 12K ROM as memory 30 . An RD control line 31 leads from the microprocessor 25 to both the random access memory 29 and the fixed value memory 30 , and a WE control line 32 establishes a Ver connection between the random access memory 29 and the microprocessor 25 ago. A 16-bit word is read from either the random access memory 29 or the read-only memory 30 when a selected memory line is addressed via the address bus 26 and a logic low control signal is applied to the RD control line 31 . The 16-bit word thus read from the random access memory 29 or the read-only memory 30 passes through the data bus 27 and a 16-bit buffer 33 to a designated register within the microprocessor 25 . A 16-bit data word is written into the random access memory 29 by addressing a selected line in the random access memory 29 via the address bus 26 and applying a low control signal to the WE control line 32 in the logical sense. Further storage options can be added to the system. By extending the address bus to 19 conductors or lines, you can use up to 512 K memory.

The data bus 27 and the address bus 26 are also connected via the base plate 4 to circuits of the servomechanism interface circuit board 7 . The servomechanism interface circuit board 7 includes 16-bit motion command registers (not shown in the drawings) and 16-bit return word registers (not shown in the drawings). These individual registers can be addressed separately or individually via the address bus 26 , and a 16-bit motion command word can thus be written to any of the drive command registers when a low voltage is applied to the WE control line 32 in the logical sense. Similarly, a 16-bit follower word can be read from an addressed feedback register when a low voltage is applied to a DBIN control line 34 in the logical sense.

As is well known, by periodically calculating a new position command number output to the servomechanism of the machine tool 13 , one can accurately control the movement of a cutting tool. In such a case, a position command register and a feedback register are assigned to each movement axis. Although the control loop may be closed within the main processor, in the preferred embodiment, the control loop is closed for each axis of machine motion in the servomechanism interface circuit board 7 using a technique and method known from US 3,752,969.

Furthermore, it can be seen from Fig. 2, that the data bus 27 and the address bus 26 are also connected via the base plate 4 with circuits of the I / O interface circuit board 8 . The I / O interface circuit board 8 includes sets of 16 input circuits and sets of 16 output circuits. The input circuits are each individually ver with a sensor in the machine tool 13 connected, for example, a limit switch, and each output circuit is connected to an actuator in the machine tool 13 , for example, a motor starter or solenoid. As input circuits can be used Anord calculations, as described in US 3,643,115 and US 3,992,636, and as Ausgabeschaltun gene arrangements can be used, as described in US 3,745,546. By generating the appropriate address on the address bus 26 and applying a logic low voltage to the WE control line 32 , data can be written to a set of output circuits. Similarly, by generating the appropriate address on the address bus 26 and applying a logic low voltage to the DBIN control line 34, data from a set of input circuits can be read out. Although the data in the form of 16-bit words in the I / O-Schnittstelleschal circuit board 8 enrolled and read who, it should be noted that each bit is assigned to a single sensor or actuator of the machine tool 13 . These are individual devices or devices which can be easily controlled using the technology of programmable controllers.

Referring to Figs. 1 and 2 it is out that the communication of data to and from the control station 2 from a front panel USART 37 leads out is ( USART : Universal synchronous-asynchronous receiver-transmitter). The USART 37 includes 8 data ports that connect a set of 8 bidirectional buffers 38 to the 8 least significant digital lines DB8 to DB15 in the main processor data bus 27 . The cable 9 is connected to a data receiving terminal and a data transmitting terminal of the USART 37 , and when an 8-bit byte of data is received via the cable 9 from the control station 2 , a control line 39 becomes a logical low interrupt signal generated. This interruption or interruption signal is served by the microprocessor 25 which generates the address of the front panel USART 37 on the address bus 26 and applies a logic low voltage to the RD control line 31 to read out the received byte of data on the data bus 27 , On the other hand, if an 8-bit byte of data is sent to the program station 3 , an interrupt signal is generated on an interrupt control line 40 by the USART 37 to indicate that the previous byte of data has been sent out. The microprocessor 50 responds with the execution of an interrupt service routine that is stored in the read only memory 30, wherein the front panel USART is addressed 37 via the address bus 26 and a cal in lo sense is generated low voltage on the WE control line 32nd An 8-bit byte of data is then given to the data bus 27 via the buffers 33 and written to the USART 37 . The USART 37 then sends the 8-bit byte of data serially through the cable 9 to the control station 2 . The USART 37 is driven by a 2-MHz clock encoder, which is connected to it via a control line 41 .

The USART 37 is a universal synchronous / asynchronous transceiver which establishes the interface connection of the main processor with the serial data connection provided by the cable 9 . The data is received serially in the form of 8-bit bytes from the cable 9 , checked for transmission errors and read in the form of 8 parallel bits on the data bus 27 . A similar universal synchronous / asynchronous receiver / transmitter is connected at the control station 2 to the other end of the cable 9 . These synchronous / asynchronous receiver / transmitter serve to transmit the data through the cable 9 in both directions Rich. The cable 9 contains only 4 conductors. By convention, according to an RS-232 protocol, it may have a length of up to 15m.

The breaks or interrupt signals generated by the front panel USART 37 and other elements in the system receive an interrupt control circuit 45 . As seen from FIG. 2, the interruption control circuit 45 is connected to receive the third phase clock signal from the 4-phase clock 28 via a line 46 . The interrupt control circuit 45 has a set of 4 interrupt code outputs and an interrupt request output. These outputs are connected to the microprocessor 25 via a bus 47 . The interrupt control circuit 45 is a commercially available integrated circuit, for example of the model type TMS 9901. The interrupt control lines 39 and 40 from the front panel USART 37 lead to the interrupt control circuit 45 , and the interrupt control circuit 45 is responsive to a signal on one of these two lines 39 , 40 , to generate a 4-bit code together with an interrupt request for the microprocessor 25 .

The interrupt control circuit 45 also determines the priority of the interruptions, and a list of the interruptions of the USART 37 along with other main processor interruptions are arranged in order of priority in a following table A. Some of these interrupts, including interrupts generated by the USART 37 , may be disabled or masked so that they are not supplied to the microprocessor 25 .

interruption description 0 Restart of the system LD Power-on reset 1 Reserve power failure 2 Single step by program 3 Data received by USART 37 4 Data sent by USART 37 5 Timing error with slow memory ready line 6 Parity Error Reading the Data Bus 27 7 Guardian timer expired 8th 1,6-ms timer 9 100-ms timer

A real-time clock circuit 50 is connected to the address bus 26 and generates a 1.6-ms interrupt on a line 51 leading to the interrupt control circuit 45, and a 100-ms interrupt on a line 52 leading to the interrupt control circuit 45 .

Programmable interface hardware

Referring to Figs. 2 and 3, it will be understood that a programmable interface (PI) 75 is included in the programmable interface circuit board 6 . The programmable interface circuit 75 is connected to the main processor data bus 27 and the main processor address bus 26 . Further, the programmable interface circuit 75 is connected to the RD control line 51 and the WE control line 32 and receives the 100 ms clock from the real time clock circuit 50 via the line 65 . The programmable interface circuit 75 is a separate processor and this processor periodically includes control over the main processor data bus 27 and the main processor address bus 26 by generating a logical low signal on a DMA REQ control line 76 . This control signal passes via a reversing member 77 to a holding terminal 78 in the microprocessor 25th When the request or the call is successful, is sent via an inverter 79 and a DMA GNT control line 80 from the microprocessor 25, a signal back to the programmable interface circuit 75 ge.

In the following, reference is made to FIG. 3. The programmable interface circuit 75 is constructed around an 8-bit data bus 82 and a 16-bit address bus 83 . The address bus 83 is driven by a set of sixteen buffers 84 from an 8-bit microprocessor 85 . The data bus 82 is connected to the microprocessor 85 via a set of eight bidirectional buffers 86 . The microprocessor may be Model Z-80, manufactured by Zilog, Inc., and the microprocessor 85 is driven by a 4 MHz clock circuit 87 .

The programmable interface circuit 75 also includes an 8-bit x 4K line read only memory 88 and an 8-bit x 2K line read only memory 89 which is electrically changeable. The memories 88 , 89 are connected to the lines (D 0 to D 7) of the data bus 82 and to the lines (A 0 to A 15) of the address bus 83 . Selected data may be read from the memories 88 , 89 when the microprocessor 85 is executing memory read commands. When such a command is executed, a logic signal is generated at one of five enable lines 91 and an rd control line 92 . A decode and control circuit 90 of the programmable interface circuit 75 actuates the enable line 91 and the memory read command releases the contents on a selected line in the memory 88 or 89 to be read on the data bus 82 .

By executing memory write commands, data can also be written to the electrically alterable ROM 89 . These instructions cause the decode and control circuit 90 to enable the memory 89 via a control line 91 and to generate a logic signal on a wr control line 93 . When such an instruction is executed, data is written from the data bus 82 to the memory 89 .

The programmable interface circuit 75 also includes a 9-bit by 2K line random access memory 94 connected to the lines (A0 to A15) of the address bus 83 . In addition, the random access memory 94 is connected to the wr control line 93 and to two enable lines 95 and 96 which are driven by the decode and control circuit 90 . From data bus 82 , 97 data are written to an addressed line or line of random access memory 94 via a set of eight gates. The gates 97 each have a release terminal which is commonly connected via a gate enable line 98 to the decode and control circuit. When a memory write command is executed by microprocessor 85 , an 8-bit word is passed through gates 97 and stored in the addressed row of random access memory 94 .

The data is transferred from the random access memory 94 to the data bus 82 via an 8-bit by 512-line map memory 100 in the form of a programmable read-only memory PROM. When data is to be read from the random access memory 94 , the map PROM 100 is enabled by a MAP-EN control line 101 which is driven by the decode and control circuit 90 . The random access memory 94 stores control program instructions that contain operation codes that are not recognized by the microprocessor 85 . These opcodes are applied to address pins on the imaging PROM 100 , and each unique code addresses a specific lead or row in the imaging PROM 100 . A number indicating the start address of a control command interpreting routine is stored in the map PROM line corresponding to the unique operation code. Whenever a control command opcode is read from random access memory 94 , it is mapped to the number indicating the start address of the corresponding interpreter routine. These numbers are generated at the picture PROM data terminals which are connected to the eight lines or conductors in the data bus 82 . The programmable interface system jumps to the displayed or specified interpreter routine, and the microprocessor 85 executes the machine instructions therein to perform the functions indicated by the control instruction operation code. All other data stored in random access memory 94 is fed directly to data bus 82 without change.

The control program is loaded into the random access memory 94 and prepared or edited via the program console station 3 . As can be seen from FIG. 3, the cable 10 from the program console station 3 is connected to the serial input and serial output terminals of a program loader USART 103 , whose parallel data connections to the eight lines D0 to D7 of the data bus 82 of the programmable interface circuit 75 are connected. A C / terminal of the program loader USART 103 is connected to the line A 0 of the address bus 83 , and its CS terminal is connected to the decode and control circuit 90 via a USART-EN line (control line) 104 . The program loader USART 103 is also connected to the wr control line 92 and the rd control line 93 , and when an 8-bit byte of data is received from the USART 103 via the cable 10 , it generates via an INT line 105 an interrupt request directed to the microprocessor 85 . When the microprocessor 85 acknowledges the interrupt, the system jumps to a program loader routine stored in read-only memory 88 . This program loader routine includes instructions that enable the program loader USART 103 through the control line 104 and generate a logic low signal on the rd control line 92 . Due to these circumstances, the received 8-bit byte of data on the data bus 82 is read.

Conversely, instructions executed by microprocessor 85 may also enable program loader USART 103 through control line 104 and generate a logic low signal on wr control line 93 to load an 8-bit byte of data into program loader USART 103 , This data is then transmitted serially through the cable 10 to the program console station 3 . In this way, characters can be inputted from the keyboard 18 , and characters can be output to the viewer 19 of the program console station 3. *** "

The programmable interface circuit 75 interfaces with the main processor via a DMA circuit 110 (DMA = Direct Memory Access). In the following, reference is made in particular to FIGS. 3 and 4. Data on the 16-bit main processor data bus 27 is sent to the 8-bit data bus 82 of the programmable interface circuit 75 via an 8-bit data latch 111 and an 8-bit data buffer 112 . The lower 8-bit byte of such a 16-bit data word is passed directly through the 8-bit data buffer 112 when a DIN control line 113 is driven by a DMA decoder and controller 114 with a logic low signal becomes.

The upper 8-bit byte is temporarily stored in the 8-bit data latch 111 , and during the next machine cycle, a CLIN control line 115 is driven by the DMA decode and control circuit 115 with a logic low signal to transmit the 8-bit byte stored in the 8-bit data latch 111 to the data bus 82 of the programmable interface circuit 75 . The 16-bit word from the main processor is thus translated into two 8-bit words in the programmable interface processor.

In the reverse direction, ie, from the programmable interface circuit 75 to the main processor data bus 27 , the data is transferred via an 8-bit data latch 116 and an 8-bit data buffer 117 . A first 8-bit byte on the data bus 82 of the programmable interface 2 is stored in the 8-bit data latch 116 when a logic low voltage is applied to a CLOUT control line 118 . Then, when the programmable interface circuit 75 occurs, a second 8-bit byte of data on the data bus 82, is generated in the logical sense a low voltage at a DOUT control line 119th Thereby, the data latch 116 and the data buffer 117 are enabled, so that both 8-bit bytes of data are simultaneously delivered to the main processor data bus 27 in the form of a 16-bit data word. In this way, bidirectional data flow is effected between the 16-bit main processor and the 8-bit processor of the programmable interface circuit.

In the following reference is made to FIG. 2. The programmable interface circuit 75 routes and directs the transfer of data to and from the main processor. It transfers data to and from two general locations, namely a map 105 of the programmable interface circuit 75 stored in the random access memory 29 and the input / output interface circuits on the circuit board 8 . The programmable interface circuit 75 addresses these locations using the main processor address bus 26 , which is exposed to it when a DMA request is granted.

In the following, reference is again made to the DMA circuit shown in FIG. 4. The main processor address bus 26 is driven by the programmable interface circuit 75 through a set of sub-byte address buffers 122 and either via a set of upper-byte address buffers 123 or an 8-byte data latch 124 . Seven inputs of the upper byte address buffers 123 are connected to a source having a high logic voltage and the eighth input is signal ground. The eight inputs of the sub-byte address buffers 122 are connected to conductors A 0 to A 7 of the address bus 83 of the programmable interface circuit 75 . The inputs of the 8-bit data latch 124 are connected to conductors in the main processor data bus 27 , and during power-up, the main processor writes the eight most significant digits of the address of the mapping panel 105 of the programmable interface circuit 75 into the 8-bit data latch 124 , This is achieved by generating the address EC1E (hexadecimal) on the address bus 26 during a write command. This address is decoded by the decode and control circuit 114 , which enables the 8-bit data latch 124 via an UPP ADD control line 126 . Accordingly, if the position of the MAP 105 of the programmable interface circuit should be changed for any reason, the programmable interface circuit 75 will automatically receive an assessment of this fact via the 8-bit data latch 124 each time the system is powered up.

A FLREQAK control line 125 is still connected to the data latch 124 and is driven by the decode and control circuit 114 from a logic low signal to generate on the main processor address bus 26 the start address of the MAP 105 of the programmable interface circuit (interface) 75 , A particular line or line in the mapping table 105 is selected by the address on lines A 0 through A 7 in the address bus 83 of the programmable interface 75 which is applied to the main processor address bus 26 via the sub-byte address buffers 122 . The address buffers 122 are enabled by a loader control circuit 127 .

Thus, by sequentially enabling the elements of the DMA circuit 110 , the microprocessor 85 can read and write data to and from the main processor memory (Random Access Memory) 29 . In this way, the contents of the mapping panel 105 of the programmable interface 75 in the main processor memory 29 and a similar PI mapping panel 106 of the programmable interface 75 in the memory 94 may be periodically changed or transferred in memory 94 to account for changes made since the previous direct memory access (DMA). occurred in this memory 94 .

Referring to FIG. 4, it is further stated that the other function of the DMA circuit 110 is to exchange data between the I / O interface circuits of the circuit board 8 and an input / output mapping board 107 stored in the programmable memory 94 Interface 75 is stored. This data transfer is controlled by the DMA circuit 110 under the direction of the microprocessor 85 , and if such a transfer is to take place, a signal is generated on an IOAK control line 128 comprising the upper byte address buffers 123 in the DMA circuit 110 releases. As a result, the I / O interface circuits of the circuit board 8 are thus addressed by the main processor address bus 26 . The particular set of 16 selected input or output circuits is determined by the eight least significant bits applied to the main processor address bus 26 via the sub-byte address buffers 122 . Under the direction or guidance of an input / output scan routine, the microprocessor 85 sequentially addresses each set of input and output circuits via the sub-byte address buffers 122 . It operates the DMA circuit 110 to transfer data from the I / O interface circuits of the circuit board 8 to the I / O map 107 stored in the random access memory 94 , and is operative to transfer data from the I / O. A mapping panel 107 to the I / O interface circuits of the circuit board 8 to transfer. In this way, the I / O mapping board 107 is periodically connected to the individual sensing devices and actuators of the controlled machine to update and update both the I / O mapping board 107 and control the actuators.

Referring to FIG. 4, the control lines operating the various buffers and data latches in the DMA circuit 110 are driven by the DMA decoder and controller 114 . This circuit is connected to a set of lines leading to the main processor and to a set of lines leading to the programmable interface 75 . An NMI control line 137 is connected to a corresponding terminal on the microprocessor 85 of the programmable interface 75 . When a logic low voltage is generated on the NMI control line 137 , the microprocessor 85 of the programmable interface 75 is presented with a non-maskable interrupt NMI. In this way, the main processor initiates a sequence of functions performed by the programmable interface circuit 75 . As will be explained, this happens every 25.6 ms, and it serves to synchronize the operation of the two processors.

After the NMI interrupt has been initiated by the main processor, the main processor continues to perform its many other functions, and the microprocessor 85 of the programmable interface 75 begins executing a series of functions that facilitate the transfer of the contents of the (PI). The display panel 105 (PI = programmable interface) from the main processor to the PI mapping board 106 of the programmable interface 75 . It performs this transfer by making a series of direct memory access requests from the main processor.

Referring to Fig. 3, it is explained that the decoding and control circuit 90 of the programmable interface 75 generates enable signals for the various elements of the programmable interface circuit 75 including the DMA circuit 110 .

The various elements of the programmable interface circuit 75 are enabled and operated in response to specific machine instructions executed by the microprocessor 85 . The operation codes in these instructions operate the wr control line 93 , the rd control line 92, and the mreq control line 140 , and the operand or address codes in these commands select a system element. The memories 88, 89 and 94 are, of course, released from a range of addresses, but each line in these memories has its own particular address.

Hardware of the non-mobile control stations

As can be seen in particular from FIGS. 1, 2 and 5, the locally-free control station 2 is connected to the main processor circuit board 5 through the cable 9 . The cable 9 is connected to a main processor USART 220 of the control station 2 . The USART 220 is located on a circuit board (not shown in the drawings) along with other elements of the front panel processor. These elements include a 16-bit microprocessor 221 , which may be a TMS 9900 model from Texas Instruments, Inc. The microprocessor 221 is connected to drive a 15-conductor address bus 222 and is connected to a 16-conductor bidirectional front panel processor data bus 223 .

Machine instructions for the 16-bit microprocessor 221 are stored in a 16-bit x 16K line ROM 224 which is programmable. Further, the address bus 222 and the data bus 223 are connected to a 16-bit × 4K line access memory 226 and a 4-bit × 2K line read-only memory 225 which is electrically changeable and stores visual display messages. From these three memories 224 to 226 , data may be read out when the memories 224 to 226 are enabled by respective control lines 227 to 229 and when the appropriate logic state is generated at respective AD and WE control lines 230 and 231 . Similarly, data may be written to the random access memory 226 when the memory 226 is enabled by the CS control line 229 , and when a logical high voltage is applied to the we control line 231 . Data can also be written into the electrically variable read-only memory 225 if it is enabled by the EAROM-EN control line 228 and if a high voltage is applied to the we control line 231 in the logical sense. The particular line into which data is written or read from the data into any of the memories 224 through 226 is selected by a corresponding address on the address bus 222 .

In the following, reference is made to FIGS. 1 and 5. The keyboard or keypad 14 of the control station 2 is connected to the front panel processor data bus 223 via a keypad interface circuit 235 .

The CRT viewer 17 of the control station 2 is connected to the front panel processor data bus 223 of the front panel processor via a cathode ray tube interface circuit 250 . The switch 15 and the alphanumeric viewer 16 of the control station 2 are connected via a switching and display interface circuit 265 to the address bus 222 and the data bus 223 . The remaining I / O devices associated with the control station 2 are connected to the microprocessor 221 via the interrupt and I / O control circuit 243 . This outputs data to a control light driver circuit 335 .

The control lines that enable the various front panel processor elements described above are largely driven by a front panel decoder and control circuit 350 ( Figure 5).

Main processor operation

First, for explanation, Fig. 2 is used. The numerical control system according to the invention performs numerous functions. Part program data is input from the tape reader 297 to the front panel processor and transmitted via the cable 9 to the main processor. The blocks of the part program data are stored in the main processor access memory (random access memory, main processor memory) 29 . Operator commands from the operator are also received by the front panel processor from the keypad 14 and switches 15 . These commands are also transmitted to the main processor whose microprocessor 25 processes these commands to operate the numerical control system in the commanded manner.

When the numerical control system executes a partial program, the blocks of partial program data are read from the random access memory 29 (128 bytes at a time). A block of subprogram data may include codes that must be decoded, include dimensions that indicate the distances that the cutting tool is to be moved, and numbers that indicate the rate at which the cutting tool is to be moved. The codes can also give instructions that the auxiliary functions such as tool change, pallet change, coolant supply, etc. are performed. When these codes are decoded, a designated flag is set in the display panel 105 of the programmable interface 75 . This mapping table is stored in the random access memory 29 . The contents of the PI map 105 (PI) are periodically transferred to the programmable interface circuit 75 to indicate that the particular helper function is to be performed.

The dimensions and numbers in a subprogram are used by the microprocessor 25 to calculate a distance or distance the cutting tool is to move along each axis of the machine tool movement in a single 25.6 ms iteration. These links are stored in active buffers in the random access memory 29 and are used by the microprocessor 25 under the direction or guidance of an interpolation routine every 25.6 ms to calculate the motion command signals output to the servomechanism interface circuit 7 .

The control of these and other functions lies with the microprocessor 25 of the main processor, which operates under the guidance of a scheduler routine stored in read-only memory 30 . In addition to FIG. 2, FIG. 6 is used in particular for the following explanation. The scheduler routine (or scheduler) is shown schematically at 360 and is entered at least once every 1.6 milliseconds when the microprocessor 25 responds to the interrupt generated by the real-time clock 50 . The various functions that the main processor has to perform are collected in seven general processes or processes, and it is the function of the scheduler 360 to assign each of these processes in turn to 1.6 ms time slices. These seven processes are defined here as: timed interrupt process 361 , block setup process 362 , block fill process 363 , front panel monitor 364 , keypad command process 365 , program load process 366, and display update process 367 . The scheduler 360 has sixteen 1.6 ms time slices (16 x 1.6 = 26.6) that it can associate with these processes during each iteration period. The number of assignable time slices remaining during any 25.6-ms iteration period are stored in a counter (ITRS) stored in random access memory 29 .

For further explanation, FIGS. 6 to 8 are used in particular. The order in which the tasks or processes are executed and the number of time slices allocated to each process during a 25.6 ms iteration period are shown in a scheduled queue 368 . The scheduled queue 368 is stored in read-only memory 30 and its content is shown in FIG . Each of the processes enumerated in the queue 368 is associated with a process control block PCB which is stored in the random access memory 29 and which contains data concerning the status of the process shown in FIG . The addresses of the respective process control blocks PCB 1 to PCB 7 are stored in the scheduled queue 368 and labeled as follows: A (PCB 1), A (PCB 2), A (PCB 3), A (PCB 4), A (PCB 5 ), A (PCB 6) and A (PCB 7). Each of these PCB addresses is assigned a number indicating the maximum number of contiguous time slices associated with the process in question.

A register PCBIDX, located in random access memory 29 , provides an index to the current or active line or line in scheduled queue 368. This register PCBIDX is used by scheduler routine 360 to sequentially enable the operations or processes. For example, register PCBIDX points to the first line or row of scheduled queue 368 at the beginning of each iteration period. Thus, the timed or clocked interrupt process 361 is activated by the associated process control block PCB 1. Since the timed interrupt process 361 must be executed to its end, it is assigned an excess number of time slices (MSC 1-32). Under normal operating conditions, the timed interrupt process is completed in less than sixteen time slices. Thus, a number of time slices are left in each 25.6 ms iteration period so that other processes can be serviced. When a process is completed or its allocated time is consumed, the scheduler routine 360 is called and the register PCBIDX is incremented to now point to the next line or line in the scheduled queue 368 . For example, after the timed interrupt process completes, the block setup process 362 is activated by its associated process control block PCB 2, and the remaining time slices in the iteration period are depleted, if necessary, to complete this process. The remaining processes are activated in a similar manner if there is time available during any iteration period, in the order listed in the scheduled queue 368 . A dummy process (not shown in the drawings) is also included in the system in the case where no process is executed at all. This dummy process is a wait loop that is executed until the start of the next iteration period.

In the following, particular reference is made to FIGS. 6 and 8. The process control blocks PCB 1 through PCB 7 store data that provides the status of the respective processes 361 through 367 to the scheduler routine 360 . The first line of each process control block stores lock-up flags indicating, in the set state of the scheduler routine 360 , that the process in question need not be executed. Thus, a bit zero is an inhibited flag (IOW) which is set when the process requests input / output and indicates that it is ready to await completion of the I / O operation. Bit 1 is a block flag (CIW) set by scheduler 360 when it receives a lock request from the process indicating that it should not be executed during the current 25.6 ms iteration period. A bit 2 is a lock flag (PRW) indicating that the process should remain locked until it is re-enabled or released by another process. As scheduler routine 360 proceeds sequentially through scheduled queue 368 , scheduler 360 queries the lock flags in the active process control block to determine if the associated process should be executed.

The second word in each process control block (PCB 1 through PCB 7) serves as a counter (CSC) which indicates to the scheduler 360, from the associated time slices, the number of remaining time slices before the next process must be activated on the run-round. When a process is activated, one of the first functions to be performed by the scheduler 360 is to load this counter (CSC) with the number of allocated time slices specified for this process in the scheduled queue 368 . If 1.6 ms interrupts occur then the time slice counter (CSC) is decremented. When its count reaches zero, control is returned to the scheduler routine 360 .

The remaining four lines of each process control block (PCB 1 through PCB 7) store data indicating the status of the process when it returns control to the scheduler routine 360 . Thus, line 3 stores the contents of a memory extension register (MXR), line 4 the contents of a workspace hint (WP), and line 5 the contents of a program status register (ST). This data is loaded into the process control block by the scheduler routine 360 when the activated process is interrupted by the 1.6 ms clock or when the process exits and is blocked by a lock bit. Then, when the process is re-activated by the scheduler routine 360 , one can reload the contents of these four lines in the process control block into the appropriate microprocessor registers so that execution of the process can continue from where it was previously interrupted or stopped ,

Timed interrupt process 361 is executed until its completion during each iteration period because it has more timeslots associated with it than it possibly consumes when the system is operating properly. The block building process 362 consumes a large portion of the remaining time in the interpolation period until it has completed its function of setting up or building the next program block for interpolation. Thereafter, the block building process 362 is suspended, and it is not needed until after the completion of the timed interrupt process 361 for a sufficiently long time to check whether the end point of the current program block has been reached. There is then a considerable amount of time available during each iteration period, and this time is allocated to the remaining "background" prose listed in the scheduled queue 368 . A typical assignment of the time slices by the scheduler routine 360 is shown schematically in FIG. 9 for three iteration periods immediately following the transfer of a new block of data into the active interpolator buffer. Timed interrupt process 361 consumes a significant portion of each iteration period. However, the time required by the block building process decreases after the first iteration period. Subsequent iteration periods are similar to the second iteration period illustrated in Figure 9 until the end of the block is detected and the block building process 362 again takes a significant amount of time.

It is apparent that the scheduler routine 360 is a flexible and efficient means of allocating time to the various functions that the main processor must perform. Processes, and thus functions, can be easily added to the system or removed from the system by making additions or deductions to the scheduled queue 368 . Priorities can be changed by changing the order of the queue entries or by time slot assignments.

For the following explanations, in particular Figs. 2, 6 and 10 are used. The timed interrupt process 361 functions by outputting motion commands to the servomechanism interface circuits 7 and exchanging data with the programmable interface circuit 75 once during each 25.6 ms iteration period. With particular reference to FIG. 10A, it is noted that the timed interrupt process 361 is input from the scheduler routine 360 at the beginning of each iteration period at location 390 . The first function that is performed is to determine if the system is up or powered up, as illustrated by a decision block 394 . When the system is booting up, the start or start address of the PI map 105 in random access memory 29 is written into the data latch 124 in the DMA circuit 100 ( FIG. 4). This enables the programmable interface circuit 75 to address the appropriate or correct memory address so that it can then communicate with the PI mapping board 105 .

After start-up, the timed interrupt process 316 prepares a data transfer with the programmable interface 75 . First, it is checked whether data has been received from the programmable interface circuit 75 during the previous iteration period. This is done in a decision block 396 . If this is no, a fault has occurred and the system branches to a process block 397 which requests an emergency stop and gives an appropriate message for transmission to the front panel processor in a viewer or display buffer. Otherwise, the system checks a control program overlap flag, as indicated in a decision block 398 , to determine if the programmable interface processor has completed its functions during the previous iteration period. If not, an emergency stop is requested and an appropriate message is displayed, as shown in a process block 399 . Indicators labeled "receive data" and "control program overlap" are stored in the PI map 105 of the programmable interface 75 . They are set by the programmable interface circuit 75 .

Under normal circumstances, commands displayed next by a process block 400 are next executed to unpack or unpack data written from the programmable interface circuit 75 to the PI map 105 during the previous iteration. These data are distributed to different locations in random access memory 29 for use by other programs. Next, data from various locations is assembled in the random access memory 29 and stored at specified locations of the PI map 105 , as represented by a process block 415 . Such data may be generated by the block building process from the part program and may include, for example, an indication that an auxiliary function, such as a tool change or a pallet change, is to take place. After this data has been assembled in the PI map 105 , an instruction represented by a process block 401 is executed by the main processor to initiate the data transfer between it and the programmable interface circuit 75 . As already indicated, this instruction generates a non-maskable interrupt for the PI microprocessor 85 . Thereafter, the programmable interface circuit 75 asks the microprocessor 25 of the main processor direct memory access DMA, and the microprocessor 25 of the master processor gives its data bus 27, address bus 26 and the control lines WE and WRD freely to the programmable interface circuit 75 miles. As will be explained in detail later, the programmable interface circuit 75 then transfers 32 16-bit words of data from the PI map 105 in the random access memory 29 to the PI map 106 in the PI memory 94 . Later, during the same iteration period, the programmable interface circuit 75 then transfers 32 16-bit words of data from the PI map 106 in the memory 94 back to the PI map 105 in the random access memory 29, respectively. The data transferred in this way are shown schematically in FIG .

In the following, Fig. 10B is used. After the exchange of data with the programmable interface circuit 75 has been initiated, the main processor continues to execute instructions in the timed interrupt process. The next step in this process is to determine if a "foreplay" flag has been set, as illustrated in a decision block 403 . A "foreplay" is always requested during the first iteration period from any subprogram block containing an S word, a T word, or certain M codes defined in EIA standard RS-274-C. This gives the programmable interface circuit 75 an opportunity to act on the S, T or M code at the beginning of the block before interpolation begins.

The system next executes instructions as indicated at decision block 404 to determine if the emergency stop flag has been set. If so, then an emergency stop and position update routine 405 is executed. Otherwise, the fore flag is checked at decision block 406 and a "dwell" flag is checked at decision block 407 . If neither of these two flags is set, a "hold stop" flag is checked in accordance with a decision block 408 and a "manual" flag is checked in accordance with a decision block 409 .

If none of these flags is set, the interpolation routine 410 is entered. This routine is executed until its completion to generate an incremental motion command number for each axis of the machine tool 13 to be controlled. A servo operation routine 411 is then executed to output the movement command signals to the servomechanism interface circuit 7 . When an interpolator block 410 is bypassed, either no increment move command numbers are calculated, or move command numbers are calculated by a kickoff routine 412 that responds to operator commands. In either case, after issuing the newly calculated move commands to the servomechanism interface circuit 7, the flags for the foreplay request and feed hold request are reset, as shown in a process block 414 . The system exits at block 413 and returns to the scheduler routine 360 .

For the following explanation, Figs. 2, 6 and 11 are used. Front panel monitor 364 is the next process listed in scheduled queue 368 . It is used to input data received from the front panel processor and to maintain a front panel map 444 in main processor memory (Random Access Memory) 29 which displays the status of lights, switches and push buttons or buttons on the non-mobile control station 2 . When a byte of data has been received by the USART 37 , indicating that a change has occurred at the control station 2 , the microprocessor 25 enters the data and stores it in a data buffer associated with the front panel monitor 364 . Three such bytes of data include a complete message transfer, and when the third byte of data has been received, the front panel monitor 364 is released from the blocked state by the communications module associated with the USART 37 . The front panel monitor 364 may now be activated by the scheduler routine 360 .

When the spin routine 360 activates the front panel monitor 364 , entry occurs at a location 425 . Instructions, as shown in a process block 427, are then executed to initially bring the front panel imaging panel 444 into a starting state. A flag is then checked in accordance with a decision block 428 to determine if any communication errors have been reported by the communication module. If so, the data is ignored and the system branches to a subroutine 429 which prepares a message indicating the error for transmission to the front panel processor. Otherwise, as shown in a process block 430 , the two bytes of status data are loaded into the front panel map 444 . The system then exits to scheduler routine 360 at block 431 , and the process control block (PCB 4) is set to reenter decision block 428 when the next complete message is received. In addition, the CIW lock flag is set to ensure that reentry into the front panel monitor 364 does not occur during the same iteration period. This allows the timed interrupt process to act at least once on the changed row in the front panel map 444 before the data can be changed again by another transmission from the control station 2 .

For the following consideration again Figs. 1, 2 and 5 are used. It will be apparent that the front panel imaging panel 444 serves as an interface between the non-mobile control station 2 and the rest of the numerical control system. For example, four of the switches 15 on the control station 2 may be set by the operator to establish the manner in which the system is to operate, ie manually, automatically, via the keypad 14, or with a single block. Specified bits in a line of the front panel map 444 are dedicated to indicating the status of these switches 15 , and it is these bits that are checked by the processes in the front panel processor to create the mode. It will be explained in more detail below that one of the functions of the front panel processor is to periodically check the status of the control station switches 15 and update the main processor with any changes that have occurred. Over the cable 9 only changes are transmitted to the main processor. In this way the traffic is reduced. It should be understood that a modification is possible in the preferred embodiment discussed hereinabove in that the entire faceplate map 444 is updated or updated if any change has occurred. Although more data will then be transferred, the software superstructure will be reduced because the number of rows need not be analyzed.

Next, reference is made to Figs. 1, 2 and 6. In the execution of this display update process 367 , all data to be transferred from the control station 2 to a send buffer is assembled. First, a set of instructions is executed to determine if any messages should be displayed or displayed. This is done by checking the contents of eight message command blocks into which any routine executed by the main processor can enter a message command. Two message command blocks are reserved for operator alarm messages. The remaining six message command blocks are reserved for machine status messages. Many of these messages are "canned messages" in which only one message count is sent to the front panel processor.

From the above description, it can be seen that the main load of the main processor's interface connection with the machine tool I / O devices 13 and with the peripheral devices of the control station 2 is carried by the programmable interface processor and the front panel processor.

Operation of the programmable interface

First of all, FIGS. 1 and 3 are used. The programmable interface processor is programmed to operate as a programmable controller. Macro instructions of the type used in a programmable controller are stored in random access memory 94 as control program 464 . These commands are loaded into the Random Access Memory 94 by an operator or operator using the keyboard or keypad 18 of the program station 3 . The macro instructions are read into the microprocessor 85 from the USART 103 and then written to the random access memory 94 via the gates 97 . The program loader routine, which is used to execute the described operations, is stored in read-only memory 88 and is called when the operating switch is brought to the "load" position.

In executing the macro instructions constituting the control program 464 , a number of functions known per se are performed, including checking the status of selected bits in the PI map 106 and the I / O map 107 . Some macro instructions perform logical operations. Others set the state of selected bits in the display panels 106 and 107 in accordance with the results of logical operations. The macro command set used is essentially the same as that described in US 3,942,158. This macro command set contains three general types of commands: bit commands, word commands, and control commands. Bit commands and word commands are stored in two memory lines. The first row stores an operation code and three bits of a bit indication code, and the second row stores an operand address. The control commands consist only of an operation code. The bit commands contain the following:

The operations performed by these bit instructions can be defined as follows:

XIC - Check if status bit is closed or if the selected bit in the mapping table is in logical 1 state.
XOE - Same as XIC, but with regard to a status bit in the illustration panel that corresponds to an actuator.
XIO - Check if the status bit is open or if the selected bit in the mapping table is in the logic zero state.
XOD - As with XIO, but with respect to a status bit in the figure that corresponds to an actuator.
OTU - If conditions true, turn off status bit, or bring it to logical zero state, and if false, do nothing.
OTL - If conditions are true, toggle status bit or put it in logical 1 state, and if wrong, do nothing.
OTE - If conditions are true, toggle status bit, and if conditions false, turn off status bit.

The operand address corresponding to each of the above Associated with opcodes identifies the memory address of the picture panel word that selected Status bit contains. The Bitzeiger or Bithinweis, the the Operation code is assigned, identifies the place of the Status bit in the addressed mapping table word.

The control commands contain the following:  

The operations performed by these control commands can define as follows:

NOP - No surgery.
BND Branch End: Termination of a Boolean Sub-Branch.
BST Branch Start: Start of a Boolean Sub-Branch.
END - end of the control program.
MCR - Perform surgery on the main control bit.

The word-like commands of the programmable controller 32078 00070 552 001000280000000200012000285913196700040 0002002950979 00004 31959rgerätes  contain the following:

The operations performed by these word commands can be defined as follows:

TOF - If conditions are true, turn on output status bits, otherwise wait until the time runs out, and then turn off.
TONE - If conditions are true, wait until the time has elapsed, and then turn on output status bit, otherwise turn it off.
RTU - If conditions are true, wait until the timeout and then turn on the output status bit, otherwise stop the timer.
CTD - If conditions are true, decrease the count by one.
CTU - If conditions are true, increment the count by one.
PUT - If conditions are true, write the number in the microprocessor accumulator in the selected memory line, otherwise do nothing.
RTR - If conditions are true, reset the timer.
CTR - If conditions are true, reset the counter.
GET - Get the word from the selected memory line and save it in the microprocessor accumulator.
EQU - Is the value stored in the microprocessor accumulator equal to the value stored in the selected memory line?
LES - Is the value stored in the microprocessor accumulator smaller than the value stored in the selected memory line?

The operand address associated with each of these word-like opcodes is an 8-bit address from a memory line in random access memory 94 .

The user develops a control program 464 that uses these macro instructions. Such a program includes instructions that check the state of the PI map 106 to determine if an auxiliary function, such as a tool change or a pallet change, has been indicated by the part program being processed by the main processor. Further, this program includes commands that check the status of selected locations in the I / O map 107 to determine whether sensor devices of the machine tool 13 , such as limit switches, are in the proper state that permits a tool change or a pallet change. The B register in the microprocessor 85 is used to store the result of such check instructions. If appropriate conditions exist, other control program instructions set the state of the appropriate bit in the I / O map 107 . When the I / O mapping board 107 is subsequently output to the I / O interface circuit in the circuit board 8 , the appropriate operation or actuator is turned on or off to perform the indicated function.

For each of the macroinstruction operation codes, a macroinstruction interpretive routine is stored in the read-only memory 88 . When the mode switch 200 of the programmable interface 75 is in the "operation" position, the microprocessor 85 repeatedly executes a fetch routine that reads out the control program macro instructions sequentially from the random access memory 94 . Each macroinstruction operation code is translated by the programmable map non-latch PROM 100 into a number indicating the start address of its macroinstruction interpret routine. The system then jumps to the displayed macroinstruction interpretation routine (interpreter routine) and executes it to perform one of the above listed functions. Each interpreter routine contains a set of machine instructions selected from the Z-80 microprocessor instruction set.

The execution of the control program 464 as well as the transfer of data between the display panels, the main processor and the I / O interface circuit in the circuit board 8 , are synchronized with the operation of the main processor. Attention is drawn in particular to FIGS. 3 and 4. At the beginning of each 25.6 ms iteration period, the main processor, as an element of the timed interrupt process 361, addresses the NAND gate 133 in the DMA decode and control circuit 114 . As a result, an interrupt signal is generated on the NMI control line 137 , which is supplied to the microprocessor 85 .

For the following explanation, Fig. 12 is also used. The microprocessor 85 responds to this interrupt by executing an NMI service routine. It contains a set of commands collectively indicated by a process block 465 . When executed, other interrupts are disabled and the contents of the microprocessor registers are kept. The bit 7 in the microprocessor B register is then checked, as shown in decision block 466 , to determine if the overlap bit has been reset. If not, an error has occurred and the system branches to an overlap error routine 467 . There, an overlap error flag is stored for later transmission to the main processor. When received by the main processor, such an overlap error flag causes the output of a message to the display device of the non-mobile control station 2 .

Next, the status word is input from the control circuit 90 as indicated in a process block 468 , and the content is checked to see if the system is in the loading mode or if a major error has occurred. If the system is in load mode, as determined by a decision block 469 , it branches to a load mode routine 470 . If an error has occurred, as determined by a decision block 471 , the system branches to an error routine 472 . It is then checked whether the fault or fault has occurred in the programmable interface circuit board 6 or elsewhere in the system. If the fault is in the programmable interface circuit board 6 , a corresponding auxiliary action is initiated.

When the system is in the operating mode and the operation is suitably performed, a reset of the watchdog timer is made by a command corresponding to a process block 473 , and a routine corresponding to a process block 474 is executed to execute 34 16-bit words respectively from the main processor -PI- Figure 105 to enter. These 34 words are stored in the form of 68 8-bit words each in the display panel 106 of the programmable interface processor. This data transfer takes place with the aid of a block transfer instruction, which addresses the main processor memory 29 via the DMA circuit 110 and then sequentially reads out 34 lines thereof. Each of these memory read operations takes less than two microseconds, so the main processor will not be bound for a long time.

Subsequent to receiving data from the main processor PI mapping board 105 , the programmable interface processor performs I / O scanning in which data is communicated between its I / O mapping table 107 and the I / O interface circuit of the circuit board 8 , This is illustrated in FIG. 12B by a process block 475 that includes instructions that sequentially read 8-bit words from the I / O map 107 and transmit them via the DMA circuit 110 to the main processor data bus 27 . For every two of these 8-bit I / O map words, there is a corresponding 16-bit output circuit board to which the data is applied. Following the output or output scan, an input or input scan is performed with the I / O interface circuits of the circuit board 8 addressed sequentially by the DMA circuit 110 , and 16-bit data words representing the state or status of each Display devices of the controlled machine tool 13 , are entered. These 16-bit data words are stored in two associated lines of the I / O map 107 , respectively. Although the amount of time that the main processor is inactive during this DMA data transfer varies depending on the number of I / O devices to operate, in general for each read and write operation using the I / O interface circuit in FIG the circuit board 8 less than two microseconds necessary. The programmable interface circuit 75 thus represents a small time load for the main processor.

For the following consideration, Fig. 12B is again used. After the input / output scan has been completed, an overlap bit is set (ie, bit 7 in the microprocessor B register), as shown by process block 476 , and the system branches to a call routine 477 for the first macroinstruction to read the control program 464 and execute it. The operation of the NMI interrupt is completed at this juncture, and the programmable interface processor proceeds to sequentially execute the control program macro instructions, as indicated by process block 478 .

In addition to the Fig. 12B and Figs. 2 and 3 are used. The last macroinstruction in the control program 464 is an end macroinstruction. When this macro instruction is fetched, it is mapped into its interpreter routine (end interpreter routine), as shown in process block 479 .

One of the first functions of the end interpreter routine 479 is the output of 68 8-bit status words from the PI map 106 to the main processor PI map 105 . Contained in these status words is the flag "Overlap" and the flag "Data Transfer" as shown in FIG . Direct memory access is requested from the main processor to perform this transfer, and the transfer is accomplished using the block transfer instruction in the Zilog Z-80 microprocessor instruction set 480 . The overlap bit is then reset according to a process block 481 to indicate that the entire control program 464 has been executed, and the macroinstruction program counter (ie, the stack pointer or stack hint) is reset to point to the first macroinstruction in the control program 464 . The programmable interface processor then waits for the next NMI interrupt to occur during the next 25.6 ms iteration period.

In the above description, it will be understood that the programmable interface processor operates in parallel with the main processor to execute the control program 464 at the same time that the main processor performs its many functions. When the numerical control system is in the operating mode, the main processor is busy or busy to execute the scheduled interrupt process 361 and the other processes listed in the scheduled queue 368 . The interpolation routine alone requires significant main processor execution time since considerable arithmetic calculations are to be performed, as disclosed in US Pat. No. 3,728,528.

The parallel operation of the two processors is illustrated in FIG. 13. At the beginning of each iteration period, the main processor initiates an NMI interrupt with the programmable interface processor and then proceeds to execute the timed interrupt process 361 . In the meantime, due to the NMI interrupt, the programmable interface processor begins to transfer the contents of the PI map 105 from the main processor by sequentially requesting the direct memory access DMA and directly reading from the main processor memory 29 . The programmable interface processor, therefore, will soon start updating its input / output map 107 by again requesting a sequence of DMA transfer operations from the main processor address space. Although the data transferred during the input / output scan does not necessarily include the main processor, the main processor data bus 27 and the main processor address bus 26 are used, and the operation of the main processor must therefore be shut down during this operation.

Referring to Fig. 13, it will be noted that the programmable interface processor executes its control program 464 subsequent to the input / output scan. The time to perform this function depends on the length of the control program 464 , but in no case extends to the next iteration period. If this still occurs, the overlap flag will not be reset and an error will be displayed to the main processor. When the programmable interface processor completes the execution of the control program 464 , it makes a series of DMA requests from the main processor during which it transfers the contents of the PI map 106 to the main processor memory 29 . The programmable interface processor is then idle for the remainder of the iteration period, but is reactivated to repeat the same cycle when an NMI interrupt is requested at the beginning of the next iteration period.

A modification of the preferred embodiment in that adjustment of the operation of the main processor during the input / output scan is avoided is possible. This modification requires that the input / output interface circuit in the circuit board 8 be connected to the data bus 82 and the address bus 83 of the programmable interface 75 . The reason why this alternative arrangement is not preferred, however, is that the programmable interface circuit 75 of the preferred embodiment can be completely removed from the numerical control system, and that the main processor can be programmed to operate the I / O interface circuits of the circuit board 8 directly to control. The programmable interface circuit 75 may therefore be offered as an option or optional unit.

The advantages obtained by the simultaneous or parallel operation of the programmable interface processor with the main processor are numerous. First of all, the time overhead of the main processor is minimal. The main processor need not wait for the control program to execute, but may instead stop execution of the scheduled interrupt process 361 and turn to other processes listed in the scheduled queue 368 . The only time overhead of the main processor are the three short time periods during which DMA requests are granted to the programmable interface processor.

A second major advantage is the ease with which the programmable interface processor can be programmed by the user. Since the control program execution is removed from the main processor sequence, the only time constraint is that the control program 464 is executed in less than 25.6 ms. However, this is more than enough time for any reasonably reasonable control program, 464 so that in practice no difficult time problems are to be solved by the programmer. In addition, since sufficient execution time is available, programmable controller type instructions, ie, macro instructions, may be used to develop the control program 464 . These commands, unlike microprocessor language, are easy to learn and understand by the user. These macroinstructions may be interpreted directly or "on line" by the microprocessor 25 to perform the required functions.

Operation of the non-mobile control station

While the programmable interface processor establishes the interface connection of the numerical control system with the individual input / output devices of the machine tool 13 , the front panel processor operates or actuates the peripheral devices that establish the interface connection of the numerical control system with the operator. Like the programmable interface processor, the front panel processor frees the main processor from a significant amount of time and allows flexibility in the type and number of peripheral devices used. The front panel processor also facilitates the addition of other features or measures not found in conventional numerical control systems. The peripheral devices can be housed in a separate, remote station.

FIG. 15 is for further explanation . The front panel processor is an event-driven system having an operating system 500 which in turn includes a scheduler routine and a set of monitor operator routines. Operating system 500's scheduler area recognizes the front panel processor events as they occur and, based on these events, selects tasks to be performed. If more than one task is due to be executed at any one time, the task with the highest priority is executed first. A list of these tasks along with their priorities are stored in a task queue 501 . The number and nature of the tasks to be performed by the front panel processor can vary considerably, depending on particular options that can be selected by the user. In the embodiment shown in FIG. 15, these tasks include a switch monitor routine 502 , a desk lamp driver routine 503 , a display guide routine 504 , a keypad routine 505, and a CRT display update routine 506 . An additional task or task is called "task-n-routine" 507 . This is to illustrate that other tasks can be performed by the front panel processor. In fact, one of the main advantages of the front panel processor is that tasks can be added to the system or taken away from the system in conjunction with little or no change in operating system software.

The operating system 500 of the front panel processor recognizes 18 different events. Many of these events are generated by the routines 502 through 507 as they perform their tasks or tasks, and others are generated by the front panel processor hardware.

Referring to Figs. 5 and 15, it will be noted that interrupts generated by the main processor USART 220 , auxiliary USART 294 , keypad interface 235 , CRT interface 250, and tape reader 297 are each communicated to the scheduler through associated interrupt service routines , As already explained, the microprocessor 221 is instructed by the 4-bit code generated on the bus 291 by the interrupt and I / O control circuit 243 for the appropriate interrupt service routine. In particular, an interrupt on the control line INT1 directs the microprocessor 221 to a main processor USART service routine 508 and an interrupt on the control line INT2 directs it to either an auxiliary USART interrupt service routine 509 or a 640 microsecond service interrupt service routine 510 , An interrupt generated on the control line INT3 refers the microprocessor 221 to a keypad interrupt service routine 511 , and an interrupt generated on the control line INT4 instructs the system to a CRT visual display interrupt service routine 512 . An interrupt on control line INT5 directs the system to a guard timer interrupt service routine 513 and interrupts on control lines INT6, INT7 direct the system to a tape reader interrupt service routine 514 .

The interrupt service or interrupt service routines 508-514 report to the scheduler in the operating system 500 . These reports include a first number indicating the occurred event and a second number identifying a particular related task. The scheduler in operating system 500 uses these two numbers as indices in sheets or tables that define what has to be done next. The events recognized by the scheduler are summarized in Table C below.

Table C

The front panel processor is a finite state machine, and thus the tasks performed by the routines 502 through 507 are always in a defined state at all times. These states are the following:

SCPT - The task is currently being executed by the front panel processor.
SEXT - The task is listed in task queue 501 waiting for processor time.
SSLP - The task is sleeping and waiting for a preset amount of time to pass.
SIOW - The task is waiting for an I / O operation to complete.
SNUL - The task is waiting for activation by an event that identifies the task. Various events can activate the task from this state.

It is of course the function of the scheduler to recognize the defined events as they occur and to bring the various tasks into the appropriate state. For example, whenever the CRT viewer 17 generates a vertical retrace signal, the microprocessor 221 is interrupted by the control line INT4, and the CRT display interrupt service routine 512 is executed. The purpose of this interrupt driven event is to initiate the updating of the CRT viewer 17 with new data during the 3.1 ms vertical retrace period.

It is the task or task of the CRT visual display update routine 507 to perform the actual data transfer, and thus it is the function of the scheduler to enable the task number or task count 7 when the CRT visual display interrupt service routine 512 reports this event. The task is accomplished by loading the task count, ie, 7, into task queue 501 , where execution occurs when higher priority tasks are completed in the task queue. Due to the vertical return event, task 7 is therefore brought from state SNUL to state SEXT.

When task 7 in the queue 501 becomes the highest priority task and the previous task has been terminated or stalled, the CRT visual display update routine 506 is activated and executed by the scheduler, ie the state of task 7 changes from SEXT to SCPT.

From the above discussion it can be seen that the tasks are moved from state to state by the scheduler in response to events reported to the task. The state changes that occur are outlined in the state event table of FIG .

The operating system 500 of the front panel processor is designed for maximum flexibility as the type and number of peripheral devices associated with the non-mobile control station 2 will vary considerably depending on the needs of the user. For example, when the CRT viewer 17 is changed, due to the hardware differences, it may be necessary to change the display guide or display processing routine 504 , the CRT display update routine 506, and the CRT display interrupt service routine 512 . The rest of the operating system 500 will not be changed. The priority with which tasks are executed can be easily changed by changing the priority numbers stored in the task status blocks.

The tasks in the front panel processor show a Operation to data from a peripheral device to enter data into a task transfer queue to write and then call the communication routine, to transfer the data to the main processor.  

Operation of the serial data transmission

The serial data transmission between the main processor and the non-mobile control station 2 is a full-duplex data connection of the RS-232 type. The routing and routing of the data communications is performed by a communications software module that includes a USART interrupt service routine and a communications routine. The communication software module is essentially the same on the main processor and on the front panel processor.

The main purpose of the communication software module is to create a log to which the main processor and the front panel processor are subject to between them commands or messages are transmitted should. The communication software module also receives Requirements for transmitting messages resident Processes or tasks. He transmits the message Using the appropriate protocol, and he reports the requesting process or the requesting task, when the transfer is completed. The communication Software module also receives messages via the serial data connection, stores them in data buffers that from the resident task or the resident process are set up and notify the resident Task or the resident process that reception has ended or that a transmission error has occurred is.

In the following reference is made to FIG. 17. A message transmitted over the data connection consists of a header segment, a text segment and a block check character BCC. The header segment consists of three bytes, designated HC1, HC2 and HC3. The first byte HC1 indicates the number of bytes in the text segment. The second byte HC2 is the device code for the receiving task or the receiving process. The third byte HC3 is a command or control code. The text segment can have a length of 1 to 255 bytes. The BCC character is a single byte which is calculated by subjecting each byte in the text segment to a logical exclusive OR operation.

If the first byte in the message (HC1) is a Zero, the message is interpreted as a command. The third byte HC3 identifies the particular command for the receiving task or the receiving process.

For the following explanation, FIG. 18 is used. It is the responsibility of the tasks in the front panel processor and the processes in the main processor to obtain data buffers and to populate them prior to invoking the communication software module for transmission. Such a buffer 570 is here referred to as process transfer queue or task transfer queue. Each buffer is associated with a task or process that transmits data over the serial data connection. Furthermore, associated with such a process or task is an IOPB block of data 571 which stores information needed by the communications software module to service the sending or transmitting task. IOPB block 571 stores a queue pointer indicating the address of the associated transmission queue. Further, it stores the address of any buffer set up by its associated task of receiving data. In addition, it stores a text length character (HC1), a device code (HC2), and command data (HC3) needed by the communication software module to form a message.

A message transfer is initiated by a task or process that loads its device code or device code into a transfer request board 572 and calls the communications software module 573 . The device code is used by the routine in the communication software module 573 to find the header data and the text of the message to be transmitted. This is accomplished by mapping through a device code board 574 which stores a list of IOPB block memory addresses for all device codes. The header data stored in IOPB block 571 is then used to form the header segment of the message, and the queue pointer stored in the IOPB block is used to locate the message text.

A similar process or process takes place at the receiving end of the message. The second character (HC2) in the received message is the device code for the process or task that is to receive the message. This character is mapped via the device code board 574 to find the correct IOPB block 571 . The address of the data buffer in which the message text is to be stored is found in the IOPB block 571 .

Claims (13)

1. Numerical control system containing

• - a main processor with
  • an input device for inputting blocks of partial program data,
  • a memory device for storing data and
  • output means for outputting motion command signals to servomechanisms of a machine tool, the main processor being operable (functions of the main processor)
    • a part of the data contained in the partial program for executing numerical control functions is converted into motion command signals and output to the servomechanisms, and
    • a further part of the data contained in the subprogram for displaying auxiliary functions to be executed by individual devices on the machine tool is converted into individual logic signals and stored in the memory device of the main processor, and further comprising
• I / O interface circuits, via which the numerical control system is connected to the individual devices of the machine tool,

characterized,

• in that a programmable PI processor ( FIG. 3) associated with a programmable interface PI ( 75 ) is connected to the main processor ( FIG. 2) and the I / O interface circuits ( 8 ), and
• - That the output of the movement command signals to the servomechanisms of the machine tool ( 13 ) takes place once during a defined iteration period and
• - That the programmable PI processor ( Fig. 3) during each of these iteration periods is once operable (functions of the programmable PI-processor) that
  • Data is input to the programmable PI processor ( FIG. 3) which
    • Display the state of the individual devices on the machine tool via the I / O interface circuits ( 8 ) and
    • display the auxiliary function to be executed, this data being stored in the form of the individual logical signals in a PI mapping table ( 105 ) of the memory device ( 29 , 30 ) of the main processor ( FIG. 2),
  • Stored control program is executed by using this, in the programmable PI-processor (Fig. 3) input data in the programmable PI-processor (Fig. 3) and in the execution of the control program data for controlling the individual devices on the machine tool - ( 13 ), and data indicative of completion of the auxiliary functions are obtained, and
  • the data serving to control the individual devices on the machine tool ( 13 ) are output to the individual devices via the I / O interface circuits ( 8 ) and the data indicating the completion of the auxiliary functions are sent to the PI mapping board ( 105 ) of the memory device ( 29 30 , 30 ) of the main processor ( FIG. 2).

2. A numerical control system according to claim 1, characterized in that the functions performed by the programmable PI processor ( Fig. 3) are executed while the main processor ( Fig. 2) performs its functions. A numerical control system according to claim 2, characterized in that the functions performed by the programmable PI processor ( Figure 3) are synchronized with the functions by means of a signal (NMI) generated by the main processor ( Figure 2), which are executed by the main processor. 4. Numerical control system according to one of claims 1 to 3, wherein

• the main processor contains a microprocessor connected to the memory means of the main processor via a main data bus and a main address bus,

characterized,

• in that the programmable PI processor ( Figure 3) includes a PI microprocessor ( 85 ) coupled to a PI memory ( 88, 89, 94 ) via a PI data bus ( 82 ) and a PI address bus ( 83 ). connected is,
• - That a direct memory access circuit ( 110 ) is provided which connects the PI data bus ( 82 ) and the PI address bus ( 83 ) to the main data bus ( 27 ) and the Hauptadreßbus ( 26 ), and
• in that the programmable PI processor ( Figure 3) is further operable due to the instructions stored in the PI memory ( 88, 89, 94 ) and executed by the PI microprocessor ( 85 )
  • the data inputted from the PI map ( 105 ) in the memory means ( 29 , 30 ) of the main processor ( FIG. 2) indicative of the auxiliary function to be performed is stored in a PI map ( 106 ) of the PI memory ( 88, 89 , 94 ), and
  • the data to be output to the PI map ( 105 ) of the memory means ( 29, 30 ) of the main processor ( Fig. 2) indicating the completion of the helper function is output from the PI map ( 106 ) of the PI memory ( 88, 89 , 94 ).

5. Numerical control system according to claim 4, characterized

• - That the individual devices are connected to the machine tool ( 13 ) to the main data bus ( 27 ) and the Hauptadreßbus ( 26 ) via the I / O interface circuits ( 7 , 8 ) and
• - That by means of the programmable PI-processor ( Fig. 3) via the direct memory access circuit ( 110 ) data from the individual devices on the machine tool ( 13 ) is input and output to the individual devices of the machine tool ( 13 ).

6. A numerical control system according to any one of claims 1 to 5, wherein the numerical control system comprises a keypad and a display, characterized by

• an FP processor ( FIG. 5) associated with a front panel FP, having an FP microprocessor ( 221 ) which is connected to an FP memory ( 224, 225 ) via an FP data bus ( 223 ) and an FP address bus ( 222 ) . 226 ) is connected,
• Communication means ( 9, 37, 220 ) for connecting the FP microprocessor ( 221 ) to the main processor ( Figure 2),
• a keypad interface ( 235 ) for connecting the FP microprocessor ( 221 ) to the keypad ( 14 ),
• - A CRT interface device ( 250 ) for connecting the FP microprocessor ( 221 ) with the visual display ( 16 , 17 ) and
• a switch interface means ( 265 ) for connecting the FP microprocessor ( 221 ) to an FP switch set ( 15 ), the FP processor ( Fig. 5) being based on instructions stored in the FP memory ( 224, 225, 226 ) and are executed by its FP microprocessor ( 221 ), is operable to receive data from the keypad ( 14 ) and FP switch set ( 15 ) to the main processor ( FIG. 2) and from the main processor ( FIG. 2) to transmit to the visual display ( 16 , 17 ).

7. Numerical control system according to claim 6, characterized

• - That the communication means ( 9, 37, 220 ) connecting the FP microprocessor ( 221 ) with the main processor ( Fig. 2), a serial data connection ( 9 ).

8. Numerical control system according to claim 7, characterized

• - That the communication means ( 9, 37, 220 ) connecting the FP microprocessor ( 221 ) to the main processor ( Fig. 2) further
  • - Have a first universal receiver / transmitter device ( 37 ), which connects the serial data connection ( 9 ) with the main processor ( Fig. 2), and
  • - Have a second universal receiver / transmitter device ( 220 ), which connects the serial data connection ( 9 ) with the FP microprocessor ( 221 ).

9. Numerical control system according to one of claims 5 to 8, characterized

• in that the memory means ( 29 , 30 ) of the main processor ( FIG. 2) stores an FP mapping table ( 444 ) and the FP memory ( 224, 225, 226 ) stores another FP mapping table ( 233 ), each representing the state of the Display FP switch set ( 15 ), and
• - That the FP processor ( Fig. 5) is operated such that
  • the current state of the FP switch set ( 15 ) is periodically compared with the state of the further FP mapping board ( 233 ) stored in the FP memory ( 224, 225, 226 ) and, in the event of a difference, the further FP mapping board ( 233 ) in the FP memory ( 224, 225, 226 ) is updated by changing its contents, and
  • the FP mapping table ( 444 ) in the memory device ( 29 , 30 ) of the main processor ( Figure 2) is updated by transmitting data to the main processor ( 2 ) indicating the corresponding changes made in the in the memory device ( 29 , 30 ) of the main processor ( Fig. 2) FP mapping board ( 444 ) are to be executed.

10. Numerical control system according to one of claims 1 to 9, characterized

• - that the control program contains macro instructions,
  • - which are of a type as used in a programmable logic controller and
  • - which are stored in a control program area ( 464 ) of the PI memory ( 88, 89, 94 ), and
• the macro instructions of the control program are executed by being converted by corresponding macro instruction interpretation routines stored in the PI memory ( 88 , 89 , 94 ).

1. Numerical control system according to claim 10, characterized in that

• - that the programmable PI processor ( Figure 3) comprises a PI universal receiver / transmitter ( 103 ) connected to the PI data bus ( 82 ) and to the PI address bus ( 83 ), and
• - That the PI microprocessor ( 85 ) is operable to receive the macro commands via the PI universal receiver / transmitter ( 103 ) from a program console station ( 3 ) and into the control program area ( 464 ) of the PI memory ( 88 , 89, 94 ) writes.