DE2822363A1 - BELT SYSTEM - Google Patents

Description

Applicant; Stuttgart, May 19, 1978

Rediffusion Reditronics Ltd ", P 354-8 S / kg La Pouquelaye, St. Helier, Jersey, Channel Islands

Belt system

The invention relates to a tape system having means for recording information signals on the tape and playing back the recorded information aaignale, in particular it is a tape system whose Operation can be controlled automatically

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There are belt systems known that make use of endless belt loops, which in cassettes or are otherwise accommodated and on which an information signal in a track and in a a control signal is recorded on another track »The control signal track contains at predetermined intervals Audio frequency impulses, the duration of which is determined at the time of recording «By setting the length With these audio frequency impulses it is possible to exercise two control functions · One is used to control the dee Tape drive in such a way that the tape stops at the end of a certain section, while the other the Recording circuit controls to record information on a following section of tape to allow or to block «The system is therefore time-conscious and responds accordingly.

The known system has found commercial application but is not flexible. For example, if the information signals from several consecutive, consist of independent pieces of music, it is not possible to choose any of the recorded pieces so that unwanted repetitions cannot be avoided after The tape has been recorded · In particular, certain tracks cannot be localized for playback will·

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Accordingly, it is the object of the invention to provide a belt system that addresses these difficulties avoids

The invention consists in that a tape system of the type described in the opening paragraph has a device for recording from digital signals identifying selected portions of the tape and information signals contained therein to the tape, a device to play back the recorded digital signals and means for generating system control signals as a function of the reproduced digital ones Having signals.

The information signals and the digital signals can be on separate tracks but also on a single track in different frequency bands to be recorded"

The control signals essentially identify predetermined portions of the tape, and can be used for one A variety of different control purposes can be used, for example to start and stop tape playback, Controlling tape playback so that selected portions of the tape are in any desired episode can be played, while other tape sections are not taken into account, for regulating the belt speed or to control auxiliary equipment, such as additional Tape machines «,

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The present invention also relates to a method to control a tape system depending on a tape that is played on a machine, which formed one component of the system. In this process, digital signals are recorded on the tape, to identify selected sections of the tape and information signals contained therein, and the recorded digital signals are reproduced and dependent on the reproduced digital signals system control signals generated.

In one embodiment of the invention, a digital code system is used, that of data pulses Makes use of which represent the encoded information and clock pulses for timing and processing of the data pulses "

The clock and data pulses consist of two discrete frequencies that are recorded simultaneously or sequentially can be, when playing, the two frequencies are determined by frequency-selective switches, converted into DC voltage signals and then digitally processed in the usual way. This system can be used for this be able to display or represent a specific section or location on an endless loop of tape and determine whether a specific Section may or may not be dubbed by the user of the tape at the will of the editor As part of these functions, stop signals are also derived in order to peg the tape for subsequent playback to bring a certain place "

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The invention is hereinafter based on dea in the Drawing illustrated embodiment described and explained in more detail. Show it

Fig «, 1 to 3 circuit diagrams of a tape coding circuit,

FIG _o 4 is a diagram of signals appearing in the encoding circuit according to FIGS. 1 to 3,

Figo 5, 6 and 7 the circuit diagram of a decoding circuit,

8 to 12 show the circuit diagrams of auxiliary circuits which interact with the decoding circuit according to FIGS. 5 to 7,

13 and 14 are schematic circuit diagrams relating to the circuit arrangements according to FIG to 12 alternative circuit arrangements and

15 and 16 additional circuit arrangements which in connection with the circuit arrangements 8 to 12 can be used ο

The control circuits of the tape system, which will be described below with reference to the drawings, meet the requirements following functions:

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1. The control of the movement of the magnetic tape via the recording, reproducing and erasing heads the machine,

2 · in monitor or playback mode, the representation of the identification code for the information which is to be played next (stationary tape) or that is currently being played (moving tape),

3, in the recording mode, the reproduction of the identification code, which is assigned to the information that is to be recorded (stationary tape) or that is currently being recorded (moving tape), and

4 ·. additionally for recording and monitoring operation the. Delivery of an indication of whether a record possible or whether the selected Plata is reserved for an existing recording which should not be overwritten · In the latter case, a preamble and hole oscillator is used locked and the recording amplifier from the recording head separated"

The control functions are performed by circuit arrangements as a function of predetermined coded information met, which are recorded on a separate control track of the tape, which are independent in playback mode is monitored by the operating mode of the main amplifier of the unit «

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The coded information is in the form of seven short time segments or periods during which either a signal is present at the frequency f1, which corresponds to a logic level "1", or during which there is no signal which corresponds to a logic level ^M 0 " followed by the same period of a signal with a second frequency f2. Whether or not a signal of frequency f1 is present during each of the seven periods is determined by the logic level of the relevant bit of the BGD code of the identification code (BCD = Binary Coded Decimal) If, for example, the identification code is 39, the BCD code for this is 0111001 »As a result, the signal on the tape is then f1, f2, -, f2, -, f2, f1, f2, f1, f2, f1, f2, -, f2. It should be noted that the last-digit bit (LSB) is transmitted first «

An eighth period with the signal of frequency f1 indicates that on the designated by the identification code Recording is possible while the absence of a signal in the eighth period indicates that a recording is blocked at this point. The eighth period associated with the signal f1 has a long one Period of the signal followed by the frequency f2. Even though the length of this last period need only be about twice as great as the short periods for this one Period chosen about one hundred times the short period when local recording is disabled, and about five hundred times the short period if local recording is allowed so that the tapes,

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one for use with the system described carry suitable recording, are also useful in existing playback machines.

The reaction of the audio amplifier and the signal routing within the playback unit depend on the operating mode of the unit from «Unless the signal amplitude is too large, this change in response behavior and the Signal routing effected by means of solid-state analog switches.

These switches are controlled by means of DC voltages derived from operating mode selection logic. The specific voltages that exist in each case depend on the selected operating mode, a push-to-talk button and the Tape read control signals from "

In the following description of circuit arrangements a positive logic is assumed in which the logic level "1" of the positive supply voltage of the logic circuits corresponds, while the logic level "0" corresponds to the negative supply voltage.

As Fig. 1 shows, the duration of the frequency pulses, which form the code pulses, determined by an astable oscillator, which is made up of components 1 and 2 is formed. When a release switch 5 is closed by the user, a monostable oscillator, which is formed by the components 4 and 5, generates a pulse that the state of a bistable element 6 to Oscillator keying changes which allows the timer oscillator 1, 2 to operate.

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The initial state of the oscillator output signal, which appears at terminal 7, has the logic level "1", so that the state at the output of NICHiD element 8, which appears at terminal 9, is a logic "0" when the oscillator closes starts working, the output signal of the NOT gate changes to "1", and this change causes a divider 10 (FIG. 2) to change its initial state, in which it ^{supplies a logic 11} O "as an output signal, to a state This level change is fed to the clock input of a parallel-serial storage register 11 , 13 and a record inhibit / enable switch 14 are inputted into the buffer register. The input takes place because the register has moved from the initial state of a parallel-series flip-flop I5 to parallel bet rubbed is set. After half a period, the output 16 of the divider 17 changes its state, that is to say that the output signal ^{rises from the level 11} O "to the level" 1 "and thereby changes the state of the parallel-series flip-flop 15. This causes the buffer register 11 to open At the same time, the output 18 of the divider 17 assumes the logic level "0" and thereby prepares a data gate 19 so that the logic level at the output of the buffer register 11 reaches the terminal via a NOT element 20 and the data gate 19 can · Terminal 21 is with the control input

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a clocked data oscillator 22 connected (Fig. 3). If at the output of the buffer register 11 (FIG. 2) a logic "1" is present, the data oscillator 22 is caused to oscillate at the frequency f1 · If However, the output signal of the buffer register is "0", then the data oscillator 22 is on Swinging prevented.

After a complete period of the sampled oscillator 22, the outputs of the divider 17 (FIG. 2) change their states again. The output 18 rises to the logic level "1" and thereby closes the data gate, whereby the data oscillator 22 (FIG. 3) is blocked will. The output 16, which is at the logic level "0", is connected to a clock gate 23 which receives a second input signal from the output of the parallel-series flip-flop 15. Since this output is at the level ^fl 0 ^M , both input signals of the clock gate are at the level "0" and the output signal fed to the Klesme is at the logic level "1". This output signal releases the sampled clock oscillator (FIG. 3), which oscillates at the frequency f2. The output signal of the clock gate 23 with the level of the logic "1" is also fed to the input of a counter 26 (FIG. 2), the value of which is increased by one.

After another half a period, the sigaal rises at the output 16 of the divider 17 again from a logical "0" to a logical "1". This transition, which is fed to the clock input of the buffer register 11, has the effect

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a feed of the ones contained in the buffer register Information about a position, so that the data status of the penultimate buffer is supplied to the NOT element 10 will «, The sequence described above, apart from the change from parallel operation to series operation of the buffer register 11 is repeated after every two periods of the clocked oscillator 1, 2 (Fig, 1) until the counter reaches a predetermined level, which in this case is equal to eight. When the eighth clock pulse is transmitted, the counter reaches "eight" and the corresponding output 27 rises to the Level "1", as a result of which a long tone timer 29 is triggered via the NOT element 28. After triggering the output 30 of the timer 29 rises to the level "1" and thereby holds the keyed clock oscillator 25 (Fig. 3) via terminal 24, while the oscillator flip-flop 6 (Fig. 1) is reset via terminal 31 · The signal from flip-flop 6 of the oscillator component is supplied, rises to the logic level "1", stops the sampled oscillator 1, 2 and sets the divider 10 and 17 (Fig., 2) back »The divider 17 in turn represents the parallel / series flip-flop 15 to the state back, which corresponds to the parallel operation of the buffer register 11, and brings the counter 26 back to the zero state.

The period of time during which the output signal of the timer 29 maintains the "1" level holds from the state of the Admission switch 14 from »If admission operation is permitted is, the timer 29 remains switched on for about five times as long as if a recording mode is not permitted «

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This measure has the purpose of also using tapes encoded for use in the system described to make suitable in known systems.,

If necessary, the function of the recording switch 14 be taken over by a spring-loaded push button switch 32 and a memory flip-flop 33 (Fig. 2), the is automatically reset after each coding process o This training prevents the recording permitting code is inadvertently recorded if the user fails to reset the record switch

The voltage applied to terminal 34 (Figo 2), the via the terminal 35 to the Plipflop 6 (Fig. 1) the voltage applied to terminal 36 (Figo 3) and the voltage applied to terminal 37 (FIG. 2) display devices are supplied to allow the user to monitor the coding process »

FIG. 4 illustrates signals that are generated in the mode shown in FIGS. to 3 circuit arrangement shown occur. The signals are denoted by numbers which are the same as the reference numbers of the components at their outputs these signals appear. The signals shown correspond to the identification code, which is indicated by the Switches 12 and 13 are selected and the one for the number 99 is characteristic, so that the signal appearing at the output 38 alternating pulses of the frequencies f1 and f2 without Spanned space, namely f1, f2, f1, f2, f1, f2, f1, f2, f1, f2, f1, f2, f1, f2.

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A specific location on a tape can be identified by a selected code by the Switch 12, 13 is set and switch 14 (or 32) "is operated ο The output signal at terminal 38 is not shown recording heads supplied, which cause that the code signal is recorded on a track separate from the track containing the information signals such as music. When the tape is played back, so are the recorded ones Reproduced code signals and fed to a control circuit as will be described below.

Figures 5, 6 and 7 illustrate elements of a Decoding circuit for processing the reproduced identification code ο

As can be seen from Pig _o 6, when the decoder circuit is switched on for the first time, a reset circuit consisting of a capacitor 39 and a resistor 40 supplies a positive pulse to a data delay flip-flop 41, the output 42 of which is thereby reset to the state of a logic "0". In addition, the outputs of a data shift register 43 are reset to a logic "0", so that conventional displays 44, which are fed via decoder 45, show the value 00. Likewise, the output 46 of a recording flip-flop is brought to the state of a logic "0", whereby local recording is prevented by causing a circuit part 48 to issue a recording-free signal

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to be removed from a terminal 4-9 «, finally the output $ 0 of a drive control flip-flop 5i is set to a logical" 0 "in order to apply a signal to a terminal 52, which disconnects a drive motor 53 and drive coils 5 ^ ( Fig "7) has the consequence

When a starting pulse to terminal 55 is supplied (Fig _o 6), which can either be supplied from a microphone switch or a timer, it appears the drive control flip-flop 5Ί "which then changes its state on the reset input 56th ^{The logic W} 1 "then appearing at the output 50 is fed via the terminal and a current amplification transistor 57 (FIG. 7) to the control electrode of a triac 58, which is switched on. In this way, alternating current reaches the synchronous drive motor 52o 50 via terminal 52 to a solenoid delay circuit 59, 60 and 61 which, after a delay time determined by resistors 62, 65 and a capacitor and allowing the drive motor to reach its final speed, switches on transistors 65 and 66 and thereby switches on the Magnetic coil 53 energized to allow the start of the tape "The magnetic coil 53 is supplied by a power supply unit that is only slightly regulated" However, the charge stored in the capacitor 67 is sufficient to ensure that the magnetic coil is attracted during the current supplied by the power supply unit sufficient to keep the solenoid in the operating state «

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The negative transition of the output signal 68 of the drive control flip-flop 51 (FIG. 6) triggers a Startimpul3 blocking element 69, the output 70 of which is connected to an input of a drive control gate 71, which prevents the output signal of a long-pulse detector from component 72 and a Traneistor 73 is formed, changes the state of the drive control flip-flop 51 during the time during which "Compatible" -? ^r J is present on "the output of the start pulse-locking member 69 is also the reset inputs of a data pulse delay flip-flop 41 and the data memory 43 in order to delete all information that could be present in these registers ₀ The last-mentioned function is superfluous for the first operation after switching on, since both registers are reset when switching on, but is required for the following operations "

The tape continues the run it has started, so that playback of the tape is possible. However, it is as first operation not possible to make a recording because the recording flip-flop 47 is the Record blocking status has "

The pre-recorded on the tape control signals induce a voltage in a read head which is connected to terminals 74 (Figure "5) _o This voltage is amplified by amplifiers 75 and 76. The gain of amplifier 75 by resistors, and 78 and that of the amplifier 76 determined by resistors 79 and 80 »capacitors 81, 82 and

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serve to reduce the size of stray signals, the following stages are fed when the arrangement in the recording mode works «The output signals of the amplifiers are via a Low-pass filter, which is formed by a resistor 84 and a capacitor 85, and blocking capacitors 86 and 87 two frequency-selective switches 88 and 89 which act as pulse detectors «

The frequency selective switches 88 and 89 generate a logic output "1" if the frequency of the input signal is within predetermined limits. The upper limit frequency of the data pulse detector 88 is determined by the network formed by resistors 90, 91 and capacitor 92 is formed and is set to f1 + 10%, while the lower limit frequency by the resistors 93, 9 ^ and the capacitor 95 is determined and set to f1-10%. The upper limit frequency is in the same way of the clock pulse detector 89 determined by resistors 96, 97 and the capacitor 98 and set to f2 + 10% set, while the lower limit frequency is determined by the resistors 99, 100 and the capacitor 101 and is set to f2 - 10%. To prevent dropouts on the tape from causing pulse detection errors lead, the output signals of the switches are prevented from entering the state of a logical "O" to be assumed if a signal failure is shorter than one

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predetermined period of time which is formed by the networks formed by the components 102, 103 and 104, 105 is fixed. Diodes 106, 10?, 108 and 109 prevent destruction of the frequency-selective Switch 88, 89 due to excessively large input signals "

When a data pulse of frequency f1 is present on a tape, it causes the output signal of the data pulse detector 88 assumes the value of a logic "1", which in turn via the terminal 110 to Result has that the data delay flip-flop 41 assumes a state in which its output 42 the has logic level "1" (see Fig. 6) »The following Clock frequency f2 on the tape causes the output signal of the clock pulse detector 89 assumes the value of a logic "1". This output signal is fed to the clock terminal of the data memory 43, whereby the logic "1" at the output 42 of the data delay flip-flop 41 is transferred to the first register of the data memory 43.

When the clock frequency f2 is not preceded by a signal, the output signals of the data pulse detector 89 and the data delay flip-flop 41 remain at the logic level "O ¹ O"

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The logic "1" at the output of the clock pulse detector is fed to a clock pulse delay circuit; which is formed by components 111, 112 and 113 »The clock pulse delay circuit is via a Buffer transistor 114- powered, which prevents the clock pulse delay circuit from the rise time of the output of the clock pulse detector 89 is increased. The inputs of the components 111 and 112 are resistors 115 and 116 at the level of a logic "0" held so that their output signals have the value of a logical "1" »If the output signal of the Clock pulse detector 89 rises to the level of a logic "1", the input signal of component 111 rises for a period of time which is determined by resistor 115 and capacitor 117. Therefore, that is Output signal of component 111 is a negative pulse. Since the output of component 111 at the end of Pulse rises to a logic "1", the input signal of the component 112 is forced for one by means of the Y / resistor 116 and the capacitor 118, the value of a logical "1" must be indicated for a period of time determined Take the negative output pulse to the NOT element 115 supplied, the output signal of which is a positive Is pulse, the width of which is determined by the resistor 116 and the capacitor 118 and which is determined by a time is delayed, which by the resistor 115 and the Capacitor 117 is determined «,

This pulse sets the output 42 of the data delay flip-flop 41 back via the terminal 119 after the data has been transferred to the data memory 45 and before Data from the next data period is being received.

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The sequence described above is repeated for every eight data and clock periods. At reception of each clock pulse is the one in each register The information contained in the data memory is transferred to the next register in the data memory 45 Therefore, for example, after the eighth clock pulse, the logic level of the first data period is in the eighth register, while the logic level of the last data period is in the first register.

The output signal of the clock pulse detector 89 is also fed to the long pulse detector, which is formed by the components 72, 73 and whose output becomes negative when a clock pulse occurs whose length is greater than a preset period determined by the resistor 120 and the capacitor 121 is determined. When the long eighth pulse is detected, the output of the long pulse detector, which is a logic ¹¹ O ", brings the output of the drive control gate 71 to a logic ^M 1 ⁿ , provided that that set by the start pulse inhibitor 69 Time has expired.

The logical "1" at the set input of the drive control flip-flop 51 causes a change of its state, whereby the drive motor 52 (Fig. 7) is switched off and the drive coil 53 is released immediately · The output signal of the drive control gate 71 is via a

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NIOHT member 122 the holding inputs of holding circuits of the display decoder 45, whereby the Data from registers two to eight of the data memory 43 are transferred to the decoders 45, which convert the BCD code into a form suitable to drive the seven segment display 44, whereby the display of the tape location number is brought up to date. As soon as the tape stops, that takes Output signal of the drive control gate 71 the value a logical "0" and allows the data in the data memory 43 without a simultaneous change in the display be changed.

The positive edge of the output signal of the drive control flip-flop 51 1 di ^{e occurs} when the state of the flip-flop changes, is fed to the clock input of the recording flip-flop 47, whereby the data in the first register of the data memory 43 is transferred to the output 46 of the recording flip-flop 47 will. If this is a logic "0", this signal is applied to a record bias and erase oscillator power source (FIG. 8) via terminal 123 (FIG. 6), thereby preventing the power source from being turned on during the recording operation happens because no control current is supplied to the switching transistor 124 for the power source from the components 125, 126c If a logic "1" is present at the terminal 123, base current is available and it is possible to obtain the required bias voltage and the erase current in the recording mode “The signal with the

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The level of a logic "0" at the output terminal 127 of the recording flip-flop 4-7 (FIG. 6) is the switching logic (Fig. 9) which allows a recording amplifier (Fig. 10) to be connected to the recording head will be connected "

A logical "0" at output 56 of the drive control flip-flop 51 is fed to the trigger input of a timer a (FIG. 11) to control the timer in automatic mode trigger »

Diodes 129, 130, 131, 132 and 133 (Fig. 6) buffer the output signals of the various gates and other components during the start and reset operations, diodes 134, 135 (Fig. 6) and 136 (Fig. 7) prevent that a logic ⁿ 0 "exceeds the base-emitter reverse voltage of the corresponding transistors when separate power supplies are used.

A microswitch 137 (Fig. 6) brings the control circuits to the original initial state when a tape cartridge is ejected from the tape device.

The operating modes of the tape recorder are selected by pressing connected pushbuttons, which are shown in FIG. Usually, when a pushbutton is pressed, it becomes in the depressed position locked while all other switches that were previously locked are released. It is possible,

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partially depressing a key switch to release other keys without locking the depressed key so that after releasing this key a state arises in which no switch is actuated. Conversely, it is possible to press two buttons at the same time, which then both lock at the same time © It is the purpose of this circuit to prevent the device from operating, if any these false states exist "

The selection switches 138, 139 and 140, which are labeled RECORD, MONITOR and AUTO, are connected to the logic level "0" by one terminal, while the other terminal is connected to the input of a NIGHT element 141, 142 and 143, respectively connected is. These inputs are normally held at the state of a logic "1" via resistors 144, 145 or _e. Therefore, the outputs of the NOT gates are at a logic ⁿ 0 "until a selector switch is actuated. Then the output changes to a logic" 1 ¹ O

Each selector switch is assigned a NOR element 147, 148 or, each of which has three inputs. One this input is connected to the assigned switch, while the other inputs are connected to the outputs the NOT elements are connected, which are assigned to the other two switches.

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If only one switch is pressed, the signal supplied by this switch to the associated NOR element is a logic "0". Likewise, the output signals of the NICHO? Elements, which are connected to the other two switches, are also a logic "0". Accordingly, all three input signals of this NOR element are at the level of a logic ¹¹ O ", so that the output signal is a logic" 1 ". The output signal of the NOT element, which is connected to the actuated switch, is a logic" 1 " and consequently prevents the output signals of the other two NOR gates from being a logic "1" _{or the like}

If more than one switch is pressed or if ", none Switch is pressed, at least one input signal is at the level of a logic at all three NOR gates "1" and prevents that the output signal is also a logic "1". Hence, then and only then if a single switch is actuated, one at the output of the NOR gate assigned to this switch logical "1" available.

For the sake of simplicity, these output signals with the level of a logic "1" that occur when the RECORD, MONITOR or AUOJO switch is pressed is, as output signals 150, or 151 or 15I "designated»

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When the current drawn from output 152 is greater the current from a current amplifier 155 becomes that which can be supplied by the NOR gate delivered

Whenever a logical "1" is present at the output of one of the NOR elements, this logical "1" is also present at the junction of diodes 15155 and 156 at. This voltage, which is referred to as output signal 157 ", is available at a terminal 158 and can, if necessary, be fed to the switch of an external microphone (not shown).

When the RECORD switch 138 is selected, this becomes Output signal I50 to the input of an IIICHT element 159 fed, the output of which is connected to one of three inputs of a NOR gate 160- Another input this member is fed via the terminal 161 of the recording flip-flop 47 (Fig, 6), the one returns a logic "0" if the code recorded on the tape allows signals to be recorded. The third Input signal is via a terminal 162 and an inverting transistor 163 from the push-to-talk button of a not shown Microphone derived. Typically, the input of inverting transistor 163 is from a resistor held at the level of a logic "0". However, if the talk button is pressed, a logical "0" appears at the third input of the NOR gate.

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Accordingly, whenever the unit is set to recording mode, the code permits recording and the talk button is pressed, a logical "1" is present at the output of component 160

If the talk key is pressed during recording or monitor operation, a signal from either the RECORD switch 138 or the MONITOR switch a pulse generator is fed, which is constituted by components 165, 166 _o The positive pulse produced by this circuit is via terminal the reset terminal of the drive control blip-flop y \ (Fig. 6) to switch on the tape drive.

If the talk button is pressed in AUTO mode, the signal 157 is fed via the AUTO switch 140 and the NOT element 167 to one of three inputs of a NOR element 168. Another input receives the output signal I5I , which is a logical "0" is. The third input is connected to the logic "0" via a resistor 169, so that all three input signals are at the level of a logic "0" and the output signal of this element is a logic "1". It is referred to below as output signal I70.

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If via terminal 172 to output 50 dos drive control flip-flop 51 (Figo 6) and to the entrance of the limb 168 a connection 171 is established is prevented the logical "1", which is always present when the tape drive is switched on, that the output signal is generated «The connection 171 thus controls the Paging system priority, The priority "microphone in front of position" applies if the connection is missing, and "position in front of microphone" if the connection is missing Connection exists.

The output signals 15Ο and 170 are in an AND gate linked, formed by diodes 173 and 174- to form a control voltage designated as output signal 175.

In AUTO mode, the drive control flip-flop becomes 51 (Fig * 6) from the timer 128 (Fig. 11), which is from the negative edge of output 50 of the drive control flip-flop 51 is triggered via terminal I72, in switched to the on-state.

Control voltages at the output of component 160, output signals 175 and 151 »and the output of the Timing element 128 in combination with the output signal are used to control the signal distribution switch of the Control audio main amplifier.

Both the control voltage I70 and the output signal of the timing element 128 switch an interface relay (FIG. 11) which is used to connect external amplifiers control when tape positions are announced or displayed.

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Display diodes 177, 178 and 179 are made up of transistors 180, 153 and 181 to indicate which mode has been selected.

The amplification of the signals supplied by a microphone, not shown, or the head part 182 (Fig. 10) is done by means of components 183, 184, 185 and 196. These signals are activated by means of the four-way analog switch 187, 188, 189, 190 and 191, 192, 193 as determined by the mode selection logic will. The switch 187 is connected to the Output of the gate 160 (Fig. 9), the switch I9I over the terminal 196 with the output 175 (Fig. 9), and the switch 192 via the terminal 197 with the relay circuit 176 (Fig. 11). Switches 193 and 194 are connected to output I5I (Fig. 9) via terminal 198 tied together.

In playback mode, the signal from head 182 through capacitors 199 and 200 is the input of the first Amplifier section 183 supplied when the relay contacts 201 are closed. The control voltage 175 (Fig. 9) is at the level of a logic "0", which causes transistor 202 to energize relay 203, and also an opening of the analog switches 189 and 19O causes. A capacitor 204 resonates with the playback head at a high audio frequency for a some increase in high frequencies and a greater increase in attenuation above this frequency to reduce noise to effect.

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The gain of "amplifier 185" is provided by resistors 205, 206 while a capacitor 207 the gain factor is reduced above the audio frequency range in order to ensure stability, The bias at the input of amplifier 185 is provided by resistors 208, 209, being a capacitor the resistor 209 decouples to maintain a high input impedance »The positive operating voltage is supplied via V / i resistors 211 and 212.

This is followed by a second amplifier stage 186 “gain factor and the frequency response required for equalization is provided by resistors 215, 214, 215 and a capacitor 216 determined. During playback mode, the output signal 175 (FIG. 9) is a logic "0", so that the Switch 191 is open and resistor 217 is on Circuit has no effect. A capacitor 218 decouples the ground-side end of the resistor 215 · Der Resistor 219 allows capacitor 218 to be rapidly charged to its operating voltage when the unit is switched on, and causes an additional low frequency attenuation increase. The input bias for switch 186 is provided by a voltage divider 220, 221 A capacitor 222 tapped ensures high-frequency stability ο

The supply voltages for amplifier 185 and for the input bias of the amplifier 186 are given additional filtering by an amplifier 184, a resistor 225 and a capacitor 224 "

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When the signal at the output of amplifier 186 exceeds approximately 900 mV, amplifier 185 also forms the resistor 225 a voltage divider to reduce the signal that the input of the amplifier 186 through the coupling capacitors 226 and 227 from the amplifier 183 reached. This achieves an automatic level control, the response time of which depends on the resistance 228 and capacitor 229 and their decay time was dependent on resistor 230 and capacitor 231

An amplifier 232 effects a further amplification in the signal path according to the ratio of the resistors 233 and 234 · «Capacitors 235" and 236 3 are the input or » Output coupling capacitors The amplifier 232 forms also a mixer for mixing in a signal that is sent to terminal 237 from a bell-tone generator (Fig. 12) is supplied, via the capacitor 238 and the resistor 239 into the signal path. In this case it is Gain for the bell tone equal to the ratio of resistor 239 to resistor 234. In In both cases, the capacitor 240 causes an additional high-frequency attenuation increase ο the output signal A volume regulator 241 is fed to the capacitor 236, which is adjustable from the front panel.

If the device is in AUTO mode switched, the switch 192 is switched on by the timer 128 (Fig ₀ 11) or during the Paginierens so that the signal from the

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Slider of the volume control 241 can reach the amplifier 243 via the capacitor 242, in which it is an output current amplifier which is connected to the output terminal 245 via a capacitor 244 is coupled. The output terminal 245 and terminals 246 (Fig. 1H) are provided with an output socket (not shown) tied together.

In other operating modes, the signal paths are modified according to the status of the operating mode selection logic, which control the quad analog switches 187 "through 194.

In recording or paging operations, the playback head 182 (Fig. 10) is from the input of the amplifier separated by opening the contacts 201. In this case the control signal for switches is 189, 190 and 191 a logic "1", so that the input signal for the amplifier 183 from the microphone socket (not shown) is derived via terminal 247. The signal is carried over capacitors 248 and 200. capacitor 248 and resistor 249 form a low-pass filter to improve the recognizability of speech. Of the Switch 191 connects resistor 217 in parallel with resistor 214 and capacitor 216 to the desired To achieve recording characteristics.

The switches 187 and 188 can work together with the reverse transistor 250 form a single pole changeover switch, so that when recording when the output signal of the element 160 (Fig. 9) is a logic "1", the signal from the output

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of amplifier 232 is fed to head 182 via 251 and capacitor 199 »

In MONITOR operation, the output of the amplifier is via 193 and 19Λ in parallel with the microphone socket via the terminal 247 and the capacitor 252 connected so that it is possible to control the recorded signal using the microphone as headphones.

The timer (Fig. 11) provides an in AUTO mode automatic repeated triggering of the drive control circuits at predetermined time intervals between two and twenty minutes can be chosen between predetermined positions. The intervals are below Use of switch 253 selected. To be stable and to ensure accurate timing, the timer 128 includes an oscillator and a twelve-stage binary Divider that supplies time signals after 4095 counts, whereby the need for large time constants is avoided will ο

The supply voltage for the timing element is taken from the emitter of transistor 153 (Fig. 9) derived via terminal 254, so that the timer only works in AUTO mode. The timer includes an internal Zener diode, which is from a resistor 255 is fed and is decoupled by a capacitor 256.

The duration is set by the switch 253, with the help of which the combination of resistors

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set; which is together with the capacitor gives the desired time constant. Resistance 258 allows the frequency to be set for adjustment «The capacitor 259 suppresses noise signals that are a could cause false triggering of the oscillator.

The timing element 128 is triggered by a negative pulse from the drive control flip-flop 51 (FIG. 6) via the terminal 172 , which is a transition from a logic "1" to a logic "0". The diode 260 prevents the trigger signal supplied by the timer from loading the drive control flip-flop 51 when it is a logical "1".

The transistor 261 serves both for level shifting and for signal reversal and provides a signal that the transistor 262 of an interface relay driver and via terminal 263 and the operating mode selector switch 138 (Figo 9) the drive control pulse gate 165 is fed β

The bias and clear oscillator (Fig. 8) consists of transistors 264 and 265. Resistors 266, 267, 268 and 269 provide a bias. Emitter resistors 27Ο and 271 effect a current limit for this stage. The oscillation frequency is determined by the inductance of the erase head 272 and a capacitor 273. The feedback path required to maintain a state of oscillation is via the capacitor and diodes 275, 276.

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To record, head 182 (FIG. 10) is biased via terminal 277 and capacitors 278 fed.

The DC supply voltage is applied to the oscillator via a transistor 124, which seibat through Components 125 <> 126 and 279 is controlled, which are connected together to form an AND gate, so that the The oscillator can only oscillate when the recording mode has been selected, the output signal (Fig. 9) is a logical "1", and if, in addition, the output signal of the recording 3 flip-flop 47 (Fig. 6) there is a logical "1" at terminal 280.

The interface relay 281 (FIG. 11) is provided for triggering additional devices. It is dated by a Timing element 128 delivered logical "1" or, in pagination mode, triggered via diodes 282 and the emitter follower 262. The contact 176 creates a short circuit between the terminals 246, which are connected to an output socket (not shown)

The bell tone generator (Fig. 12) generates a sequence of two bell-like tones that precede a selected point or a pagination announcement, to attract attention.

A logical "1" at terminal 263 or 283 (Fig. 9 and 11) switches the transistor 284 via the terminal 285 (Fig. And 12) and one of the diodes 286 or 287, so that on

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Input of the ITICHT element 288 a logical "Ο" arises. The resulting logic "1" at the output of the NOT gate 288 is applied to the input of the component 289 for a time which depends on the time constant of the capacitor 290 and the resistors 291, 292 depends. During this time it becomes a negative Pulse generated at the output of component 289 (logical "0"). When this impulse becomes the state of logic "1" returns, a second negative pulse is generated at the output of component 293, whose Duration of the time constant of the capacitor 294- and of the resistors 295, 296 depends. These two impulses form the control impulses for the bell tones,

During the first pulse, the circuit arrangement formed by components 297 »298 oscillates on a first frequency. During the second pulse, the circuitry oscillates from the components 299 and 298 is formed on a second frequency «The vibrations are heard at the end of the second Control pulse on or when the collector of Tranaistor 284 returns to the level of a logic "1".

The leading edge of each control pulse also briefly switches transistors 300 and 301 one after the other one so that the capacitor 302 across the resistor can be charged to the supply voltage, whereupon a slow discharge occurs through resistor 304-.

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The voltage on the capacitor 302 causes the oscillations of the component 298 to be fed via the diode gate 305 »3Ο6 to the resistor 307 with an amplitude that decreases from the ratio of the resistors 3Ο8, 307. The oscillation is still a square wave, which is filtered by the transistor 309 with the associated components in order to generate a sine wave that produces a pleasant tone _{or the like}

The resistor 310 is adjustable from the front panel, in order to be able to adjust the volume of the bell tone via the terminal 237 (Figo 10).

The bell tones are usually selected at the beginning of a or to announce a predetermined one Digit triggered If bell tones are only needed for one condition, removing the diode 286 (Fig. 11) the bell tones to announce the above-mentioned places (paging chimes) or by removing the diode the bell tones to indicate predetermined places (spot chimes) suppressed

FIG. 13 shows an alternative circuit arrangement to the circuit arrangement according to FIG. 6. This alternative arrangement enables the user to display the duration of a recording in seconds.

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Instead of the output signals of the data memory 4-3 (Fig. 6) being fed directly to the display decoders 4-5, they are fed to the inputs of data registers 311, 312, 313, 314-, 315, 3I6 and 31? fed. These circuits store and present at their outputs the information that is present at their inputs during the positive thresholds of the input clock signal. When the output signal of the Antriebssteuertors 71 (Fig .6) is the logical "1", so upon receipt of a 'stop signal, the data is transmitted from the data memory to the data register, where they are held until receipt of the next stop pulse _e The outputs of the data register are applied to a set of the inputs of presentation selectors 318 and 319.

A main frequency signal derived from the electrical grid is fed to the input of a divider counter 320 which provides an output signal per second. This signal is fed to a second display counter 321, which supplies a BCD-coded output signal, which represents the past count »The output signals this counter is applied to the second set of inputs to display selectors 318 and 319.

When the unit is first turned on, a digit / time selection flip-flop 322 is set to have its Q and Q output signals adjust the display selectors so that that their output signals correspond to the first set of

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Input signals corresponding ;, indicating the code that is contained in the data registers 311 "to 317 _o At the same time, an erase flip-flop is set 323, so that its output signal prepares the presentation inputs the display decoder 324- and 325th Therefore the display will show the tape location code.

If the unit is set to recording mode, recording is permitted if a time switch 326 is pressed, the digit / time and clear flip-flops 322 and 323 change their state. As a consequence, that the output of the seconds counter 321 from the Display selectors 318, 319 and display decoders 324, 325 is supplied «. However, this one is in the erased state so that there is no display by the display device »

Once the tape drive is operating, a reset signal is fed to divider 320 and it begins; the Counter to work »After a time determined by a delay counter 326, a signal fed to the clear flip-flop 323, which allows the display to light up, the display to light up can be used as an indicator that a recording can begin and the expired one Recording time shown at the end of the recording, because either the drive control gate 71 (Fig. 6) has stopped - pulse is generated and fed to terminal 327 or

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When the user releases the talk button, an end of recording detector 328 generates an output pulse which causes digit / time dial flip-flop 322 to change state and cause the display to show the last identification code generated by the tape is. Terminals 329 * 330 and 331 receive the output signals from gates 160 (Fig. 9), 149 and 148. Terminals 332, 333 and 334- receive a trip signal, a solenoid delay signal from the delay circuit of Fig. 7, and the line voltage. If this circuit arrangement is provided, the locking function of the display decoding memory is not required.

Figure 14 shows an incomplete tape reset circuit. This circuit allows the user to record part of the tape and, during playback, to cause the device to continue running after the last recorded message (position) has been played until the first message is available for playback.

The output of the data memory 43 (Fig. 6), the data registers 311 supplied to 317 in the same manner as in the circuit arrangement shown in FIG. 13 · The outputs of the data registers are terminals 335 supplied to a detector 336 for the last digit by using the Code for the last recorded message are compared, which is fed to the terminals 337 and which is set by the user by means of a switch (not shown) "last digit". If the

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The code read from the tape is less than or equal to the code set with the "last digit" switches has been, the output of the detector for the last digit is a logic "0" and it will this signal is fed to a NICIIT gate 338. the Logical "1" from the output of the NOT element 338 is fed to the stop pulse blocking element 339. The logical one "1" at the input of member 339 has the effect that its output signal, which is fed to a member 340, a logical "0" is.t «,

A positive stop pulse from drive control gate 71 (Figo 6) is negated by the stop pulse delay elements 34-1 and 34-2 and delayed the delay is long enough to allow adjustment of the output of detector 336 for the last digit. When the negative, delayed stop pulse is received, the two inputs of the element 34-0 are one logic "0", so that its output assumes the value of a logic "1", whereby the state of the drive control flip-flop 51 (Fig »6) changed and the drive switched off will ο

After the last digit selected, the code for each subsequent identification will exceed the code that has been set by the switch for the last digit, and 63 becomes the output of the detector 336 rise to a logical "1" for the last digit. The result of this is that the NICHiD member 338 supplied input signal for the link

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a logical "0" is _o If the other inputs are also a logical "0", the output signal will be a logical "i" »This forces the output signal of the element 34-0 to a logical" 0 ", where ~ by preventing stop impulses from reaching the drive control, the belt will therefore continue its run until the first position is reached at which the code delivered by the belt is less than the code entered using the switches for the last position, and it the stop pulse will stop the belt again.

So that centrally prerecorded messages are not missed can be set to a code that is smaller by setting the switches for the last digit iat al3 the code of these messages, is used by the recording flip-flop 4-7 (Figo 6) whenever a Code for a centrally recorded message is determined, a logic "1" is fed to member 339, which the stop pulse blocking members 339, 340 prevent stopping impulses from being blocked.

Likewise, a logical "1" is always assigned to member 339 when the unit is in recording and monitoring mode »Therefore the tape can only be used with Playback mode continues.

809849/0741

If the tape continues to run, a logical "1" is sent from The output of the element 359 is fed to the switching logic, to prevent the reproduction of audio signals and an operation of the interface relay.

Another addition, not shown, can be provided with a logical "1" ala output signal of the detector 336 triggers a fast forward for the last digit. In this case is an additional one Signal required on tape preceding the information recorded in the first location and that causes the unit to run at full speed switched back

The circuit arrangement described can be supplemented by further devices, for example by Adding a switching device gives the possibility of a certain section of a recording select »So by comparing the coded output signal of the tape with preset Information that is, for example, in a digital memory, an automatic Search for a specific tape section can be made possible by the preset information is identified, followed by an automatic switch to playback. “It goes without saying playback itself is also triggered automatically

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or a wait state for further commands can be set «If several such options are provided are, a P ο Ige of predetermined sections can be played automatically, either with minimal delay or by using the internal Timer with predetermined intervals »

Conversely, it can be left out for certain requirements certain sections may be more appropriate »

In a particular application of this system, the coding at the time a program signal is generated is β with. coupled to a random number generator so that the playback of selected sections takes place in random order »This measure can do this A very large number of program combinations can be used with a relatively limited number of sections to create·

Although the system described above generally suggests the use of numerical representation, it is easy to expand the system to include letters, for example in Music Systems Other uses for the system include audio-visual equipment, in which the controller or coded information derived from a tape is used for this purpose can control a number of projectors, possibly with faders.

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Fig. 15 shows a device which makes it possible certain passages or spots during playback off «.

Ea may be that the user of the facility who recorded a series of spots on a tape, wishes to omit one of these positions or advertisements, for example if this is an advertising spot and the displayed product is no longer available.

In the case of the basic unit, it would be necessary to transfer the tape and replace the 3 unwanted spots to insert a new one «The circuit arrangement according to 3? xg. 15 ha * the purpose of allowing the user to omit selected ones Allowing spots provided the spot was recorded locally »This condition was added because passages recorded by the editor of the tape program and cannot be deleted by the user and which the publisher may have paid for, either may be left out.

Although the circuit arrangement can be designed so that any number of spots can be skipped is, an arrangement is shown here in which because of the limited Ratzes available for selector switches the ability to skip is limited to digits 00 to 09.

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Each time the control circuit detects a stop pulse (with the clock frequency), the Q output of the drive control flip-flop changes from the logic "1" to logic "0" _s, this negative transition through the terminal 34-3 and the capacitor 344 to the clock inputs of the data registers 3 ^ -5 and 34-6. When this pulse is received, the data are copied from the data memory 3 ^ 7 into the data register. Signals from the data memory 43 (FIG. 6) are fed to the inputs labeled 34-8.

The output signals of registers 345 and 34-6 correspond to as soon as it registers 3 ^ 5 and the three Data lines of the register 34-6 concerns which the The tens digit of the digit code are the data that were transferred to the register as the tape drive stopped Output equal to the complement of that in memory transferred data »

The output of the register 34-5 is a BCD decimal decoder 3 ^ 9 supplied «One for each digit the outputs "0" through "9" of decoder 349 are on the logic level "1", depending on the J unit number of the Position code «, These output lines are via Isolating diodes 350 which can be actuated by the user Spot outlet switches fed «Any switch that the user has turned to this switch

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omitting the assigned spot connects the corresponding output line to the input of a NOT member 351 »which in turn is one of three Inputs of a NOR gate 352 feeds.

Accordingly, if the units digit of the spot code, which is located in the data register, corresponds to a switch which has been operated by the user, then the input signal for the element 34-2 is a logical "O ¹ O In all other cases it is a logical" T ¹ «A second input signal of the three-input NOR element 352 is fed from the data lines of the register 346, which correspond to the tens digit of the spot code, via a NOR element formed by diodes 353. This input signal is a logic "0" if the spot number is 09 or less. In contrast, this signal is a logical "1" if the number of spots is ΊΟ or more.

The third input to gate 352 is a logical "0" if local recording is allowed and logical "1" if local recording Is blocked.

The output signal of element 352 is a logical "T ^1. If the number of spots is between 00 and 09, local recording is permitted and the switch assigned to the number of spots has been actuated. This output signal is fed to an input of an element 35 * 1- and causes the output of this element

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is a logical "0", regardless of the state of its other input. Because this output signal via a diode 355 and the terminal 356 for control of the output of the device and via diode 357 and Terminal 358 for controlling the bell tone generator (Fig. 12) is used, no output signal can be obtained from the device in this state.

The output of gate 352 is also fed to a NOR gate 359 via a NOT gate 360. In the described state, namely with a stationary tape and a skipped spot, both inputs of the element 359 are at a logic "0". As a result, its output signal is a logic "1". This output signal is fed via the terminal 361 to the timing element 128 (FIG. 11) which triggers the tape drive after a short time interval determined by the resistor 362, so that the tape runs to the next spot without reproducing the output signal. The logic "0" from the NOT element 360 is fed to the input of the element 168 (FIG. 9) via a diode 363 and a terminal 364- so that pagination connections can take place even though the motor is running. A resistor 365, which replaces the connection shown in Figure 9 by a _o dotted line limits the the NOT gate 360 supplied current.

If the digit code is not selected as the code to skip or is at least 10, or if the coding then blocks a local recording

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the output signal of the element 352 a logic "0" and the output signal of the gate 354- depends on the State of its other input signal. Since this input signal is derived from NOT gate 366, is the output signal of the link 354- identical to the Input signal to NOT gate 366 · This input signal is the control voltage that is supplied by the level shifter 261 of the timing element (FIG. 11) is supplied and which is now supplied via the terminal 367, the NOT element 366, the element and diode 355, which replaces top diode 282 in FIG. 1, the interface relay driver 262, and the analog switch 192 (Fig. 10) is supplied. This means that under this condition the device works normally, so that the spot begins at the end of the timer interval and the output signal is fed to the output socket will. The control voltage is also applied to transistor 284 (Fig. 12) via NOT gate 366, gate 354 and the diode 357 replacing the diode 287 in Fig. 11, supplied to the bell-tone generator Trigger the beginning of each played spot.

In Fig. 16 there is shown a tape rewind circuit. This circuit allows the user to occupy only part of the tape with recordings and during playback to cause the tape to continue running after the last recorded message (spot) until the first message is available for playback again

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The data from the data store is transferred to data registers 34-5 and 34-6 as is the case for the spot exhaust circuit 15 has been described «The output signals of registers 34-5» 34-6, which correspond to the spot number code correspond, detectors 368, 369 are supplied for the last spot in which the code with the BCD code for the last recorded message is compared, which the user received with the aid of Last Spot switches 370 has set.

If the code read from the tape is less than or equal to the code that has been set by means of the last spot switch, the output signal of the detector is a logic "0" which is fed to the NOT gate 366 (FIG. 15) _{or the like} The logic "0" at the input of this NOT element 3 causes the device to function normally, as has been described for the spot outlet circuit

When the code read from the tape is greater than the code set by means of the last spot switch, the output signal of the last spot detector is a logical "1". This signal is fed to the input of gate 352 via HICIIT gate 366 and causes the tape runs across all spots where a 'local Recording is not disabled, as has been described for the spot exhaust circuit. As with the Spot-skip switching cannot be skipped by centrally recorded messages here either the last spot switch is set to a code that is smaller than the code of these messages.

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Claims (1)

Claims Tape system with facilities for recording Information signals on the tape and reproducing the recorded information signals by means for recording digital signals, the selected sections of the tape and information signals contained therein identify, on the tape, a device for Playback of the recorded digital signals and means for generating system control signals as a puncture of the reproduced digital signals « Tape system according to claim 1, characterized in that the recording devices include an astable clock generator, a parallel-serial register to which clock pulses are fed from the clock generator, switches for feeding a binary digital code to the parallel inputs of the register, which digital code depends on the clock pulses appear at the serial output of the register, a data oscillator controlled by the serial output signal of the register, which oscillates at a first or a second frequency depending on the state of the output signal of the register, and a clock oscillator which oscillates at a third frequency, and that the Output signals of the data and the clock oscillator are combined into a common output signal, which consists of a sequence of pulses of the first or second frequency, which are separated by pulses of the third frequency. 101141/0741 ORIGINAL INSPECTED 3. Tape system according to claim 2, characterized in that the second frequency is zero. 4-O band system according to claim 2 or 3i, characterized in that that a counter that counts the clock pulses is coupled to the astable clock generator sets the register to parallel operation after the binary digital code has been clocked out of the hegister has been. 5 · Bandsyatem according to claim 4, characterized in that that a timing element is coupled to the counter which controls the oscillator in its oscillating state holds after the binary digital code has been blanked from the hegister to the end of the digital code generate indicative signal. 6. Belt system according to claim 5 »characterized in that that the astable clock is controlled by a bistable flip-flop, which in turn is controlled by a Trigger switch is controlled to turn on the clock and controlled by the timer to turn off the clock when the dao end dee Signal indicating digital codes is generated. 7 · Band system according to one of the preceding claims, characterized in that the digital signals in Form of pulses of different frequencies are recorded and the device for generating System control events includes frequency selective switches, each of which responds to one of the frequencies of the recorded impulses. • 01149/07 * 1 8. Hand system according to claim 7, characterized in that that there are devices which respond to the frequency-selective switches prevent missing signals if the duration of the absence is less than a predetermined one Period of time. 9ο belt system according to claim 7 or 8, characterized in that that the digital signals in the form of data pulses of one frequency and clock pulses of one other frequency aiifgezeich.net and two frequency selective Switches are present, of which the switch responding to the file impulses is on Delay flip-flop controls that feeds the data pulses to a data memory, during which on the Clock signals responsive switch supplies clock signals to the data memory » 10. Belt system according to one of claims 7 "to 9, characterized in that there is a tape drive control circuit which, upon receipt of a digital signal stops the tape " ο Belt system according to claim 10, characterized in that that the digital signals are terminated by a termination pulse which is longer than the previous one Pulses of the digital signals, and that there is a detector which recognizes the long pulse and which the Tape drive control circuit activated when the termination pulse is received «. 809849/0741 12o belt system according to one of the preceding claims, characterized in that there is a group of selector switches which when actuated are, output signals with a certain logical Deliver levels and the output signals are each fed to a NOT element and a NOR element, and that the NOR gates are connected to all NIGHO? gates, with the exception of the NOT gate of the associated switch, so that if only one switch is operated, at the output of the associated NOR gate an output signal appears, but on no NOR element has an output signal if more than one switch is operated. 13 «Belt system according to one of the preceding claims, characterized in that it comprises a timer, which activates the tape drive control circuit at predetermined time intervals «, 14. Tape system according to one of the preceding claims, characterized in that it comprises a bell-tone generator which generates a sequence of tones when a tape drive circuit is switched off . 15. Belt system according to claim 9 or one of claim dependent claim, characterized in that the output signals of the data memory corresponding Data registers are supplied that a device responds to a shutdown of the tape drive and then causes the transfer of the data from the data memory in the data register and that a device for Display of the content of the data register is available. 809849/0741 16 «, belt system according to one of the preceding claims, characterized in that there are means for selecting a digital code, means for Detection of a code recorded on a driven tape, a device for detection a correspondence between the selected and recorded codes and a device which causes the information corresponding to the code recorded on the tape to be played back that matches the selected code. 17 · Tape system according to claim 16, characterized in that the device for selecting a digital code enables the selection of a sequence of digital codes and means for playing the sequence of Information associated with digital codes is provided. 18. Belt system according to one of the preceding claims, characterized in that the information signals and the digital signals are recorded on different tracks on the tape. 19 · Tape system according to one of Claims 1 to 17 »characterized in that the information signals and the digital signals are recorded on the same track of the tape in different frequency bands ainde 8098A9 / 07A1 -Λ- 20 _β method for controlling a belt system in response to a band that is played by means of a related belt system playback machine, characterized in that digital signals are recorded on the tape, identifying the selected portions of the Bandea and information signals contained therein, the recorded digital signals played back and generated depending on the played digital signals üsystemsteuersignale. 809849/0741