DE2548158C2 - Arrangement for pulse regeneration - Google Patents

Description

50

The invention relates to an arrangement for regenerating RZ (return-to-zero) signal sequences.

Digital information transmitted over lines is received deformed. It is therefore necessary to regenerate the useful signal in order to ensure error-free further processing.

A circuit consisting of a toggle switch ('D flip-flop), as in »The Integrated Circuits Catalog for Design Engineers «published by Texas Instruments, and a downstream AND circuit, solves the mentioned task, but has too long a takeover time and is therefore not for extremely high Frequencies suitable, in addition, their power consumption is relatively large.

From DE-OS 22 22 577 a Schaltungsanord- *>^r> voltage known that also solves the above object, but takes a completely different approach. A bistable multivibrator is controlled in addition to the two stable states for a time fraction determined by the clock signal, preferably for half a bit period, with the aid of the clock signal in such a way that the same potential occurs at both outputs of the multivibrator, so that At the desired sampling time, the flip-flop first briefly assumes an unstable state due to the potential jump in the clock signal and only then, depending on whether the PCM signal constantly present at the input of the flip-flop circuit has exceeded or fallen below the decision threshold, reaches one or the other stable state that the flip-flop maintains for the rest of the bit period even if the PCM signal changes before the flip-flop has completely reached the respective stable state, and that the PCM signal at the input of the flip-flop is limited to such a value that it is unable to handle the K toggle switching from one stable state to the other.

The clock signal controls an auxiliary transistor, which short-circuits the flip-flop in cycles, so that the The flip-flop circuit is de-energized and assumes the neutral state

From US-PS 30 69 500 a circuit arrangement is known, which also the above object can solve. The disadvantage of this circuit is that the transistors used are not protected against saturation is, so that this arrangement can not be used for higher clock frequencies.

From US-PS 32 70 288 a circuit arrangement solving the stated problem is also known, which is also not suitable for high clock frequencies. It also has a high power consumption required, because of the series connection of up to 3 transistor stages and the associated higher Operating voltage. The data cannot be transferred to the flip-flop in an edge-controlled manner, rather, needle pulses must be generated for this purpose.

The task leading to the invention was to provide a circuit that operates at discrete times should recognize whether an impulse is present or not. This recognition is said to be in a very short period of time (Takeover time) be possible. If the impulse is recognized, then it should be applied to the circuit for the duration of the applied clock pulse can be passed on to the output. The circuit is designed to range from low to very high work at high clock frequencies, can be implemented with little effort and have a low power consumption own.

The object is achieved as described in claim 1. Appropriate exemplary embodiments are described in the subclaims. The mode of operation is explained below with the aid of an exemplary embodiment according to FIG. 1 and FIG. 2 and a pulse diagram according to FIG. The pulse diagram, FIG. 3, shows, except for the potentials at the information input D, at the clock input T and at the signal output Q, the respective conductive or blocked states of the transistors, but not their output levels. This representation is useful because the output of a single Tränsistörschälters can have a low level despite the blocked state if another transistor switch, the output of which is directly connected to the output of the blocked transistor switch, is in the conductive state and thus the low level at the output of the locked transistor switch.

The level at the signal output Q is determined by the switching states of the transistor switches 72, 74. The interaction of all transistor switches results in the following function of the entire arrangement. A pulse with the same duration as the clock pulse occurs at the signal output Q only if, during the takeover time - this only appears as time interval 8 in the pulse diagram - a level exceeding the threshold of the transistor switch 71 is on the information input channel D. In all other cases, the signal output Q has a low level.

The voltage jump between high and low level at the signal output Q is when using transistor switches according to FIG. 2 in the arrangement according to FIG. 1 is equal to a diode threshold voltage. This means that the circuit can be operated at very low currents and therefore has a low power consumption

The delayed switching off of the transistor switch 73 can be achieved, for example, in that the transistor is controlled into the saturation range by saturation protection diodes with different voltage levels. The delay time achieved in this way is equal to the takeover time in which the circuit can recognize a signal and pass it on to signal output Q.

The following describes which switching states the individual transistor switches in the respective Time intervals according to FIG. Take 3.

In time interval 1, the information input D is at a low level, and the clock T is at a high level. Then the transistor of 7 * 1 is blocked, the transistors of T2, T3. 74 are conductive, ie T2 and 74 force the signal output (fine low level.

In time interval 2, the information input D is at a high level, and the clock T is still at a high level. Then the transistors of Ti, T2, T3, T4 are conductive, ie 72 and 74 force a low level at the signal output Q.

In time interval 3 there is Dein at the information input high level, clock 7 is now low. Then the transistors of 7 * 1, 73 are conductive, the Transistors of 72, 74 blocked, d. H. 72 and 74 allow a high level at the signal output ζ).

In time interval 4, your information input is low, and clock 7 is still at a low level. Then the transistors are in front. 71, 73 conductive, the transistors of 72, 74 blocked, ie 72 and 74 force a high level at the signal output Q.

In time interval 5 Your low level is applied to the information input, clock 7 is now at a high level. Then the transistor of 71 is blocked, the transistors of 72, 73, 74 are conductive, ie 72 and 74 force a low level at the signal output Q.

The situation in time interval 6 is the same as in time interval 2.

The situation in time interval 7 is the same as in time interval 1.

In time interval 8 there is Dein at the information input low level, clock 7 is now low. Then the transistors of 7 * 1, 74 are blocked, the transistors of 72, 73 are conductive, i. H. 72 forces a low level at the signal output ζ). There the transistor of 73 is switched on via the clock input with diodes of different threshold voltages was, and the transistor of 73 is therefore in saturation, the switch-off only has a delayed effect the end.

In time interval 9, your information input is low, and clock 7 is still at a low level. Then the transistors of 71, 73 are blocked, the transistors of 72, 74 are conductive, ie 72 and 74 force a low level at the signal output Q. The transistor 73 has now blocked with a delay and brings the transistor of 74 into the conductive state.

In time interval 10, information input D is at a high level, clock 7 is still at a low level. This actually creates the prerequisite that a high level could occur at the signal output Q , but the transistor of 73 remains blocked and therefore keeps the transistor of 74 conductive, so that a low level is forced at the signal output ζ) of 74. The transistors of 71, 74 are conductive, the transistors of 72, 73 are blocked.

In the time interval 11 there is a low level at the information input D, the clock 7 is still at a low level. Then the transistors of 71, 73 are blocked, the transistors of 72, 74 are conductive and force a low level at the signal output Q.

In time interval 12 there is a high level at information input D, clock 7 is still at a low level Level. Then the transistors of 7 1, 74 are conductive, the transistors of 72, 73 are blocked, i. H. 74 forces at the signal output (fine low level.

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. Arrangement for regenerating a deformed by the transmission line RZ (return-tozero) signal sequence using transistor switches and a clock sequence synchronized to the received signals, characterized in that all transistor switches have two equivalent inputs, the first input having a first transistor switch (Tl) serving as a threshold switch forms the input (D) of the entire arrangement, that the first transistor switch (Ti) can be controlled via the second input from the signal output (Q) of the entire arrangement, that a second from the 'S output the first transistor switch (T 1) via a first input and from the clock (T) via a second input controllable transistor switch (T2) can short-circuit the signal output (Q) of the entire arrangement that a third from the clock (T) via a first Input and from the signal output (Oi but a second input controllable delayed disconnecting transistor switch (T3) a fourth Transistor switch (T4) can control via a first input that the fourth transistor switch, which can also be controlled by the clock (T) via a second input, can short-circuit the signal output (Q). 2. Arrangement according to claim 1, characterized in that the transistor switch each consists of a transistor (Tr), a resistor (R) and four diodes (D i, D2, D3, DA) are constructed, that the emitter with the reference potential, the The collector is connected to the output (A) , that the resistor (R) is connected between the base and the emitter, that the first diode (Di) tables the first input and the base, the second diode (D 2) between the first input and the output (A) is connected so that the third diode (D 3) is connected between the second input and the base, the fourth diode (D 4) between the second input and the output ^. 3. Arrangement according to claim 2, characterized in that in the switch-off delayed transistor switch (T3) the first diode (D \) has a smaller «threshold voltage than the second diode (D 2).