DE2525287A1 - ASSOCIATIVE MEMORY - Google Patents

Description

The invention relates to an associative memory according to the preamble of claim 1.

Integrated modules for building associative memories are already known. (Compare data sheet TT / uL Memory 93402 of Fairchild Semiconductor from May 1971). The known module has a comparatively small storage capacity of 16 bits. The attempt to increase the capacity has in the past mainly been the number of within a building block feasible linkage or storage links a limit set »Due to the increasing mastery of integration technology, the problem has shifted, so that the limits more and more are given by the maximum number of external connections. As is known, are essential in associative memory more connections than with linearly addressed memory

d " ⁵ e required because additional lines for / input of the mask and for the output of the hit signals have to be provided.

It is true that the number of external connections of the module can be reduced in that the data lines are used for both input and output of data are used that are necessary for the selection of the memory locations Address decoders are integrated within the module and that the mask is also supplied via the data lines will. The last-mentioned measure requires the provision of a mask register within the module, which however the circuit and time expenditure increased.

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Proceeding from the knowledge that the associative processing of the stored data in the vast majority of cases only over parts of the entire content of memories medium or high capacity, the invention is based on the object of specifying measures that allow to increase the storage capacity that can be realized within an integrated module without reducing the number of external Connections exceeds an acceptable level.

According to the invention, this object is achieved by the in the characterizing Part of claim 1 specified measures solved.

In addition to a particularly favorable ratio of the capacity that can be realized in a single memory module to the number The hierarchically organized associative memory offers great advantages for the required external connections Processing of independent tables or lists, especially when sorting unordered stored terms. Every The address of the underground memory forms an independently associable area (see patent application P 25 05 477.7).

The invention is described in more detail below with reference to an exemplary embodiment shown in the drawing. 1 shows a schematic illustration to explain the basic principle,
2 shows the internal structure of a memory module.

Fig. 1 shows the associative memory according to the invention as a block from which a thin slice S1 is separated and a has moved up a little. This slice S1 is intended to represent the associative surface. The rest of the larger part S2 of the block denotes the linearly addressable, non-associative underground memory.

The entire data exchange between the associative memory and the VPA 75 E 2009

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its environment occurs solely through its surface. Direct access to the underground storage is not possible.

To facilitate understanding it should first be assumed be that the surface is formed by a fully associative memory, for example from 64 word lines consists of 8 bytes each. The individual memory cells are assigned comparators in a known manner, which are line-by-line cooperate and if the content of the line matches the specified search term, a hit signal hand over. A changeable mask allows the association area to cover parts of the word lines, possibly except for one Bit to be constricted. The lines of the surface memory can be selected separately for the input and output of data will. In the "Associate" operating mode, all Lines captured at the same time.

Each line of the surface memory is assigned 2 ⁿ , for example 32, lines in the underground memory which can be addressed by an "underground address". The 2 ⁿ lines form an underground storage area. Corresponding lines of all underground memory areas are detected by the same underground addresses and form an underground memory level.

The very broad interface between the subsurface and the surface created in this way can be used in one Storage cycle, the entire content of the surface storage is transferred in parallel to the addressed underground storage level or vice versa can be taken over from there.

When dividing the total memory into individual integrated modules with the highest possible degree of integration, it is advisable to to reduce the number of people leading to the outside world

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Connections the interface between the surface and to lay the subsurface in the interior of the building block.

Fig. 2 shows a schematic representation of an advantageous Embodiment with a capacity of 1024 bits (1 K-bit), the existing capacity according to the previously mentioned assumption of the surface memory is not included. The block contains 64 bit elements AS, which are arranged in four lines of 16 Bit elements are arranged. The lines within the Blocks generally only comprise partial words of the total memory, can be selected individually for read or write cycles. For this purpose, a binary-coded surface address AA is fed to the module via the external connections 26 and 27, which by the decoder DA is converted into the form 1 of FIG. An inhibit signal IN (connection 25) enables the selection of a certain module or a group of 4 word lines of the surface of the total memory,

Under the previously made assumption that the surface represents an independent storage: aähiges arrangement, everything exists their bit elements from a memory element for storing a data bit and a comparator for associative comparison of the stored data bit with the relevant bit of the search term. The outputs of the individual comparators of a Lines are linked according to an AND function. The connections 21 to 24 serve to output the hit signals TRa. About the Terminals 17 to 20 are preceded by the hit signals TRi Blocks forwarded. If the logic circuit provided allows a wired AND operation, then you can Corresponding hit output lines are simply connected to one another and the hit input lines are dispensable. These lines can also be dispensed with if the hit signals from all of them ultimately lead to one common word line combined lines of the individual modules linked by an additional outer AND element will.

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For every four bit elements with the same value in the four lines of the surface in one block there is a connection 1 to 16 for the input or output of data (bit lines) to disposal. Furthermore, connections 34 to 49 are provided for the input of the changeable mask. The last The connections mentioned can be saved if there is a 16-digit register in the block for intermediate storage the changeable mask is integrated. In addition to the increased circuit complexity, the for an association process required a total of time, because in a first step the mask over the bit lines must be saved, at least when their state has changed compared to the previous association process.

The binary-coded instructions for determining the reading, writing or associating working modes are provided via the connections 32 and 33 supplied to the decoder DB and decrypted by it. The control signals act both on the surface ais also on the underground storage.

Analogous to the assignment of a memory area with 2 lines to each line of the surface memory in the overall arrangement there are also 2 lines of the corresponding length of an underground sub-memory within a module of each line of the surface memory Assigned to US. The exemplary embodiment shown in FIG. 2 is based on 16 memory lines (η = 4). The one for addressing the underground storage US underground addresses UA accordingly consist of 4 bits that are fed in at connections 28 to 31. Basically, only one address decoder per module is necessary for decoding the underground addresses UA. To the However, it can be useful to save internal control lines in each memory area or even just a part to assign its own address decoder to one of these. In Fig. 2 there is no decoder for the underground address UA shown.

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The associative memory according to the invention can with bipolar or with unipolar (MOS) elements, in particular also as so-called CCD memories are produced. In all of these cases, the storage elements are non-volatile, i.e. H. static or quasi-static read signals. Since the content of an addressed storage level in the underground storage US is already available, the storage cells in the surface can be omitted. The surface then worries about that only the connection to the outside world.

It should also be mentioned that it is advisable to use a Provide memory cell in each word line of the underground memory for the entry of an occupied bit. The busy bit is retained as long as the content of the relevant word line is still up-to-date. Free storage spaces are determined by means of an associative search process, which is carried out by correspondingly setting the mask on the contents of the relevant memory cells is limited in the addressed memory level.

2 figures

5 claims

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Claims (5)

-7 claims (i_j) Associative memory built up from integrated building blocks, hierarchically organized, with word-by-word (line-by-line) access and with an association area within the words to be determined by a selectable mask, characterized in that each building block is organized hierarchically in itself, in such a way that one consists of several lines existing associative surface is provided with associative comparators interacting line by line, which can receive data from the outside or output to the outside or with a linearly addressable underground (partial) memory with 2 ⁿ lines that can be selected independently of the lines of the surface and that each module contains a decoder for selecting the lines of the surface (partial) memory and the underground (partial) memory, 2. Associative memory according to claim 1, characterized in that that the surface has its own storage cells. 3. Associative memory according to claim 1 or 2, characterized in that means are provided in each module which, when the command "associate ¹¹ " is present, activate all lines of the surface or of the surface (partial) memory at the same time. 4. Associative memory according to claim 3 »characterized in that that a mask register that can be loaded via the data lines is integrated in each module. 5. Associative memory according to one of the preceding claims, characterized in that upon input VPA 75 E 2009 609850/0567 of a new value an occupied bit in a specific memory cell the relevant word line is set and that free memory locations are determined by an association process, in which only the specific memory cells of the addressed storage levels participate through appropriate masking. VPA 75 E 2009 6098S0 / 0567