DE2441099A1 - SYSTEM FOR TRANSMISSION AND TRANSMISSION OF DIGITAL MESSAGES VIA A STEP-BY-STEP NETWORK - Google Patents

Description

Dipl.-Pays. Leo ihul

Stuttgart

J.H. Dejean - 23

INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK

System for the switching and transmission of digital messages over a tiered switching network.

The invention relates to a system for switching and transmission of digital messages over a tiered switching network connected by digital channels, in which the messages are combined into message blocks, which are preceded by a message header and each message block with Passage through a switching stage from an input to an output channel is forwarded.

There are currently two different types of intermediation in telegraphy. and transmission systems used. The one in The system commonly used in the USA uses transit switches in which each message is in the form of message blocks is received on punched tape (storage switching) In every through switching the header of a message block, which only contains the address of the recipient terminal, read by the operator, the next Determines the exchange to which the punched tape with the

August 21, 1974 Sa / I4r

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■ alignment block is transmitted from a punched tape reader transmitter * This process is repeated until the Message block has reached the recipient's switchboard.

In the case of telex systems of the second type, an example of this is the telex system, is through automatic switching between the participants or at least between allows a time-limited exchange of messages for sending and receiving switching.

When telephoning, the participants or operators are in direct contact when they exchange their messages. Although there are similarities in telex and telephoning because of the direct contact, so far it is has not yet succeeded in merging the two systems into one.

The invention has for its object to provide a system of the above type which operates automatically. This is achieved according to the invention in that the message header Contains as many selection characters as there are switching levels must be traversed, with each individual selection character becoming an individual to be traversed Transmission level belongs and contains an address, which corresponds to the output channel to be passed through, that each switching stage contains a selection circuit, which recognizes the selection character belonging to its own switching stage that means are provided which the message block according to the address in the recognized selection character to the output channel.

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This results in the advantage that the switching takes place so quickly that digitized voice messages are also possible can be transmitted in blocks.

Further developments of the invention can be found in the subclaims .

The invention will now be explained in more detail with reference to the exemplary embodiment shown in the accompanying drawings. Show it:

Fig.l is a simple block diagram for illustration the general principle of the system according to the invention,

2 shows a digital message block, which is transmitted via the in Fig.l network shown is transmitted,

FIG. 3 shows a digital message block shown in relation to FIG during transmission through the network shown in Fig. 1,

4 shows the block diagram of a switching stage according to the invention of the system shown in Fig.l,

5 shows the block diagram of a paging system, which the message transmission controls between successive units of the chain shown in Fig. 4,

Fig.6 shows a multistable circle, which in random selection circles is provided in various components of a switching stage shown in Figure 4,

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FIG. 7 shows a preselection unit, which is shown in FIG Preselection groups are used,

Fig. 8 the input circuit of an input memory of the in Fig. 4 stage shown,

FIG. 9 an input or buffer memory of the FIG. 4 switching stage shown,

Fig.10 shows a part of the functional circuits of a in Fig.4 the selection circle shown,

Fig.11 the other part of the functional circuits of the in Fig.10 circle shown, with Fig. 11 to the right of Fig. 10,

Fig.12 shows an output memory, the one shown in Fig.4 Mediation level and

FIG. 13 shows the output memory of the switching stage shown in FIG .

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Fig.l shows a very simplified block diagram according to the invention of a switching and transmission network The telephones 2 and 3 are via the network 1 with the corresponding TeIefönendgeräte 4 and 5 connected. The telephone sets 6 and 7 are connected to the network 1 via the teleprinter terminals 8 and 9, respectively.

Network 1 contains a large number of switching stages, of which only three, namely Cl, C2 and C3 represent-

are provided to simplify the description. It is assumed that telephones 2 and 3 are in duplex connection are connected to one another by the three stages Cl, C2 and C3 shown. The output line from 2 to 3 or from the end device 4 to terminal 5 goes through line 10, stage Cl, line 11, stage C2, line 12, stage C3 and line 14. The return line from 5 to 4 goes via line 15, stage C3, line 16, stage C2, line 17, stage Cl and line 18.

It should be noted that the connection between telephone sets 2 and 3, but at least between 4 and 5, is a four-wire connection and you will see later that this is only advantageous associated with no disadvantages, especially from an economic point of view. Assume that the teleprinters 6 and 7 are in simplex connection via stages C1, C2 and C3. The simplex connection between 6 and 7 or between terminal 8 and terminal 9 goes via line 19, stage Cl, line 11, stage C2, line 20, stage C3 and line 21.

It should be noted that between stages Cl and C2 both Telephone and teletype the common line 11

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use. This particularity, which is a feature of the invention, will be understood from the following description. Noted let it be that telegraph machines 6 and 7 are both teleprinters and other data transmission or receiving devices provided that their operating speed is compatible with the transmission speed of the system 1.

For the sake of simplicity, it is assumed that the stages Cl, C2 and C3 are identical and that they have all 16 inputs EO to E15 and 16 have outputs SO to S15. In the mediation stage Cl is input EO connected to line 19, input El with line 10, input E9 with line 17 and Input E15 and output SO are not valid, output S1 is connected to line 18, output S7 to line 11, outputs S10 and S15 are not connected. There is no connection in switching stages C2, EO. Input El is connected with line 11, input ElO connected to line 16, input E15 and output SO are not connected, output S9 is connected to line 12, output Sl2 to line 20, Output S14 with line 17, output S15 is not connected. In the switching stage C3 is input EO with line 20 connected, input El not connected, input E6 connected to line 15, input E14 to line 12, input E15 and Output SO are not connected, output Sl is connected to line 14, output SIl is connected to line 16 and output S15 with line 21.

With regard to the terminals 4, 5, 8 and 9 we take with regard to in the following description that the required memories 2, 3, 6 and 7 are available, that they are in blocks appropriate length by the system after insertion of a

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Heads are transmitted before each block that the packets and their headers from the terminals 2, 3, 6 and 7 received will.

Both the inputs and outputs of the switching stages C1, C2 and C3 and the inputs and outputs of the switching stages not shown in Fig.l are theoretically connected to stages of this system, which are not shown. Some of the stage outputs or inputs can be omitted if concentration or dilution is desired. The number of lines between two levels can be varied according to the traffic to be expected between the two levels. Thus, in Fig.l only one pair of lines 11 and 17 is provided between C1 and C2, but three lines are provided between reference symbols C2 and C3, two of which 12 and 20 of. Cl go to C2 and only a 16 from C3 to C2.

FIG. 2 shows the example of a message block with a header and subsequent data, which from here on is referred to as a message packet. This message packet represents a message as it is being prepared for transmission in a terminal, more precisely as it is in terminal

iZur
device 4 \ transmission to terminal 5 is being prepared . It can be seen that each message is made up of control characters symbolized as squares, each control character being composed of eight bits. In the special case of a PCM telephone message, each 8-bit control character corresponds to a voice sample.

As for the head and sometimes a certain number of message control characters, the content is every one

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Control character identified by only four bits, the others four bits are redundancy bits and are derived from the first four. The Control characters are transmitted with their redundancy bits in such a way that they are checked at the input of a switching stage can and if necessary;. errors can be corrected that arise during transmission over the line such as

have set.
e.g. 11, 12, etc. A checked and possibly corrected control character is regenerated. On the other hand, only the four bits of a header control character can be transmitted within the switching stage, where the risk of errors is small, while the remaining four bits are used for data transmission within the switching stage. Whenever the four bits are to be distinguished from the last four bits, we will say that the first four bits are to be binary. Control characters belong under the last four of the tenth digit of the control character.

From Fig.2 it can be seen that the message headers one after the other consists of the following control characters. Start control character DP for recognizing the start message, the Also called class control characters because it can have different values that allow different message classes to distinguish. In this example four different values are distinguished. The value 1 is used the messages within the network, the value 2 received telegraphic messages, the value 3 telephone Messages and the value 4 samples or service messages; - two control characters Ll and L2, which indicate the number of Specify control characters to be regenerated, all header control characters + control characters at the beginning of the package, if

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applicable; 256 control characters equal to 2,048 bits were used Maximum message length declared as this is the storage capacity which is often found in the market; because the control characters Ll and L2 each have four data bits contain up to 256 regenerated control characters, i.e. a complete maximum message length;

A selection counting character CS, the count of which is 1 when terminal 4 is left and whose value is increased by 1 after each passage through a switching stage if the start character DP has the value 1, 2 or 3 and by two digits after each passage, if DP the value 4, the reading of the count at each stage allows the control character to be processed in a predetermined manner; In the example described, a telephone message is considered so that DP = 3 and since three levels have already been passed, the content of the control character CS at the output of C3 is four; in . In some cases a message must go through a greater number of stages, e.g. more than 15, and if the CS count shows 15, the 16th character is designated, which is the second selection order count CS \ which counts one or two places after each pass through the Switching level is increased, follows, etc.?

the

a character I, which terminal is sending the message

concerns; in the example described, it is the terminal 4 and the character I has the value 1 corresponding to the input El of the stage Cl;

- A first control character S1, which determines the line at the output of the first stage passed through; in the described Example, the control character Sl has the value 7 corresponding to the output S7 of Cl;

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- A second control character S2, which the line to output the second stage passed through determined; here S2 has the value 9 corresponding to the output S9 of C2;

- a third control character S3, which the line at the output the third stage passed through determined; here S3 has the value 1 according to the output. Sl of C3;

- An end control character FS, which is recognized in the last switching stage, the value of which is 15, which is the transmission of the packet for the receiving terminal, which in this case is terminal 5;

- A debit control character CH, which the processing the message in the 'receiving terminal, which here 5 is determined. If the number of operations to be performed exceeds 15 with respect to this message in a terminal, two or more debit characters are provided .

The message packet marked with inf or information is then combined with the messages useful to the message user Oaten provided, with an end character FP with the value 15 being generated at the end.

As for the outgoing telephone exchange channel between apparatus As for 2 and 3, the head looks like this: 3-1O-O-1-1-7-9-1-15-CH. The last character will be later explained. For retrograde canal, the head looks like this: 3-10-0-1-6-11-14-1-15-Ch. The terminal looks similar 8 released head for message transmission

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between 6 and 7 from: 2-1O-O-1-O-7-12-15-15-CH.

It is clear that if a transmitted message is a sample with DP = 4, that there is a space between S1 and S2; another between S2 and S3 and another between S3 and FS. Later you will see how these spaces, or better O-values _{/ are used} at the output of a terminal.

It should be noted that the self-correcting code in the head characters is different from the self-correcting codes of Frame synchronization characters can be distinguished, which will be described with reference to the figure, so that these synchronization characters can be easily distinguished from other header characters.

The message, which only contains the data packet and the header, as just described with reference to FIG found in this or a very similar form both when passing through each switching stage C1, C2 or C3 as well as after reception in a receiving terminal sdwie or 9. As we shall see later, the message is transmitted character by character within the switching stage. On the other hand, the message characters on lines between a switching stage or between a terminal and its associated switching stage e.g. on lines 10, 11, 12, 14, 15, 16, 17, .18, 19, 20, 21 summarized in frames of 16 characters, as shown in Fig.3, with which the message shown in Fig.2 is reproduced on a line while it is being transmitted. The first character of each frame is a self-correcting one Synchronization sign but the self-

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corrective code will be different than that for packet headers is used so that the input interface synchronization analysis circuit can detect it.

It should be noted that the five on five lines shown in FIG Frames are all different from each other.

The first line represents a frame corresponding to the case in which no message is transported over the line will represent. The frame contains a first synchronization character with the value O followed by a padding character with the Value 15 transmitted by the sending station. In this way, the transmission synchronization between a Transmitter on one end of the chain and a receiver on the other side of the chain can be maintained.

The second line represents a frame that contains the transmission the message starts. This frame contains a first synchronization character with the value 0, followed by eight padding characters with the value 15, while the following seven characters are the first seven header characters shown in Fig.2 the message are. It should be noted that the start message can begin on any frame character, except of synchronization characters.

The third line corresponds to a frame containing the last characters of the header and the first data characters of the packet; this frame necessarily starts with a synchronization character, for which we have selected the value 15 in this case in order to be able to distinguish it from the synchronization character with the value 0, which is needed when no message is to be transmitted.

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The fourth line corresponds to a frame that only contains package characters? it starts with a synchronization character with the value 15.

The fifth line corresponds to a frame that is the last Contains packet characters, followed by self-correcting packet end characters FP, followed by padding characters of the value 15 followed. The synchronization character has the status 11 for this frame, which means that the message end character FP is indicated which was found in position 11th of the frame.

As long as no messages have to be transmitted, one only encounters frames of the type in line 1. As long as a message has not been completed within a frame, frames with data characters of the type shown in line 4 can be seen. Line 2 corresponds to the message frame of the start type and line 5 corresponds to the message frame of the stop type. There are also other types of frames that contain both a stop message and a start message. The latter frame is but ;, not shown an expert can it be readily constructed "! Messages with fewer than 16 characters so transferred in less than a frame könnter ^ are in principle not permitted."

It is also obvious that if a large number must be passed by switching stages, that the head than the longer must be shown in Figures 2 and it may be that one or more frames encountered between the lines 2 and 3, Contains header control characters with a preceding synchronization character with the value 15.

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It is understood that the above transmission system which Frame with 16 characters used, in which the first is a synchronization character, is not an inventive feature represents. A system with frames of different lengths can also be used. It should be noted, however, that a shorter frame is less useful for transmission because the synchronization characters then appear more often, so that there would be less time left for data transmission. Longer frames lead to synchronization problems, with which the error rate increases. The frame length of the present system should always depend on the quality of the Transmission channels of the system must be determined.

It should be noted that the start character DP has all values except 15 can have, with which the start character is differentiated from padding characters can be.

4 shows a switching stage in network 1 according to Fig.l shows how the switching stage Cl. The entrances EO, El, E15 and the outputs SO, Sl, S15, which are already off Fig.l are known, are shown here in Fig.4. It should be noted that the inputs and outputs are on the same side of the Switching stage are shown, as well as on the opposite side of Fig.l. This will be the two directional lines are better marked, e.g. that which contains the input line 10 and the output line 18. The input line 19, which is already shown in Fig.l mentioned, should also be mentioned.

The inputs EO to E15 are connected to the inputs of the input memory MEO to MEl5 connected, the outputs SO to S15 with the outputs of the output memories MSO to MS15

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ties are. The outputs of the input memories MEO to ME15 are correspondingly connected to the inputs 22 of a preselection switching network 23, the outputs 24 of which correspond to the inputs of the selection circle JO to Jn are connected. The outputs of the selection circuit JO to Jn are correspondingly connected via switch 25 iait the inputs 26 of a selection switching network 27, the outputs 28 of which with the inputs of the output memory MSO to MSl5 are connected »Finally, the switches 25 connect the outputs of the selection circuit JO to Jn with the Buffer inputs MTO to MTn, the outputs of which also connect to inputs 22 of preselection switching network 23 are connected"

An input memory, such as »MEO, can have several incoming messages received via line 19 / after each message has been completely saved, the Output of this input memory connected via the switching matrix 23 with a free selection circle in which the Selection characters, in this case S ^, are processed. Each input memory MEO to MEl5 has an input circuit MEEj, in which the start character OP is recognized, so that only actual control characters are stored, but not the padding characters that are on the input lines, e.g. 19, flow. First the messages are in the register memory stored and then provided with a frame so that the start character DP at the output of this register memory appears, and ultimately an output circle MES triggers the search for a free selection circle JO to Jn as soon as a start character DP the output of a register memory achieved. In the following embodiment it is shown

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how the registers can be operated in parallel.

The preselection switching matrix 23 is symbolically here as Coordinate selector is shown, the vertical of which are e.g. connected to the inputs 22 and the horizontal of which are correspondingly connected to the outputs 24. Since several input memories can claim at the same time, with To be connected to a free selection circuit, a priority selection system is provided to avoid double connections to prevent. The selection system will described later. The switching matrix 23 can consist of intersection points at the intersections of the horizontal and vertical exist; these crossing points should have a working speed that corresponds to that of the overall system is compatible.

The selection circles JO to Jn contain a register which contains practically all characters of the message header can, in order to specifically enable the analysis of the selection characters that the switching stages passed through correspond. Thus, the selection of an output memory gives access to the output channel to which the message is sent to the switching stage has to follow. As shown in Fig. 4, the output circuits can be the output memories Reach MSO to MS15 through the selection switching matrix 27. This selection switching network is the preselection field 23 similar and is shown as a coordinate selector with vertical connections to output 28 and horizontal ones Connections to the output 26. The crossing points in 27 can be of any type as long as they are sufficiently high Have speed.

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The output of each selection circuit JO to Jn is connected to an input 26 of the switching matrix 27 through a switch 25 _o In the working position, switch 25 connects the output of a selection circuit to an output 26 and in the rest position, switch 25 connects the output of the associated selection circuit to the input an associated transit memory between the transit memories MTO to MTn. You will see later that a selection circle cannot present itself as free in relation to the input memories MEO to ME15, unless its assigned transit memory can store a new message, ie "" that it has at least one free elementary memory "The outputs of the Transit memories MTO to 14Tn are correspondingly connected to the inputs 22 of the preselection switching network 23. In this way, an input 22 of 23 is connected either to an output of an input memory MEO to ME15 or to an output of an intermediate memory MTO to MTn, the humming of the inputs 22 being 16 + n + 1. The buffers have practically the same configuration as the input buffers. »Both have an input trip, theirs

the.

own register memory and an output circle, the search after a free selection circle JO to Jn triggers ^ as soon as a start character DP reaches the output of a register.

The selection switching network 27 is controlled by a priority selection circuit _f which is not shown _? the works ^ as soon as several selection circles JO to Jm wait ^ with the same output memory MSO to MSIS are connected to ο ■ * ■ - ,. -

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The output memories MSO to MS15 are the input memories MEO to M215 the same. They contain an input circuit, their own register memory and an output circuit.

In order to provide a simple description of how the switching stage works, 4, we follow a message that appears on line 19. It is assumed that one of the storage registers MEO is available. The MEO input circuit recognizes a start signal DP and forwards this message to the available one Register. When the stop signal FP is recognized in the input circuit from 1ΙΞ0, the following signals go into the Register, but they become one through the input circle other available «registers. In the register

the stored message is provided with a frame, i.e. it moves until the character DP is the starting position of the register has reached. The starting circle from MEO then requests a selection circle JO to Jn and the one not shown Priority dialing area connects a free selection area with the exit from MEO via the switching matrix 23

It is assumed that the selected selection circle is Jl. As soon as this circle is selected, it corrects the transfer the iJ message header coming from MEO goes through 23 and enters the selection circle Jl. Two characters in particular are analyzed in this register. First that Control character SI, which in this case indicates that the message must leave the stage at output S7, which is with is connected to the memory output MS7. Consequently, the selection circuit J1 will request output memory MS7 and the

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If there are several selection groups _? the selection circuit Jl included, request to be connected to the output memory i4S7, work in a special way. If the connection between Jl and i4S7 should be possible directly, then the switching matrix 27 connects the output 28 corresponding to MS7 with the input 26, which belongs to Jl and additionally the selection circuit Jl ₄ acts, which recognizes that it is connected via the output memory MS 7 is, switch 25 is energized. Which connects the output Jl with the corresponding input 26. o Circuit Jl then controls the transmission of the remaining message that follows the head from memory MEO to Jl and at the same time the transmission of the head and then the rest of the message from Jl to the output memory HS 7.

Ls are jedocn other cases possible in which instant connection of Jl to 1,437 per selection circuit Jl must then transfer the message header is not possible if, for example memory MS7 or if there are other selection circuits with the memory MS 7 connected no free register memory, preserved and a predetermined time wait, at the end of which several decisions have to be made, depending on the type of message to be transmitted. As already mentioned, the start character has four possible values and these values are analyzed in circle Jl. If the value of DBi is a service message, then circuit Jl must continue to wait for a connection to memory MS7. If DP2 corresponds to a telex message, the selection circuit Jl connected to the intermediate memory MTI via switch 25 will, at the end of a predetermined time, the header and the remainder of the message it

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received from MEO is transferred to the intermediate storage MTI. If the value of DP = 3, this denotes a telephone message, then the selection circle Jl, the Still connected to the MTI cache, the header and the rest of the telephone message to MTI are transferred to it unless the 10th digit of the character DP corresponds to a predetermined digit N. In this case, the selection circle Jl cancels the message header, which it keeps and forwards the transmission of the remaining message from MEO to Jl and cancels all control characters, FP included, in the remainder of the message. Every time when a selection circle transfers a ready message to a buffer, the 10th figure of the character, DP increased by one digit; this 10th figure can reach a maximum of 15. In addition, if the Selection circuit Jl is connected to the output memory MS7, it transmits, as already said, the head after the 10th digit. of the character DP was reset and after Increase of the selection counter CS by 1. If the value this character DP is now 4, becomes circle J4, which is not with

Service memory MS7 can connect a persistent message as many times as necessary into the intermediate memory MTI transfer. But the moment the reference character J1 is connected to the output memory MS7, the head is changed. Two digits are added to the selection order counter to add the 10th digit of the DP character read and around this 10th digit in a character which corresponds to the Head follows to write at a predetermined position · Then the 10th digit of the start character DP is canceled. In fact, in this last case, one would like to know how often a message had to wait in order to count the waiting time in a

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To be able to determine the switching level.

As already said, the input memory ME, intermediate memory MT and output memory MS each contain different register memories. The register set of a memory can be controlled in different ways. The registers can, for example, be energized in a fixed sequence, ie the first free register selected by the input circuit of the memory is always the register which immediately follows the register in which the message arrives. In the same way, the output circuit of the memory selects the following registers in the order in which the messages are stored. According to another method, an available register is randomly selected from all available registers of the memory with the aid of an input selection circuit and one of all registers whose content is in frame form and whose output line is occupied by a character DP with the aid of the output selection circuit. A memory type is described in detail later, in which the register selection at the output and at the input occurs randomly.

All discrete lines 22 "24 ^, 26 and 28- are three-core. One wire is used for the transmission of the control character f a second wire is used for the transmission of the synchronization signal for organs such as input _{memory p} selection circuit, output memory or buffer and finally a third wire for signaling between two connected organs. The switching matrices 23 and 27 are therefore provided with crossing points that can switch three wires.

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From the above it can be seen that each switching stage has a certain number of operating characters with the Sends out a message, especially in the message header. There is recognition of the start character in the input memory DP, regeneration of the characters to be regenerated, the number of which is determined by the characters Ll and L2; In the selected selection circle there is the analysis of the start character DP, that of the selection character S accordingly the selection level in question, etc .; the matching synchronization character is found in the output memory before transferring on the line to the next stage, etc. That is why it is necessary to take between 2-by-2 Units of a switching chain within a stage have a character-ura-character transmission system to be provided, with the possibility of stopping at each character if an operating character or an operation has been carried out in one of the units, such as \ an analysis needs a stop in the transmission to be finished before the arrival of the following character.

Fig.5 shows a unit U, which in the following with input unit is designated to indicate that it is transmitting messages which are processed in a unit D. which is also referred to as the input unit to indicate that it is receiving the message. In the Unit ü, the message or part of the message is stored in a shift register REGU, which e.g. consists of eight bit cells, each of which is a message character wearing. It should be noted that the REGU register is also divided into several sections that are connected in series,

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can be split up with indexing in the different sections that appear like a single register.

The message is transmitted one after the other on line BD, which runs from the output of the register REGU to the input of the register REGD in unit D. The registry RSGD is similar to the REGU register.

Unit U contains a transceiver TRU and unit D, a transceiver TRD, transceiver TRU and transceiver TRD are connected to one another by two lines SY and SG, where line SY is the bit synchronization transmits and line SG the message itself.

The transceiver has four signal inputs: CANU is excited when unit U in U and D, the register contents REGU and REGD, decides the cancellation, RELü Is ₍ excited when unit U decides to release unit D at the end of the message transmission; BLOU, which is excited if the unit U decides to suspend the transmission for the duration of a character; and PREU, which is energized when unit U is ready to begin sending the start message.

The transceiver PRD has similar inputs: CAI-ID, BLOD, PRED, the functions of which can easily be derived from those of the corresponding inputs of the transceiver TRU.

Transceiver TRU has five signal outputs ACBD, which provides a signal when the input BLOU has been energized and when the blocking device in TRD received has been; NACD, which delivers a signal when the

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Input CAÜD has been excited; LERD, which is a signal supplies, when the input RELD has been energized, OLBD, which supplies a signal when the BLOD has been energized; and ERPD, which provides a signal when the PRED input has been energized.

Transceiver TRD has similar outputs: NACU, ACBÜ, OLBU, LERU and ERPU, their functions slightly different from those derived from the corresponding outputs of the transceiver TRU can be.

Transceiver TRU has an input CLU for clock signals supplied by a clock CL, while frequency is the bit frequency; an output SBU, are given by which the Bitsynchronisationssignale to the register REGU for pushing, an output SYU be transferred through which the clock signals to the input SYD of TRD, and an output SGU by which the disadvantages ⁷ directed transmitted to the input SGD of TRD will. The transceiver TRD has an output SBD, through which bit synchronization signals are sent to the register REGD in order to shift it, and a special output SYA, through which the clock signals can be transmitted to other circuits of D, if necessary.

The operation of a transmission system according to FIG. 5 is described below. Assume that the veins BD, SY and SG through a switching network, like the preselection field 23 or selection field 27 or another Selector, as we shall find it later in this description, of which each field or selector is three-wire Have intersection points.

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As soon as the units TRU and TRD are finished, the one with Sending and the other receiving, the input presence inputs PREU and the output presence inputs PRED energized, as well as from the corresponding outputs ERPU and ERPD, which trigger the start of the transmission when the the crossing point connecting two details is closed and the outputs SBU and SBD are synchronous The clock signals are energized in order to ensure the synchronous operation of the registers REGU and REGD be transmitted by SY. In every 8-bit mining there is there are eight moments and at each moment the state of the wire SG, whether current is flowing or not, which theoretically is the state one of the signal outputs or, as an exception, the common state of two input signals that go to TRU and TRD belonging is displayed.

As long as the character-by-character transmission is uninterrupted is transmitted, only the inputs PREU and PRED are energized. When unit D recognizes a character in REGD, which it has to process and if the processing time has to last one character or more, the Output blocking input BLOD energizes, which in TRU the transmission of the following character, during which the BLOD input is energized, blocked. This will make the outputs SBU and SBD at the end of the character for the following Locked characters. As you will see later, TRU sends back a blocking identifier, which is sent to D via ACBU and D is allowed. BLOD input to block or to re-energize if blocking is longer than one Character must last. It should be noted that during the blocking the wire SY continues to feed the clock signals

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transmitted, whereby the synchronous operation of both transceivers is secured.

The inputs PREU and PRED remain energized and thus show indicates that a transmission stop has taken place while the Units are still in communication.

At the end of the message, unit U energizes the release input RELU, which is transmitted at the end of the character output LERO and LERU, indicating that unit D is starting its processing in "disconnected" mode can. In addition, internal connections are created that reintroduce all bistable circuits to be provided in TRU and TRD.

Nominal unit D is a character error during a processing step recognizes, it can decide ^ to cancel the whole message and do so: namely the exit cancellation input CAND to excite. Apparently Circle D cancels the contents of REGD and with ^ the excited Output NACD cancels U the content of REGU and then e.g. energizes the input release input RELU. In order to the starting point of the previous processing step is reached again.

In theory, it is the input unit that makes the release decision falls because it knows the end of the message sent. Therefore, the RELD input in D is in the example not used.

The signals passed through two transceivers such as TRU and TRD are shown in the table below.

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In the normal state when transferring characters between U and D a signal is applied to the terminal PREU of TRU and a signal to the terminal PRED of TRD. on the other hand no signal is sent to the CANU, RELU, BLOU, CAND, RELD and BLOD created.

It should be noted that the communication through the switching stage according to FIG. 4 can sometimes, as will be seen later, involve three units in a row at the same time. This applies in particular to a message whose header has already been processed by a selection circuit which has found a free output memory to which it has started to transmit. At this point in time, the start of the message in the output memory is a small part of the passage through the selection circle and the end is still in the input memory.

Time slot in
within one
Character From input to output input,
hext transmitted signals
(Seride receiver TRU) 1 2 From exit to entrance
unit transferred Si
gnale (transceiver TRD) 1 2 0 LERD M. BELD M. 0 CANU 0 Exit release NACU P. 1 Incoming cancellation OLBD M. STUPID M. 2 RELU 0 Curfew LERU P. 3 Output release NACD M. CAND M. 4th BLOU 0 Initial annulment OLBU P. 5 A whole special 6th curfew ACBD 0 Entry lock ACBU M. Identifier PREU M. Identifier PRED P. 7th Entrance attendance Starting property
Ness

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It goes without saying that we transfer systems according to FIG. 5 who work in tandem. In the previous example, the clock is in the output memory housed and he synchronizes a first system, which between himself and the selection circle is working. Circuit TRU of the selection circuit has a supply synchronization output analogous to SYA. The output signals from SYA are used to synchronize a second transmission system is used, which operates between the selection circuit and the input memory. It should be noted that the transmission system according to FIG. 5 both from the output unit and from the input unit can be synchronized.

In the following figures, the transmission systems are shown schematically by two rectangles with a reference starting with three letters TRU and TRE are shown, followed by letters indicating which system unit they belong to. Only the inputs and outputs that are necessary to understand the invention are shown.

A multistable circle is shown in FIG Random selection circuits in different units of the switching stage, such as that in Figure 4, is used. Considered be an input memory such as MEO, of which we have already mentioned that it contains various register memories, an output and an input circuit. As already mentioned, a register memory is available or free if it is empty, and since different registers are available at the same time, a selection circle is required in the input circuit to select the register memory to which the next message will be directed. At the exit of the

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Multiple registers can store the message with frames so that the character DP appears in the last line and the starting circle, which is a selection circle contains in order to search the registers, their message is sent to the selection circle, e.g. JO. It understands that we find the same circles in the output memories MSO to MS15 and in the intermediate memories MTO to MTn. The selection work in the coupling matrix also requires selections, which are described in detail later.

It was assumed that all of these selection circles form a multistable circle _; as shown in Fig.6. In theory, this multistable circuit 29 can have any number of inputs. However, to simplify the illustration and description, only three inputs 30, 31 and 32 are shown. The multistable circuit 29 has as many NAND input gates as it has inputs. In this case the gates 33, 34 and 35. Each £ JAND gate works like a UIiD gate, followed by an inverter and has as many inputs as the multi-stable one, Weis in this case three inputs. The output of each gate is connected to the output of a multistable circuit. In this way, the output of 33 is connected to the output, the output of 34 is connected to the output 38, and the output of 35 is connected to the output of 40. The outputs of the gates 33 to 35 are also connected directly with respect to the inputs of a NAND gate 42, the output of which is connected to the output 43 of FIG. The first input of 33 is connected to the input of 30, while its second input is connected to 40, ie to the output of 35 and is its third input

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connected to 38, i.e. to the output of 34. The input connection of 34 and 35 can easily be derived from those of 33.

It is assumed that there is no logical one signal at the inputs 30 to 32 is present, each gate 33 to 35 supplies a logical 1 and the output from gate 42 is logical O, which indicates that all inputs 30 to 32 are not available.

It is assumed that a logical one signal is present at input 30 and that 31 and 32 carry logical 0 signals. The three inputs of the gates 33 are in the 1 state and the output of the gate is logic 0. This O signal, which is applied to 42 leaves output 43 in the 1 state change, which indicates that at least one of the inputs of 29 is available, and additionally will the logic 0 is applied to the second input of 34 and to the third input 35, which means that if a Signal 1 applied to one of the inputs 31 or 32 or both is, the state of the gates 34 and 35 will not change as long as the signal 1 is present at the input 30. Circle 29 is therefore actually a rault-stable circle. Such a circle was already in the French U.S. Patent 1,388,503 issued June 28, 1968 has been applied for and is shown in Figure 5 of this patent.

It is assumed that there is a simultaneous! Signal at inputs 30 and 31 and that at the output of gates 33 and

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logical O is present. The zero signal from 33 is sent to the input of 34 is applied, which will change its state again and the signal O of 34 has the same effect on the Gate 33. However, these gates are not always complete identical, especially with regard to the switching speed from one state to the other, so that the fastest gate to impose its output signal on the other and only one of the outputs will remain in the zero state. From this point on it repeats itself the previous way of working.

It is easy to see that if all inputs from 29 at the same time a 1-signal received, that only one goal lasts changes its state. The reasons for this are the different switching speeds. Summarized let it be that the selection of an input among different ones at the output 29 is a logical 1 at the input and a logical O at the output corresponds to the selected input.

In the input and output circuit of the input memory ME, Output memory MS and intermediate memory MP can use outputs 36, 38 and 40 directly to control the switch, connecting the selected registers can be used.

In Figure 7, a selection device is shown, which connects an input memory WE to a selection circuit J via the preselection switching network 23. This selection device uses multistable circles such as 29 from Fig. 6. From Fig. 4 we know that the outputs of the intermediate

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memory MT iait that the selection circuits can be connected via the same switching matrix 23 and that the circle in FIG. 7 makes a selection between the input memories ΜΞ and the intermediate memories MT, which are treated in the same way. On the left, the output circle MES of the input memory ME is shown, at least the parts that play a role in the selection of the selection _{circle J and the output circles MTS of the intermediate memory MT and on the right as far as the parts are involved /} the circle J. On the left you find the circles MESO's Memory MEO, MES3 of memory ME3, MES15 of memory ME15, MTSO of intermediate memory MTO and MTSn of intermediate memory MTn and right the circles JO, J5, JK and Jn. The circles MES3 and J5 are shown in more detail. The other circles correspond to these and are the same. In the lower center, the switching matrix 23 is shown with its control circuit CCP. The circuit MES3 contains a multistable circuit 45 which is the same as 29 of FIG. 6, except that an OR gate set 54 and 64 is added for each input, as well as a branch circuit 46 and a control circuit 47. Circuit J5 contains an available circuit 48, a multistable circuit 49, which is the same as 29, and a control circuit 50.

The multistable circuit 45 has a NAND input gate set, from era only gate 51, whose entrance through line 53 with the Output of the OR gate 54 is connected, shown whose first input via wire 52 with the available circuit 48 is connected. The other inputs of 52 are connected as in FIG. The output of 51 is with both the corresponding inputs of other gates 51 connected / as

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- 33 -

but also an inverter circuit 55 with the first input of an [MD gate 56 of the branch circuit 46 »

The control circuit 47 essentially contains the transceiver set TRUi-IES of the input memory ME3 and the output selector SMES of this store. A single transceiver TRUMES is shown with its input PREU and its outputs SYU, SGU and ERPD. The PREU inputs of the senders TRUES are connected to the corresponding inputs of the OR gates 65, the output of which is parallel to the second inputs of the UrtfD gates 56 are connected. The ERPD outputs from TRUES are connected to the corresponding inputs of the OR gate 64, the output of which is in parallel with connected to the second inputs of the OR gate 54 »The Outputs SYU and SGU are via the corresponding wire BD connected to one input of the selector SI-IES with the field 23, as can be seen in connection with FIG.

The branch circuit 46 contains an end gate set 56 and the OR gate 65. This guides the decision made in 45 to district 49 in J5 "

The disposition circuit 48 in J5 contains an AND gate 57 with an input 58 which is connected to the output of the disposition circuit of the intermediate storage HT5 input circuit within J5 and a second input which is connected to the output of the ID gate 59 , which has two inputs, one of which is connected to the output LERU of the Sendeeinpf ängers TRDJ of the control circuit 5O and the other to the output LERD of another transceiver TRUJ in JS, which is used for transmission to the output memory MS or

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Zwisciienspeicher MT is used. The exit of gate 57 is connected to the wire 52, which is often over all gates 54 according to J5 in all selection circles 45 of the output circles MESO to ΜΞ315 and MTSO to MTSn is available.

Oer multistable circle 4 9 contains a NAüD entrance gate set, of which only gate 60 is shown. The first input of 60 is connected to the output of AND gate 56 via wire 61. There are as many wires 61 and NAND- Ίοχ & 60 as there are memories ME and IAT . The multistable circuit 49 also contains HAND gate 62 analogous to 42, the output of which is connected to the input PRED of TRDJ in 50. The control circuit 50 contains a coder 63, whose inputs are correspondingly connected to the outputs of the HAoiD-'JJore, such as, for example, '60 and whose outputs are connected to the. Inputs of the preselection control circuit CCP are connected. Coder 63 may be of the type described in French patent 1,588,503 mentioned above. In Figure 7 only the output of 60 connected to 63 is shown, as well as a single multiple line between 63 and CCP. The other GCP inputs are connected to the coder of the other circle 50 in circle JO to Jn. Control circuit 5O also contains transceiver TRDJ with inputs SYD and SGD _1, input PRED and output LERU.

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The inputs SYD and SGD are together with the associated Wire BD connected to the output of field 23, the output of which belongs to J5 »

In order to describe the operation of the selection system in Figure 7, it is assumed that circuit MS3 calls, ie _f that its memory ΙΊΕ3 in which the mark DP have a message reaches the last cell of at least one of its registers that the selection circuit 5 is freely and that the other memories and selection circles are occupied.

Gate 57 delivers a signal with the available circuit J5, because its two inputs are marked.The input circuit of the intermediate storage MT5 in J5 is available (even if its output is occupied by other selection circuits) and marks the output 58 and gate 59 is open because TRDJ and TRUJ of J5 (see Fig. 10) are idle _o With all other J-circles that are occupied and the ERPD output of each TRUMES of MES3 that are idle, the OR-Tpr 54 is in together with the other J-circles Quiet, resulting in a logical 1 at the output of each NAND gate, = The output of gate 51 is logical 0, which is sent to the other NAND gate to lock it on the one hand and to the inverter 55, whose output signal i is on the first input, on the other of the associated tMD gate 56 , the second input of which, like PREU by TRUMES, is also marked with OR gate 65 _{or the like}

The logical! Output from gate 56 is given to the first input of NAND gate 60 through wire 61. All other in-

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gears up to 60 are in the 1 state, as there is no other ME or MT memory calls. The logic 0 from the output 60 is given on the one hand to the corresponding input of the coder 63, which from this the address of the memory ME3 is determined to be connected and to the NAND gate 62, which is a logical 1 at the input PRED of TRDJ in 50.

As soon as the connection in 23 has taken place, the lines BD, SY and SG are lengthened, which is how TRUMES works and TRDJ is synchronized by the clock in J5, as we will see later and the output ERPD changes to the 1 state through 64, making the state of the multistable circuit 45 independent of its input state changes will. The state of the gates 56 and 60 remains. therefore unchanged. On the other hand, the gate 57 in 48 no longer stays open, because neither output LERU of TRDJ nor output 59 remain marked. As already said, the condition remains of the multistable circle 45 unchanged.

When the end of the message has been transferred from ME3 to J5, as will be seen later ^ release commands are exchanged and output ERPD from TRUMES changes to the 0 state, which unlocks circuit 45 via 64. the The connection in 23 is also interrupted because the gates 56 and 60 and the coder 63 change state.

The above description was based on the assumption of an individual calling memory and a single free selection circle; if you look at the workings of the multistable One can imagine the circle in Fig. 6

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easily the case of multiple calling stores and multiple Introduce free selection circles.

In Figure 8, the input circuit MEE is an input memory ME shown. All input memories and input circuits are identical, regardless of the level of the considered System according to Fig.l. However, in order to work on a To be able to illustrate a specific example, we assume that Fig.8 the input circuit MEE of the input memory MEl

represents

the switching stage Cl / and that the message to be received comes from the connection 4 and that this message is the Has the shape shown in Figure 3.

Line 10 is connected to a digital data receiver 65, the first output of which is connected to the input of a bit synchronization separation circuit 66 is connected and also to the input of a frame synchronization recognition 67, whose second output both with the input of a control character and regeneration circuit 68 and with the input of a 8-bit register 69 is connected.

The output of the circuit 68 is connected to the first input of a switch 70, while the output of the register 69 is connected to the second input of switch 70 «The output of 7O is connected to the input of a Register 94, the two consecutive characters of a message. a first and a second Can store cell, and its output with a wire BD is connected, which has the same puncture as the vein BD in Fig.5. The wire BD transmits the useful characters Selector SMEE for one of the storage registers MEl "

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- 33 -

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The control input of switch 70 is connected to the 0 output a flip-flop 74 connected. When output 1 of this flip-flop is energized, switch 70 transmits the characters that from register 69 konunen. On the other hand, if output is 0 is excited by 74, 70 transmits the characters controlled and regenerated by 68.

The reception circuit 65 is a synchronization separation circuit 66 and the frame synchronization detector 67 are conventional circuits such as those used in digital data transmission systems are used and they are interconnected in such a way that a The cancellation signal reaches the third output of the receiver 65, which is connected via an OR gate 89 to the cancellation input CAiJU of the message transceiver TRUMEE so that no signal is transmitted to the second output of 65. When the synchronization is in time only tfachrichtensignale ^ are excluded synchronization signals, from second output of 65 transmitted.

The output of circuit 66 is first to the bit synchronization input of the recognizer 67, secondly to the bit synchronization input of a character synchronization circuit 75 and finally to the first Input of a UüD gate 71, the second output with the first output of a flip-flop 72 is connected. Input 0 of flip-flop 72 is connected to the output of an inverter 73, whose input is connected to the output ERPD of the signaling circuit TRUl-EE.

Recognizer 67 has five outputs. Output 77 is connected to the Zetchen input of circuit 75. The exit of

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is connected to the first input of an AND gate 84. Output 78 which occurs during the entire period of a frame supplies a signal when the frame synchronization signal deviates from 0 or 15 with the first input of a Flip-flops 88 connected, the 1 output of which with 'the first Input of a Ul-iD ^ gate 83 is connected. The exit from gate 83 is with the counting input of a binary counter

85 connected, which has five stages associated with counting from O to 17 are connected and is with setting inputs

86 connected to enable the original value can be adjusted to its first four levels. Output 79 represents a cable with four output ports, which are connected to the inputs 86, which supplies the 15th complement of the synchronization character value «, Output 80 is connected to the second input of AND gate 84 via inverter 87 and supplies during the period of time one signal for each frame synchronization signal. Output 82 connects to the first input of OR gate 109 connected, which has three inputs and whose output is connected to the input DLOU of the circuit GRUMEE istj it supplies a signal to start the character “which each Synchronization signal precedes,

The regeneration ^ and control circuit 68 verarbeitet- the self-correcting code mark and used for the processing of a character, the transmission time of a character "It includes a control input 9Q _4, which is connected to the first input of an AND gate 91 whose output is connected AESM input CAMU via the OR gate 89 is connected. Every time a character is incorrect and not regenerated

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can, a signal is transmitted from output 90. register 69 contains a cell which is designed in accordance with the transit time in 68 to deliver characters to switch 90 who are in phase with those of 63 coming. The second entrance of the gate 91 is with the exit 0 of the flip-flop 74 connected.

The output of gate 84, which normally supplies a signal in phase with the output signal of the symbol synchronization circuit, ie at the receiving end of each symbol, except synchronization symbols, is firstly connected to the clock input of a sequence counter 92, which has the four positions 0 to 3, and secondly to the Input 1 of a flip-flop 72 _f which does not allow the clock pulses coming from 66 to continue running until the start of reception of a character, thirdly connected to the second input of a gate 83 with the first input of an AND gate 106 and fourth with the test input of a comparator 95. As will be seen later, the counter 92 is used to count the first four characters of a header. In the rest position it has the status 0. After the fourth character of a message and until it is reset, it remains in position 3, as you will see later.

The parallel output of the first cell of the register 94.der like all other PaxsLlelausgangs has as many wires as data bits, is with the code input of the! Comparator 95 as well as with an AND gate set 96, the number of which corresponds to the number of parallel outputs (for simplification in the following only one exit and one gate are considered). If the pending code differs from 15

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(til t

I I · ·

■ ι ι ·

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separates, the comparator 95 emits an output signal at the moment in which a signal coming from gate 84 is present. The parallel output of the second cell of the register 94 is connected to the first input of the AND gate 97. The second inputs of the gates 96 and 97 are connected in parallel to the output 2 of the counter 92.

The O output of the flip-flop 74 is connected to the first input of the UtfD gate 104, which has three inputs, the second of which is connected to the output of the comparator 95 and whose third input is connected to the O output of the order counter 92 and whose output is first with the first first input of an AND gate 98, which has two inputs, and second with the first input an AND gate 99, which has two inputs, is connected. The output of the AND gate 98, whose The second input is connected to the output ERPD of the signaling circuit TRUMEE, is to the counter input of the order counter 92 connected.

The selection circuit 100 has as many inputs 101 as there are register memories are present in the memory ME. The input 101 is energized as soon as its associated register is free; it works like circle 29 in Fig. 6 and has as many outputs 102 like inputs 101. The outputs 102 are connected to the inputs of a conventional control circuit 103, which is able to assign the intersection points associated with the selected registers 100 in the selector SMEE conclude. As soon as a register is selected, the signaling circuit TRUMEE is activated by SMEE with the assigned

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connected signaling circuit TRD of the register and the output ERPD is marked, with which the availability signal ^ is given to the AND gate 98.

The output of the AND gate 99, the second input of which is connected to the output of the inverter 73, is connected to the input 1 of a flip-flop 108. The 1 output of flip-flop 108 is connected to the third input of OR gate 109. The 0 output of the same flip-flop 108 is connected to the output 37 of the counter 85. The output of the binary counter 85 is also connected to the reset input of the order counter 92 through an OR gate 105. The second input of the gate 106 is connected to the <Jem 3 * output of 92 and the output 106 is connected to the counting input of the binary counter 107. The counter has default inputs, which are connected to the corresponding outputs of the gates 96 and 97, which allow _y to predefine an original value before the start of counting. Its output is connected to the 1 input of flip-flop 74. In theory, binary counter 107 can count up to 255. It should be noted that the outputs of the register 94 _{transmit the complementary values of the characters L1 and L2 /} which are stored in the register.

The 0 output of the order counter 92 is for

one connected to the second input of the OR gate 109 and on the other hand with the 0 input of the flip-flop 88 and with the reset input of counter 85. Output 1 of order counter 92 is connected to the input of a monostable multivibrator 93, the output of which is connected to the parallel tenth input of the first cell of the register 94

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is to the tenth figure of the character at the moment when Counter 92 changes to position 1 to be able to cancel. In this way the tenth piece of DP is canceled, before it is transferred to the memory ME.

The message transceiver circuit TRUMEE is the TRU circuit in Fig. 5 the same. Its release input RELU is with the Output of a binary counter 85 connected. Its output NACD is connected to the reset input of the counter via OR gate 105 92 connected.

It should be noted that all registers 68, 69 and 94 are synchronized to the TRUMEE output SBU by connections (not shown) will.

The operation of the input circuit MEE in Fig. 8 is will now be described with reference to the reception of a signal shown in FIG.

The first synchronization signal O is received by the receiver 75 and fed to the recognizer 67, it being assumed that the bit and character synchronization Ln are clock. Output 78 is not energized. It should be remembered that the relevant initial state for order counter 92 is the 0 state and that for flip-flop 74 is also the 0 state. Switch 70 allows signals coming from circuit 68 to pass. It is assumed that the checking and regeneration of the characters is in order. It is further assumed that at least one register of the memory ME is free and connected, and that the output ERPD of TRUMEE is energized.

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Therefore gate 9 8 is opened as soon as the output of gate 107 is energized. As soon as the comparator 95 has a DP character detects, it delivers a signal to the output of the gate 104, which is excited because the other two inputs through the counter 92 in the 0 state and the flip-flop 74 in the 0 state are excited. In addition, the clock signal from Gate 71 is transmitted synchronously with the received character bits.

In the first frame, the following characters with the value 15 are transferred to register 94 via 68 and 70. on in this way the characters of the first frame do not change the state of the circle MEE. The same applies to them first eight of the second frame too.

The mark of rank 8 in the second rank is a DP mark, which is stored in the first cell of 94. As soon as this DE. Character is stored, which has the value 3 has, since at the beginning of the telephone message the connection 4 comes heard ^ it is compared in the comparator 95, the supplies an output signal which opens gate 104 and thus triggers counter 92.

Counter 92 changes to the 1 state, whereby the 10th figure is reset by DP in 94. The modified DP character arrives in the second cell 94, while the character Ll in the first one occurs. Gate 104 is closed. The blocking signal transmitted up to now is now suppressed by gate 109.

Counter 92 changes to receive the next character synchronization signal which comes from 75 to 84 into the 2-state. Character Ll goes to the second cell of 94 and character L2 enters the first cell. The gates 96

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and 97 are open and the complements of the values of Ll and L2 are supplied to the binary counter 107. Character Ll moves from 94 to memory ME and is replaced by L2.

Counter 92 changes to state 3. The following characters are successively transferred from 68 to 94 through 70 and from 94 to ME as described above. The state of the MEE circle does not change until the recipient receive the character preceding the synchronization character with the value 15 at the beginning of the third frame Has. Output 82 of 67 is then energized, which, via BLU, is followed by the transmission of the following character from MEE ME blocked. The synchronization character is recognized in the recognizer 67 / whose output 68 is not excited. Of the. exit 80 is energized and blocks gate 84 for one character in counter 107 during a synchronization character is prevented from increasing its value. It's open-* Obviously, that the character should not be counted because it is not part of the message header. If at a message that differs from the one shown in FIG. 3 between two of the first four control characters Character arrives, the counter 92 would also lock for one character. This stop of the counter 107 and if applicable 92, as well as blocking the transmission by BLOU after ME appears on every frame with every synchronization character and is not described again.

In response to the following character S3, the counter 107 starts again to work and circle MEE returns to the state which preceded the arrival of the synchronization character.

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is gone. As can be seen from the example of the message according to Fig. 3 knows, the characters Ll and L2 are to be checked by eight and corrective characters are determined and the counter 107 is filled with the corresponding complementary number 247. if the counter has counted to 255, it supplies an output signal which switches the flip-flop 74 to the 1 state, whereby 70 is switched and gate 91 is blocked. As the following characters of the package are not self-correcting circle 68 can no longer carry out a cancellation, i.e. excite CAiJU over 89. Switch 70 connects the output of 69 with the receipt of 94. In this way, the uncorrected characters of the packet are replaced by 69 transfer.

The transmission continues in this way until the synchronization character of the fifth line of the message according to Flg.3 is reached if a synchronization error does not occur, which cancel the message in register ME would.

When the synchronization signal of the fifth line in detector 67 is recognized, its output 78 is excited (which subsequently causes the flip-flop 88 to change its state learns and the gate 83 is opened). The output 79 is energized, causing the 15th complement of 11 in the first four levels of the binary counter 85 is set. When counter 85 has reached the value 17, it supplies an output signal, which resets counter 92 energizes the 0 input of flip-flop 74 and provides the RELU input of the circuit TRUMEE free; the flip-flop changes its state. The end-of-message character FP can be used by the second cell of 94

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are transferred, but will not be transferred to ME because the memory was released during the transfer of the last Data character of the message was arranged.

It should be noted that the end of the fifth line of the message after FP consists of the numbers 15, whereby the start of the following message is initiated, is transmitted by 10, which is recognized in the manner described above will. However, it is possible for a message to start in the same frame in which a message ends. In this case there must be a pause for a pad character during the transmission time between stop signals FP and the following start character DP can be provided in order to synchronize the clock after a new input memory cell to search. The character DP is then recognized because the ERPD exit when a new memory is searched for has been marked and the AND gate 98 opens.

It should be noted that even if a cancellation command was transferred from register TRD from ME to circuit TROMEE, this is possible in accordance with the circle according to FIG. 5, the counter 92 from the output NACD reset via OR gate 105 and nothing further is transmitted to ME until a new message is recognized. It should also be noted that upon the arrival of a message, the TRUMEE circle indicates no availability, the whole The message is received in MEE, but is not transmitted further because flip-flop 108 orders the transmission of blocking signals during the entire reception period.

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Pig.9 represents an input memory ME or an intermediate memory MT represent, in particular the battery of register memories RM and the memory output circuits MES, their input circuits MEU which have already been shown in Fig.8, on the left half of Fig.9.

In the example described, the battery of the register memories RM contains the registers RM1, RM2, ..., RMp. the Register number ρ is determined by the one in which the memory is contained Switching stage determines the traffic handled, i.e. the type of traffic, the number of selection circles in the stage, the average detection time of a message within a register, etc. In a first approximation if the number ρ is at least 4, if the first memory is considered empty, the second a message 8 stores, the third provides the containing message with frames to this at its output already usteIlen and the fourth is used to transmit a Message to a selection circle with which it was connected as described with reference to FIG. In practice, the The number of registers must be greater than four, because, for understandable reasons, there must be security and reliability be guaranteed during rush hour.

Each register contains a memory unit 110 with an associated memory logic 116. This unit contains in the example described an input cell 111, a certain Number of memory cells and one output cell 112. The input cell 111 receives the bits of each character one after the other, i.e. the eight bits of a character, via wire BD fall one after the other into cell 111. Then the signs become fed into the memory cells in parallel, character by character.

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The output cell 112 carries the bits of each character serially, which then appear one after the other at their output 113. It should be noted that the unit 110 is a memory of the silo type, as in the November 8, 1971 issue pages 85 to 89 in "Electronics" in an essay entitled "Dianamic MOS shift registers can also simulate stack and silo memories". These Among other things, memories require the data they contain to be refreshed at predetermined time intervals. For this purpose, an output 114 is provided to a To suppress signal in 110 which is energized when the memory is being refreshed and therefore not is able to transmit characters to its output 113. The unit IiO also includes a command signal output 115, which is energized as soon as a start character DP has reached output cell 112, thereby indicating indicates that the message has been framed. A circle indicating the absence of data in unit 110 examined, if this should be empty, is also provided in 116 and the output of this examination circuit is via wire 133 with the first input of a AND gate 118 connected.

Each storage unit 110 contains at least as many cells as how the message contains at most characters, e.g. 256 characters in the example described.

Each register also contains an output transceiver TRDME, which works together with the input transceiver TRUMEE works according to Fig.8. The inputs SYD, SGD and PRD as well as the outputs ERPU, LERU, SBD and · NACU are specially designed

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indicates. It also includes an availability flip-flop 117, which is in the 1 state when the AND gate 118 is open. Output 1 of 117 is with the corresponding Input 101 of the selection circuit 100 is connected (see Fig. 8) and to the input PRED. Of the The O input of flip-flop 117 is connected to the LERU output. Output LERU is also via an OR gate 132, which has three inputs, with the input 1 of a flip-flop 119, the output 1 with the first input an AND gate 121 is connected, which has three inputs. Circle 120 provides internal clock signals that the Advance characters in unit 110. The output of 120 is connected to the second input of an AND gate 121, whose output is connected to the second input of a circuit 122, which is used as a time reference for the Memory logic 116 functions and its first input is connected to the SBD output of TRDME and its third input is connected to the SBU output of the TRUMES circuit. Output 123 of 122 has three wires that via 116 with cell 111 for the transmission of the bit synchronization required for the serial input each Character, which comes through WD of the input circle in Fig.8, secondly with cell 112 in a similar way as the Serial transmission of each symbol and third becomes a symbol synchronization signal during the frame transferred to the character advancement in 110. For example, circle 122 contains a divisor that divides by eight to obtain the To receive the signal of the character from the bit synchronization through TRDME -.- The circuit of the circuit 122 is conventional, if silo storage is used, as already mentioned.

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The third output of the UHD port 121 is with the 0 input of a flip-flop 124, the 1 input of which is connected to the output 115 of 116. Flip-flop 124 indicates that with the 1-state the frame is ended and that the register RM for message transmission to a selection circle JO until Jn is ready (see Fig. 4). The I output of 124 is connected to both the PREU input of TRUMES and the corresponding input 125 of a constituency 126, the circuit of which is identical to that of circuit 29 in FIG. The O output of 124 is also connected to the second input of the UIJD gate 118 connected.

The second input of the OR gate 132 is with the output NACU of TRDi-IE and the third input of 132 with the general Backed her RA3 of the system.

The constituency 126 has as many inputs 125 as register RM exist, i.e., number ρ. An input 125 is energized when the corresponding flip-flop 124 is in the! State, i.e. when the message is framed. There are also ρ corresponding outputs 127 that match the inputs of conventional Control circuit 120 are connected, which can close in a selector SMES. The corresponding intersection of the Registers is picked out by 126. Selector SMES has as many three-wire inputs as there are registers RM and one three-wire output, which is the output line and memory MG to an input 22 of a. Before- . selection switching network (see Fig. 4).

It has been seen that a transceiver TRUMES is provided in connection with a transceiver TRDJ in the selection circuit

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is to control the message transfer between the register RM and the circle J, which in connection with the circle from Fig.7 selected, executes. TRUMES has the inputs PREU, BLOU, RELU and the outputs SYU, SGU, NACD and SBU.

Circle 47, which was already mentioned in connection with the description with FIG. 7, is represented by a rectangle in FIG shown with dashed lines and contains the constituency. 126, the control circuit 128 and the selector SMES, as well as all message transceivers TRUMES of the register RMl to RMp. SYU and SGU as well as exit 113 from 112 are connected to the selector SMES and 22 via three wires correspondingly with SY, SG and BD. SYU is in this case a synchronization input i.e., as in Fig. 5. juxtaposed, the clock is located in the output unit, which is the connected selection circuit J here. exit SBU, as already mentioned, is connected to the third input of circuit 122. Output is NACD from TRUMES connected to the first input of an OR gate 131 which has three inputs, the second of which is connected to the output NACU is connected by TRDME and the third to the general RAZ, the output of which is connected to the reset input the memory logic 116 is connected. Input BLOU is connected to output 114 of 116.

The O input of flip-flop 124 is connected to the output of one OR gate 135 connected, which has three inputs, the first of which with the transmission end output 130 of the logic 116 is connected, the second to the NACD output of TRUMES and the third to the general RAZ. Exit 130 is also

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connected to the RELU input. The O input of the flip-flop 119 is connected to the TRDME ERPU output.

The operation of the circuit of Figure 9 will now be described assuming that register ME1 is empty, circle 100 of MEE has been selected and that the corresponding Crossing point of the selector SMEE is closed. The signaling circuits TRUMEE and TRDME are therefore connected. Output S3D transmits the incremental bits and with Averaging circle 122 it lets the bits enter 111 and the following characters enter 110.

It has already been seen that the output SBP is not energized, if the input circuit MEE decides, immediately none Transferring characters. For the duration of one character, which blocks the operation of 110.

If an error occurs in the character regeneration circuit 68, the input CANU of TRUMEE is marked and output NACU of TRDME is marked, which means that 110 is triggered via the OR gate 131. Since flip-flop 117 has not changed its state, register RMl still remains with the Circle MEE connected to receive the following message.

If there is no error at the end of message recording, output LERU is energized and sets the flip-flop 117 to the O state. RMl is no longer available and 100 searches for another free register. FlipfiLop 119 is in the 1 state. Register RMl is then from everyone external communication is cut off and works independently, the internal clock 120 provides incremental pulses to the

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Circle 122. The message advances to 110 to the right.

When the character DP reaches cell 112, the output 115 is energized and brings flip-flop 124 to the 1 state and closes gate 121. As already mentioned, the autonomously operating memory unit can still be subjected to a refresh. Output 1 of 124 energizes the PREU input of TRUMES and also sends a signal to the corresponding input 125 of the constituency 126. Let us assume that 126 selects an RM circle that differs from Rill. The state of the circle in RMl remains unchanged, except for periodic refreshes of 110. Then we assume that ¹ RMl is chosen. The marking of the input PREU also allows the end of the work of the selection of the selection circle J through 56 and 65 (see Fig. 7). It will be assumed that the selection work determines the storage ΜΞ in Fig. 9.

As soon as the switching matrix 23 is the corresponding crossing point closed, TRUMES is with the transceiver TRJT of the connected selection circle J connected. The TRUMES ERPD output is energized and, on the one hand, locks the multistable circle 45 in Fig. 7 and on the other hand the connection with the selection circle J.

Output SWU, which is located with the clock in J, caused over circuit 122, the output signals of the bits of the character and the Fortsehaltea in 110. Remember s _e i, that when J barrier emits signals, the output of SPC on a

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Character is locked. If during transmission or while waiting, caused by the processing time of the head through circuit J ¹ , unit 110 goes into the refresh condition, its input is energized, which energizes input BLOU and causes the transmission of an inhibit signal to TRDJ. If J sends out a cancellation signal, output NACD is energized, which resets unit 110 via OR gate 131. Output NACD is connected to the O input of flip-flop 124 through gate 135, which triggers the same mode of operation described above for the normal case of a release.

Assume that among the control functions of the register 110 ,, such as triggering the refresh, recognition of the transfer stop etc., the logical unit 116 the characters, that have entered the selection circuit J in 101 during the transmission of the message, to count the release signal, which RELU excites at the end of the penultimate character to trigger.

At the end of the character FP, the ERPD returns to the idle state, which frees the multistable circle 45 in Fig. 7. As soon as 116 has examined that 110 is empty _/ 118 is opened by 133 and allows 117 to pass into the 1 state, whereby register RM in turn enters a call state with respect to circuit MEE.

Instead of a silo type memory and character-by-character memory may use any other suitable type of memory for unit 110 if that one works has adapted control logic.

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FIGS. 10 and 11 represent one of the selection circles JO to Jn in FIG. 4, which are referred to herein as circle J with the associated buffers MT. More precisely, FIG. 10 relates to the input and selection processing circuit of J _f , FIG. 11 relating to the output circuit from J to an output memory MS (see FIG. 4).

As in FIG. 7, the availability circuit 48 with the AND gate 57, whose first input is also found here connected to the output 136 of the buffer MT and its second input to the output of a UNü gate 59 whose first input is connected to the output LERU of the transceiver TRDJ of the control circuit 50 and whose second input is connected to the output LERD of the transceiver TRUJ. Under 48 you can find the multistable circuit 49 and the control circuit 50 with its coder 63 and the transceiver TRDJ.

The intermediate memory MT is identical to that part of the input memory MG which is shown in FIG with;

also fäem constituency 100, the steering committee 101 and the Selector SMEE in Fig. 8. Output 136 of MT corresponds to the input of 100 (not shown in Fig. 8), the is identical to output 43 of Figure 29; that is, it is designed to indicate when memory MT is available if it contains at least one available register. The number of registers in the buffer MT may actually be different from those of the input memories. This is determined by the respective Traffic determined.

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Sendeerapfanger TRDJ exchanges signals with TRUMES (see Fig. 9). You can see the inputs SYD ₇ SGD, PRED, BLOD, CAI-ID and the outputs OLWI-I as well as LERU and the bit synchronization input CLD. From the bit synchronization at the output of the gate 166, a character synchronization signal is supplied at the output SYCH from the bit synchronization at the output of the gate 166 through a divider 129. The PRED input is connected to the multistable circuit 49. The third connecting wire BD is connected to the input of a register 137 which is similar to the REGD.

Register 137 has the storage capacity for at least all control characters of the message up to the last selection character; it works as a shift register. It is assumed that a message can pass through a maximum of 15 switching stages with a single selection counting character CS and 15 selection characters S1 to S15, in addition to the first three DP, L1 and L2, a minimum capacity of 137 are 19 characters. For DP it is useful in the case of a sample message if two selection characters CS are provided, where DP has the value 4 and CS is increased by two at each level, so that the minimum capacity of 35 character cells is «

Output SYCH is connected to the input of a counter 138, the maximum count of which is 4, to which SYCH supplies a signal every time t7 from TRDJ, whereby the symbol synchronization is formed. The counter 138 has five 'outputs 0, 1 ..., 4 _y which are shown in Fig. 10, but instead of showing their direct connections to other circuits, a corresponding number indicates the inputs *

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Counter 138 also contains a blocking signal input connected to the OLBU output and a reset input, which is connected to the LERU output.

The first cell of the register 137 has a four-wire output 139, each wire of which with the corresponding jSix bit cells are connected and have a four-wire output 140, with each wire connected to the corresponding 10th bit cells. Cable 139 is in parallel with the first Inputs of AND gates 141, 142 and 143 connected. Indeed there are four gates 141 ^ but will simplify cable 139 is viewed as a single wire and port 141 as a single port. Same applies for 142, 143 and for the cable L40 too.

The second input of the gate 141 is connected to the output 0 of the counter 138. The output of 141 is with the Decoder 144 connected to the four outputs DPI, DP2, DP3, DP4 corresponding to the four values 1 to 4, which represent the characters can have. Output DPI of 144 is with one Time delay circuit 145 connected, the time constant of which is very large, e.g. on the order of a millisecond, i.e. when output DPI is energized, the output of 145 will remain energized for one millisecond. The output of 145 is connected both to the first input of the OR gate 146 and to the first input of an iiOR gate 147. Of the Output 147 is the first input of an AND gate connected, the second input of which is connected to the 1 output of a Flip-flop 185 is connected, which stores the state of the output DPI and is reset by the output LERU of TRDJ will. The output of 148 is one with the first input

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OR gate 149 connected. The output of 149 is connected to the input CAND of TRDJ. The output DP2 of 144 is connected to the first input of an OR gate 150, which has three inputs. The output of 150 is connected to the 1 input of a flip-flop 165, whose O input is connected to LERU and whose output 1 is connected to the 1st input of an IMD gate 151 connected 1st. DP4 output of 144 is connected to both the second output of an OR gate 150, as is also the wire 152 shown in FIG _o ll. Output DP3 is connected both to the first input of an LWD gate 153 and to the first input of an AND gate 15 4. The second input of gate 154 is connected to cable 140 and its outputs are connected to the input of a decoder 155 »The output of 155 is connected on the one hand to the second input of an OR gate 149 and on the other hand to the input of an inverter 156, the output of which is connected to the second input of an AND gate 153»

Cable 140 and decoder 150 are used to analyze the 10.3 digit P of the character DP when there is a telephone message, i.e. "h" when DP = 3 "As can be seen from the description with reference to FIG. "DP become When DP = is greater by one unit after each pass through the buffer MT 3 and the longed number _g reaches the predetermined value H of DP dansi the output of 155 is energized which the cancellation of: message 149 and CAWD As a result, "In the opposite case, when the output of 155 is not energized, the inverter 156 delivers a signal to the gate 153". The output of 153 is connected to the third input of the OR gate 150.

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The second input of AND gate 142 is the output 3 of the counter 138 connected. The outputs 142 is with connected to the setting input of a binary counter 157, which is used to decode the selection order counting character CS according to Fig.2 is used. The signal output of the counter 157 is actually connected to the output of an AND gate 158, the first input of which is connected to the output 4 of 138 and the second to the output SYCH. If the third character is set at 157, the character synchronization is applied to the value set in 157 was going to count backwards. When the countdown has reached the value 0, the output is from 157 excited, i.e. when the selection character belonging to the current stage is in the first cell of 137 is. Counter 157 also has a blocking signal input which is connected to the output OLBU. Exit 157 is both with the second input of the gate 143 ^ aIs also connected to the second input of the gate 151. The exit of 143 is connected to the input of a decoder 159, which has as many outputs as lines emanate from the switching stage. An excited exit from 159 corresponds to a value of the character S, which is transmitted from the first cell of 137 to the decoder 159, at the time the gate 143 opens. The outputs of the decoder 159 are accordingly with a battery of memory flip-flops shown in FIG. 160. Every energized output of 159 is associated with a flip-flop of 160, which remains energized as long as the output of the inverter 161, which is connected to the O input of the 160 flip-flop and does not emit a signal, the input of 161 is connected to the! output of a flip-flop 162,

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The outputs of the battery 160 are increased accordingly Input of the output memory S in Fig. 4 via the IMD gates 274. only one of which is shown connected

controlled

and are from the 1 output of a flip-flop 273 £ its O input with the output LSRD from TRUJ and its. 1 input is connected to output 170 of register 137. An output 163, which corresponds to the output of 160, is shown to aid the following description of the mode of operation.

The output of the Ui-ID-To res 151 is connected to a time delay circuit 146 _? whose time constant is about 50 microseconds, a time which corresponds to a reasonable waiting time for a free output memory. When the output of circuit 1ό4 is energized, its output remains energized for about 50 microseconds. The output of 164 is connected to the second input of an OR gate 146.

As already mentioned with regard to the circuit TRUjMES in FIG. 9, it is the output circuit TRDJ _f that transmits the synchronization. The clock input CLD is connected to the output of an OR gate 166, the first input of which is connected to the output of a UWD gate 167 and to the output of an AND gate 168

is

connected ^ "The first input of gate 167 is connected to the output of a clock circuit CLJ, which is similar to CL in Fig.5. The second input of 167 is connected to the output of an inverter 169«

The selection circuit J also contains a transceiver TRUJ, which is designed so that it can be used in connection i: JLt a transceiver

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Receiver of the type TRD cooperates, which is accommodated either in the output memory MS or in an associated intermediate memory MT, depending on what the memory is connected to. Circuit TRUJ has the inputs BLOU, SYU, RELU and the outputs ERPD, LERD, SYB ₁ . Output SYD is connected to the first input of an AND gate 168, the second input of which is connected to the output of an OR gate 275, which is also connected to the input of inverter 169. The inputs of the OR gate 275 are correspondingly connected to the output of a UÜD gate 176 and to the I output of a flip-flop 220 in FIG.

The synchronization of the data transfer from the memory ME or MT to circle J is first saved by the clock CLJ, whose output signals pass through 167, da the input of 169 is not energized, through OR gate 166 to CLD. If then circle J with an output memory MS or intermediate memory MT is connected, then the memory clock feeds the circuit TRUJ and the synchronization takes place through the output SYB via the gate 168 opened by ERPD, through the gates 176 and 275 for a memory MT or, as will be seen later, by X for a memory MS. This clock signal is transmitted through gate 166 to the CLD. The input of 169 fed by 275 prevents signals from CLJ from passing through 167 after J has been connected to an MS or MT memory, this memory controls the transfer from ME or MT to J and from J after MS or MT.

The output units of the last cell of 137 are connected to the first input of a UHD port 178, to the input

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a flip-flop 273 and with the input of an IHD gate 221 (see Fig.11) via wire 218. The output 181 of the unit of the penultimate cell of 137 is connected to the 1 input of a Flip-flop 272 which is reset by ERPD from TRUJ and its! output connected to the input BLOD of TRDJ.

The output of the OR gate 146 is with the 1 input of a flip-flop 162 and the first input of an HQR gate 173 connected. The 1 input of a flip-flop 162, on the other hand, becomes connected to the control input of a relay 25, which was already mentioned in Figure 4 and on the other hand with the inverter 161 “Output ERPD is connected to the second Input of a LJOR gate 173 connected, the output with is connected to the O input of a flip-flop 162. The O exit of 162 is with the first input of an AND gate 176, the second input of which is connected to the ERPD output of TRUJ. The ERPD output is also linked to the second input of a HOR gate 167 connected

When Fiipflop 162 is in the! State, the electronic relay 25 is energized and connects the known three veins SYU, SGU and BD ⁹ with its three-wire output 177. When 162 is in the 0 state, the relay 25 is not energized, ijnd SYU, SGU and BD 'are connected to the three-wire output 174, which is connected to the input of the intermediate memory MT.

The output of gate 176 is one with the second input UüD gate 178 connected, the third entrance to the Output of an adder 180 is connected, which is supplied by the tenth output 179 of the last cell of the register 137 adds a tenth value “That means that the

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Gate 178 represents four similar gates. The new value calculated from 180 is reinserted into the last cell of register 137 from 10th input 171 through gates 178. In addition, circuit 180 has a control output which is connected to the input BLOU of TRUJ by OR gate 181 to the input BLOD of TRDJ, a connection only being indicated by part in order to simplify the drawing. Thus, BLOU and BLOD can be aroused during the time of a character to give the circle 180 time to calculate. The other input of the gate 191 is connected to the output of an AND gate 190, one input of which receives the signal “K (see FIG. 11) and the other input of which is connected to the 1 output of 162.

The output LERü from TRDJ is also connected to the trigger input a counter 182 whose signal input 183 receives the symbol synchronization signals from SYCH and whose Output connected to the first input of a UÜD gate 184 is. The second input of 184 is with the O output connected by 162. The output of 182 is also connected to the first input of a gate 186 via wire 175 (see Fig. 11), the second input of which is connected to the first output of 162 via wire 192. Of the The output of 186 is connected to the trigger input of the counter 188 (see Fig. 11) whose signal input 189 the Receives character synchronization from SYCH * that come from divider 129 'and that are identical to 129. Of the Counter 182 has a capacity which is 1 less than that of register 137. The output of the UND gate 184 is connected to the first input of an OR gate 187,

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whose second input is connected to the output 188 via wire 194 and whose output is connected to the input RELO and PRUJ. The memories 182 and 188 are used after the input memory has been released to send the end of the message to the output memory MS or the intermediate memory MT to signal _e

For a description of the circuits illustrated in Figure 10, it is assumed that the Memory ME (see Figure 9) there transmitted message which is illustrated in Figure 2 _e, and that the first stage in Fig Cl l ^ includes the selection circuit.

At the time 0 of the counter 138 the character DP is in the first cell of the register 137 and has a unit number with the value 3 and a tenth number with the value 0 “The unit number of the value 3 is transmitted via wire 139 to port 141 and in the Circle 144 decoded, the output DP3 of which is marked _o The value O of the tenth digit is transmitted through gate 154 and decoded in 155. If 0 is less than η, then the output of 155 is de-energized and the output of inverter 156 is energized, thereby opening gate 153. The output of the OR gate 150 is energized and flip-flop 165 changes its state, marking the end of the decoding of the character DP. The O output of 138 can be connected to the output buffer BLOD by a length delay in order to ensure that these various processing steps can take longer than the time required to transmit a character to delay the transmission of Ll rna a character «

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The following characters LL and L2 of the one shown in Fig.2 Message blocks are received and stored in memory 137 stored. Then becomes the selection order count CS received with counter 138 in position 3. gate

142 is open and the unit number of PS is in the Counter 157, i.e. in this room. 1. When the counter 138 changes position 4, the contents of the counter become counted down and as soon as the counter has reached 0, in this case immediately, the output of 157 is energized. It should be emphasized that the blocking input of the two counters 138 and 157 is connected to the OLBU output because they do not have to continue in the event of a block.

The following character S1 is then processed. This concerns the first stage through which the message went. gate

143 is open and the unit number of S1 is decoded in decoder 159. In addition, the outputs from and the flip-flop 165 energizes the time delay circuit 164 through the AND gate 151. The 1 state, which corresponds to the position of the selection circle J, which is used to search for a connection, goes through the OR gate 146 and flip-flop 162 Output memory MS provided by the selection character S1 is. The 1 output of 162 cancels the output of inverter 161, causing flip-flop from works accordingly with Sl. Assume that the marked flip-flop of 160 belongs to wire 163? i.e. if Sl = 7 is that the 7th flip-flop and wire 163 run through gate 274 to memory MS7. However, core 163 becomes like this long not energized until the corresponding gate 274 of flip-flop 273 is opened, whereby the 1 state is assumed as soon as output 170 of the arrival of the characters DP in

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the last cell of 137 was excited, the! output of 162 has excited the electronic relay 25, which connects the wires SYU, SGU and BD "with wire 177, which runs in Fig, II. The wire 163 is with the input of a constituency of the input circle of the output memory MS7; this constituency corresponds to the circle 29 of FIG. 6, which was described in connection with FIG Reasons; another message that comes from another selection circuit is transferred to memory MS7 ^ or all other registers of memory MS7 are occupied.In addition, it is not certain that if several selection circuits call memory MS7 at the same time, as shown in 10. It is therefore planned that the selection circuit will be maintained in the state in which it was for a predetermined time; The purpose of the flip-flop 162 is to keep the! State fed to the inverter 161, the time delay circuit 164 sending a signal to the HQR gate 173 via 146 _o The side constant of 164 _e, for example 50 microseconds, was chosen long enough to be at least one Make the selection in the output memory but short enough not to occupy the input memory ^ which continues to receive other messages »

During the waiting time of 50 microseconds. moves the input storage tank with the transfer of the characters to the selection circle ο Several BJpossible cases are described below? 1 »Sign DP has not reached the last rope of 137 Output 170 not energized, not even wire 163. In the 2-cell register 195 in FIG. 11, the one with 137 via wire

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B ^{1 are} connected, no characters occur and the flip-flop 220, whose 1 input is connected to the de-energized unit output of the second cell, remains in the 0 state. Output X is therefore not energized and the OR gate 275 does not energize the gate 16 8 either, but leaves gate 167 open, which enables the character transfer to the register 137 using the clock signals CLJ, 2nd DB reaches the penultimate cell of 137. Output 181 is then energized, causing flip-flop 272 to change state, and output ERPD of TRUJ, which is not in contact with other transceivers, is not energized. The signal from 272 at the input BLOD of TRDJ allows TRDJ to block after the transmission of the following characters. Character DP then gets into the last cell of 137. 3. Character DP reaches the last cell of 137. Output 170 is energized while adder 180 adds one to the 10th digit of DP. The flip-flop 273 changes to the 1 state, as a result of which wire 163 is excited. The wire 163 connected to an input of the input circuit of the constituency of MS7 allows the possible selection of the described selection circuit in MS7. 3.1 As soon as the choice has been made in favor of this selection circuit in the switching matrix 27 (see FIG. 4), the transceiver TRUJ is connected to the transceiver TRDMS of a register MS7 and output ERPD is then excited and signals the output presence. 272 suppresses the blocking signal at the input BLOD of TRDJ. The second input of NOR gate 173 is energized and flip-flop 162 is held in the 1 state, thereby maintaining battery 160 and energizing 163. In addition, gate 16 8 remains closed and the blocking input BLOU from TRUJ remains energized at 190 and 191.

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This means that no characters can be transmitted from MS7 to TRDIIS. Controlled by the clock CLJ, however, characters get from the input memory to 137 and from there to the register (see FIG. 11), namely during the transmission time of the first two characters. As soon as DP has reached the last cell of 195, flip-flop 220 changes to the 1 state and supplies the signal X. This opens gate 168 and ~ X suppresses the blocking signal at the input BLOU of TRUJ. Under these conditions, the control characters and then the packet characters from the input memory to the output memory MS7, the control being carried out by the clock synchronization of the register MS7, through output SYB and gate 168 provided with relays. Only subordinate hold commands in the selection circle adapt the message header to a new selection in the following stage C2 (see FIG. 1), as will be described in connection with FIG. The circuit TRUJ must remain blocked until DP has reached the second cell of 195 in order to prevent the memory MS7 from accepting invalid characters before the arrival of DP,

3.2 The selection of the output circuit does not take place before the end of the side delay circuit 164. Flip-flop 272 remains in the 1 state and at the end of the time delay the output signal from 164 which is applied through 146 to the first input of NOR gate 173 disappears. Since the other input of 173 is not energized by ERPD, gate 173 causes flip-flop 162 to return to the 0 state. The control input of the electronic relay 25 is no longer excited and drops out, as a result of which the wire SYU, SGU and BD ^{1 are} connected to wire 174, which belong to the associated buffer store MT, while those coming from gate 190

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Blocking signal can be suppressed. The inverter is no longer energized and provides the flip-flop battery 160 back to 0. Because of this, output 163 is no longer energized and the circuit no longer calls memory HS7. Since the intermediate storage HT is available as required (otherwise the chain between ME and J cannot be established), the ERPD output is activated immediately excited. The state of flip-flop 162 is not affected. On the other hand, gate 178 is through the open gate 176 opened and the adder 180 transfers the tenth to increase the digit from DP to the last cell of 137 to indicate that the message is once in a buffer MT was directed - originally it was assumed - that the tenth digit is 0 -. then The message runs without interruption with the exception of the blocking in the ME or MT register for refreshment, as shown above. This transfer runs uncontrolled by the clock MT through SYB, since gate 176 via 275 the Gate 168 has opened. At the end of the message, memory ME sends the release signal, which is received in LERU, thereby triggering counter 182 when character FP reaches the last cell of 137. Since the second entrance with is connected to the O output of the flip-flop 162, arrives a signal to open gate 184. The signal passes through OR gate 187 and energizes RELU in TRUJ thereby enabling the memory MT and the selection circuit takes place as soon as FP has been transferred. All memories are reset to O, as soon as output 136 of MT is excited, the initial state is reached again.

It should be noted that as soon as the message output from Selection circle begins the circles TRDJ and TRUJ tandeia-

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work wisely, for example with the blocking output OLBD from TRUJ, not shown, which is connected to the blocking output BLOD from TRDJ. This happens regardless of what the memory is connected to, whether with output or buffer. In fact, a blocking decision in the output memory should not only be transmitted to the selection circuit, but also to the input memory. To this end, the connections between the transceivers of J could be designed like those provided between CLJ and SYB for synchronization transfer, using the necessary logic circuits. Another possible case is briefly described below, depending on different values of the start characters DPr a) DP has the value 3, but the message does not come from the input memory, but from the buffer memory. The 10th digit decoded by the 155 is less than W and processing continues as above. It may also be that the tenth digit equals N, the output of 155 is energized, and the cancellation input CAND is energized. The contents of 137 are dispatched as well as those of the buffer register from which the message comes . The freed selection circuit is ready to receive further messages, b) DP has the value 1. Output DPI of 144 is energized, whereby the output of circuit 145 is energized for a long time interval of about one millisecond. The output of 145 energizes the output of the OR gate 146, whereby the flip-flop 162 is brought to the 1 state. The selection of an output of the battery 160 takes place as described above. If the choice of a selection circuit from the memory MS

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occurs during the delay time of 155, flip-flop 162 remains in the! state and the rest of the processing takes place as described above. If the selection is not made in a timely manner, none of the NOR gates 147 will be marked. 147 transmits a signal passing through the open AND gate 148 and the OR gate 149 to produce the input signal CAND to cancel. The input memory and selection circuit are released. One recognizes from this that a hasty Message for which DP = 1 can never pass through a buffer; if no output for a millisecond is available, sign of abnormal operation of the outgoing line, the message is canceled. c) DP. has the value 2 or 4. After decoding one of these values by 144, the output becomes DP2 or DP4 marked. In the part of the selection circle shown in Fig. 10, the rest of the processing in 1 to 3.2 continued. It can be seen, however, that output DP4 is connected via wire 152 to that part of the selection circuit which in Fig.11 it is shown where the messages of type 4 are transmitted to an output memory of a special Treatment. The working method of the selection circle at the end of a message has already been described, when this is transferred to a buffer. The case will be described later with reference to FIG is transferred to an output memory.

In Fig. 11 the circles of the selection circle J are shown, which are used when messages leave the circuit for transmission to an output memory, - Regarding of the circles in Fig. 10, we assume that flip-flop 162 is in the 1 state and the ERPD output of TRUJ is excited,

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to explain the operation of the circles in FIG can.

The three wires of the cable 177 are again separated, SY and SG are simply extended, while the wire · BD ^{1 is} connected to the input of the register 195, which has two cells. The 10th output 197 of the first cell of 195 is connected to the first input of an AND gate 196, the output of which is connected to the input of the memory 198. It should be noted that output 197 is a four-wire cable, that there are four ports 196, and that memory 198 can be a set of four flip-flops. The output of the memory 198 is connected to the first input of a UUD gate 199. The output of the gate 199 is connected both to the first input of an OR gate 200 and to the unit input 201 of the first cell of FIG.

The unit output 202 of the first cell of 195 is with connected to the first input of an AND gate 203 and to the first input of a UI-JD gate 204. The output of gate 203 is connected to the second input of an OR gate 200. The exit of gate 204 is on the one hand connected to the input of an adder 205, which increases the value attached to it by 1 and, on the other hand, with the input of a UHD gate 206 and finally with the first input of an AND gate 207. The output of the gate 206 is connected to the input of an adder 208, the output of which is connected to the fourth input of the OR gate connected is. The output of gate 207 is connected to the input of an adder 209, the output of which is connected to

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the third input of the OR gate 200 is connected. the Adding stage 208 can add 2 to the value attached to it, whereas adding stage 209 adds 1. The exit the gate 200 is connected to the input of a redundancy generator circuit 210, the 10th digit of a Character is calculated according to the unit number which is at its input. This circle 210 is known and is not further described here. The output of 210 is with the 10th input 211 of the second cable of tied together.

A five-digit counter 212 is also provided which is similar to counter 138 in FIG. The trigger input of the counter 212 is connected to the output of an UltfD gate 221, the first input of which is connected to the ERPD output of TRUJ via wire 193 and the second input of which is connected to the unit output of the last cell of 137 via wire 218. The Signal input of counter 212 is connected to the output of an AND gate 213, whose first input is connected to the 1 output of flip-flop 162 via wire 192 in FIG. 10 and whose second input is connected to output SYCH ^{1 of} the character synchronization circuit via wire 217 is.

The output of gate 213 is also connected to the second input of a ÜJID gate 214, which has three inputs connected, whose first input is connected to the output 4 of the counter 212 and whose third input is connected to connected to output DP4 of 144 in FIG. 10 via wire 152 is. The output of 214 is connected to the signal input of the setting counter 215. The setting input of 215 is connected to the output of the adder 205 and

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whose exit is rait the second entrance of the gate tied together.

Wire 152 is also connected to the second input of gate 206 and to the input of an inverter 216, whose Output is connected to the second input of the gate 207.

Gate 186 and counter 188 are shown in connection with FIG has already been mentioned. One output of gate 186 is connected to wire 192, while the other input is connected to Wire 175 is connected, with which the connection to the output of the counter 182 is established.

The second input of gate 196 is with the O output of 212 and to the second input of gate 203. The second input of gate 2O4 is to the output 3 of 212 connected. The output of the second cell of 195 forms together with the wires SY and SG the cable 26, which goes to the selection matrix 27 in Figure 4.

The output of the adder 208 is also connected to the first input of an OR gate 223, whose second input is connected to the output of the adder 209 and the output of unit digits input 222 of the last cell is connected from the 195th

The unit digit output of the last cell of 195 is connected to the 1 input of flip-flop 220. It has already been said that this flip-flop would prevent the memory MS7 from being stored before the character DP the

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last cell of 195 has reached. The circuit 210 as well as the adding stages 208 and 209 each have a control output, which is connected in a suitable manner to the input BLOU of PRUJ in FIG. 10 via the OR gate 191.

As soon as the character DP is the last cell of 137 in Fig.10 has reached and the selector J from the output memory MS7 would be selected, the message can go through register 195 to MS7. At the same time, the gate 221 is on the Wires 193 and 218 open, which triggers the counter 212, which receives the character synchronization signals from SYCH * receives since flip-flop 162 is in the 1 state. if 212 is 0, DP is in the first cell of 195 and it is known that this character DP then consists of a unit number which indicates the type of the message and that this message running through J was not modified, while the tenth digit is the number of cache runs of the level concerned.

At time 0, the unit number is applied to the redundancy generator circuit 210 via AND gate 203 and OR gate 200, who calculates a new tenth digit that goes into the second cell of 195 in its place. In case that more time than one character requires, Kreis blocks the transmission through 191 to MS7 and BLOU. At the same At time 0, the tenth digit of the first cell arrives in memory 198 through AND gate 196.

It should also be noted that as long as DP is not the second cell of 195, flip-flop 220 via Y 190 and 191 emits a blocking signal. This is required so

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the registers of the memory MS7 do not contain any incorrect characters save before the DP arrives.

At times 1 and 2 of 212, the successive arrival of L1 and L2 in the first cell of 195, takes place after their transfer MS7 nothing.

At time 3 of 212, the gate 204 is open and the unit digit of the selection order number CS is taken from the first cell of 195 transmitted. "Depending on whether the character DP of the message has the value 4 or not, two cases are possible, which are described below:

1st DP does not have the "fourth 4th wire 152, which is connected to 144 is not energized and the inverter 216 opens the gate 207. The unit digit of CS is fed to the adder 209, which adds 1 to the exact selection in the following Level to enable and gives the new value to the circle 210 over 200. In addition, the new value occurs the gate 223 as a unit number in the second cell of 195, Since the addition requires a certain time, the Adding stages 208 and 209 with suitable blocking outputs Mistake. The new tenth of 210 then takes the place after the CS unit number.

2. DP has the value 4. Wire 152 is then energized and opens gate 206. The CS unit digit then becomes the adder stage 208 fed which adds two and the. lets the new digit enter the second cell of 195, this happens

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over 223 and 222. The circle 210 also calculates the new one tenth digit. In addition, the adder 205, which adds 1, is supplied with the CS unit number and the calculated Value set in counter 215. It should be noted that this setting takes place even when DP does a has a value deviating from 4 without disturbing the operation. At time 4 of 212 the gate 214 is through the energized wire 152 is open and the counter 215 receives the character synchronization from 213. When the count of 215 is O, then the character that corresponds to the level selection character to be found directly in the first cell of 195; Gate 199 follows through the output signal of 215 opened as well as by the output signal 4 of 212. The number P which has entered the memory 193 becomes placed in the first cell of 195 instead of the unit digit. In addition, the number P over 200 is used for the calculation the tenth digit nabh 210. The number is found behind the selection characters belonging to the level of cache passes and thus the quality of service as a function of traffic.

At the end of the message, register 182 in FIG a signal to wire 175 and the open gate 186 triggers the counter, which counts up to two, before it gives a signal via 194 to the OR gate 187, which is connected to the input RELU. Gate 184 is closed because flip-flop 162 is in the 1 state. the Release is then carried out in the manner described above. It should be noted that counter 188 also has a lock input through has connected a line not shown to the output OLBD of TRUJ.

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It should also be noted that counters 138 and 212 remain in position 4 until selection circle J is complete is reset to O after being released.

12 shows the input circuit of an output pexcher MS and the register memories Rid'l to RM'p 'of this memory. However, only part of this register is shown; the supplementary part is shown in FIG better understanding of the description should be placed directly to the right of Fig. 12. More precisely, Fig.12 the output memory MS7 to which the signals of the Selection wire 163, which is from the selection circuit of Fig, IO and 11 come, were headed.

The HS input circuit contains a first constituency 225, a second constituency 226, a coder 227, an AND gate 228 with three inputs, a control circuit 229 and a selector SI4SE. The memory MS itself contains a register memory set RM ¹ I to RM'p ¹ . Each register RM ¹ is practically identical to each register RM of an input memory ME or an intermediate memory MT. Consequently, the ^{circles contained in register RM 1} I have the same reference numerals as in FIG.

The first constituency 225 is the same as constituency 29 in FIG. It contains the inputs such as 163, i.e. the inputs with the corresponding selection veins of the SelekidonskiöLses Jl to Jn are connected. If a selection circuit is selected, then one of the wires 230 at the input of the coder marked. The outputs of 227 are with the corresponding

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Entrances to Ui ID gates 218, only one of which is shown is connected.

The second constituency 226 is also the same as the district 29 shown in FIG. It contains the inputs, such as 231, which are correspondingly connected to the available flip-flops 117 of the registers RM ¹ , outputs such as 232, which control the associated circuit 229 and an output 233, which signals that the selection was made in 226, ie that one of the registers RM * can receive a message.

As already mentioned, the outputs of 227 are connected to the first inputs of the gates 228. The output 233 is with connected to the second input of these gates 228, while their third input is connected to a circuit 235 via wire 234 (see Fig. 13) is connected, which can indicate that the outgoing connection line is in a ready-to-send state to the next switching level. The outputs of the gates 228 are connected to the control inputs of the control circuit CCS of the Selection switching matrix 27 connected. Circle CCS is identical to circle CCP in FIG. When CCS works, it closes Circle 27 is a three-wire crossing point to connect a selection circle J to the input of the selector SMSE.

The outputs of the SMSE selector are connected to the corresponding RM ¹ registers. In each register, such as in RIl ¹ I, we again find a memory unit 110 with an input cell 111 and an output cell 112 the associated memory logic 116 an output transceiver TRDMS that works with TRUJ, available circuits the flip

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flops 117 included, as well as AND gate 180 and empty storage unit identifier 133, bit synchronization circuit with clock generator 120 and finally the control circuits of the unit 110, the the circle 122 and the OR gate 131 contain. Wire 130 is excited as soon as a data transfer has taken place. Wire 115 is energized as soon as the frame is finished.

The circles just mentioned are useful when the message is requested to enter a register RiI ^{1 of} the output memory. This is different with the memory input circuit in FIG. 9: the internal clock generator 120 is used to synchronize the circuits TRDMES in FIG. 12 and by TRUJ of FIG. 10, so that the messages reach 110, which allows the flip-flop 199 to eliminate them.

Assume that the constituency. 225 selects the output wire, ie to serve the call transmitted by the selection circuit in FIGS. In addition, it is assumed that register RM ¹ I is free and that this was selected by the constituency 226, the output 233 of which is marked. Finally, it is assumed that the outgoing line is working properly and that wire 234 is therefore marked. In SMSE the three-wire crossing point is ^{closed according to RM 1} I and in the selection switching network 27 the circle CCS excited by the gates 228 has closed the matching crossing point. It should be noted that constituencies 225 and 226 can work independently in parallel. In terms of time, as soon as the second choice has been made, the transmission can take place without any loss of time.

The message input synchronized by clock 120 in unit 110 follows the autonomously operating register RM ',

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which frames the message, i.e. that the character DP appears in cell 112 of 110. This mode of operation has already been described in connection with the input memory in Fig. 9 and it is unnecessary to describe it here to repeat.

The sending of the message from the register to the outgoing line will now be described with reference to FIG.

On the left in Fig. 13 you can see the output circuits of eLne's memory as in Fig. 9. ^{The registers RM 1} I to RM'p ¹ of FIG. 12 can also be seen, each of which has an output transceiver TRUMSS, which is similar to the TRUi-IES in FIG. 9, the output selection circuit 126, the control circuit 128 and the selector SHSS, de .r is similar to SMES in FIG.

Noteworthy differences of this circle from Fig. 9 concern the lines coming from the connections PREU and ERPD from TRUMSS (not shown in Fig. 13) and which is routed in Fig.9 to the OR gates 65 and 64 of Fig.7 to ensure the preselection selection, which is not required here.

The circles belonging to the outgoing line to the next Stage, in this case line 11 in Fig.l, mainly contain an output transceiver TRLS which exchanges signals with TRUMSS, two registers 236 and 237, character sources with the value 15, such as 238 and 239, a source 240 for characters of the fourth O, a test circle 235 and a certain number of logical circles,

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The transceiver TRDLS contains the inputs SYD, SGD, CLD, which is connected to the clock generator CLS, as well as the input BLOD and the outputs LERU, ERPU and SBDy die other inputs and outputs are not shown. The frequency of the clock CLS corresponds to that of iJ line transmission line 11; the frequency is certainly lower than that of the clock generator used to transfer messages can be used within the stage. Output SBD is connected to the various registers, for which bit synchronization is required, such as 236 and 237 and sources 238 to 240, whose Bits need to be extracted in bit synchronization; to simplify the drawing, these are connections not shown. Output SBD is also connected to a divider 241 which provides the character synchronization, especially at the input of a 16-digit character counter 242, i.e. it can count from 0 to 15. Each register 236 or 237 can have a frame of 16 Store character stores such as any of the frames shown in Figure 3. The frame, however, which is a message stop sign FP is stored in 236 or 237 with a synchronization character 15, but not with a synchronization character which indicates the rank of the character FP. Like a synchronization sign with a different Value is entered is shown below. The inputs of registers 236 and 237 are correspondingly connected to the outputs of an electronic relay 243, its individual input with the output of an OR gate 244 is connected, which has three inputs. The outputs of the registers are connected to the corresponding inputs

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connected to an electronic relay 245, its single output with the first input of a UHD gate

246 is connected, which has two inputs. The states of the electronic relays 243 and 245 are controlled so that when the output of the OR gate 244 is over 243 is connected to the input of 236, then the output of 237 via 245 to the input of 236, then is the output from 237 through 245 with dsm input from 246 connected and vice versa. In other words, when register 236 is full, register 237 unloads and vice versa. The state change of the electronic relays 243 and takes place simultaneously, controlled by a control line

247 at the output 248 of the counter 242, which is energized when the counter is in position 15.

Sources 238 to 24O are non-erasable memories that the characters they contain are transmitted when their inputs are controlled by the bit synchronization supplied by SBD gets excited. In this way the input of the source 238 is connected to the 1 output of the flip-flop 249, whose 1 input is connected to the LERU output and the O input to the ERPU output. The exit of 238 is connected to the first input of an AND gate 250, which has two inputs. The entrance from source 239 is connected to output 248 of 242 and its output to the first input of an electronic relay 251. The input of the source 240 is with the output of

248 of 242 connected and its output to the second input of an electronic relay 251, the output of is connected to the first input of an OR gate 244.

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The control input of the electronic relay 251 is connected to the ERPU output, which when energized connects the output of 239 to the output of 251 , and when not energized XSt ₁ connects the output of 24O to the output 251 »All of Characters transmitted to sources 238-240 are self-correcting. The output of the AND gate 250 is connected to the second input of the OR gate 244 “The third input of this OR gate is connected to the wire BD of SMSS. This OR gate can pass post data characters coming from registers RM'1 to RM'p ⁹ or also pad characters from the source

238 or synchronization characters coming from the source

239 or 240 come _β The second input of the UNDr gate is connected to the output of an inverter 252, the input of which is connected to the output 243 of 242.

The counter 242 also contains an output 253 which is connected to the first input of an AND gate 254, which has two inputs, and a further output 255 which is connected to the O input of a flip-flop 256 . The line 253 is practically a multi-core cable; there are as many UlflD gates 254 as there are veins in 253; this line allows the contents of the counter to be transmitted through the gates 254 to a memory circuit 257, the inputs of which are connected to the outputs of the gates 254. Output 255 is excited when the content of counter 242 = 1. Circle 257 is used to record the counter content 242 and to convert this content into a self-correcting character which is provided at the output which is connected to the first input of an AND gate 253. The 1 input of flip-flop 256 is connected to the LERU output

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the j. during its 1-output rait the first input one AND gate 259 is connected, which has two inputs. The second input of 259 is connected to the output 248 of 242 and the output of this flip-flop is connected to the second Input of AND gate 258 and the input of an inverter 260. The output of 260 is with the second input of the AND gate 246, the output of which is connected to the first input of an OR gate 261. Of the The second input of 261 is connected to the output of a gate 258. The output of 261 is connected to the input of a Data transmitter 262 connected, the output of which is connected to line 11.

In order to illustrate the operation of the output line in FIG. 13, it is assumed that the frames shown in FIG. 3 are transmitted on line 11, which means that this message contains these frames stored, for example in register RM ¹ I and that the other registers RM'2 to RM'p "are empty.

Before the message in RM ¹ I is framed, the selector SMSS and register 236 are decoupled, the latter containing the 16 characters of the first line. The ERPU output of TRDLS is not energized and flip-flop 249 has remained in the 1 state since the LERU output was last energized. It is also assumed that counter 242 is in position 15. The output of the source 214 is connected to the first input of an OR gate 244 through 251, flip-flop 256 is in the 0 state, whereby AND gate 259 is closed and via 260

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AND gate 246 is opened.

At this moment 15 of 242 line 247 switches the registers 236 and 237, The output of 236 is connected to 246 and 251st Therefore transmitter 262 "transmits the characters from 236 to 11. The input of 237 is connected to 244 via 243. The first character to enter 237 comes from source 214, which is energized by 248. On the other hand, source 238 transmits since port 215 through 2.52 is closed, no characters after 244, In this way 237 receives the synchronization character O from the second line. As soon as 242 changes to the O position, the source 214 is no longer excited and gate 215 is open, 237 then becomes the first eight pad characters 15 coming from source 238 are received.

At the ninth character of the second line, it is assumed that the message has been ^{framed in RIi 1} I, that the selection of RM ¹ I has been made in 126, that selector SMSS has been connected , and that output ERPU has been energized. 249 therefore switches flip-flop between the ninth and tenth characters in the O to stand, is canceled so that the excitation of the source 238 and the electronic relay changes its state 251 and connects source 239th The first character DP enters through BD, 244 and 243 in 237, followed by the other messages showing the second line,

When the counter 242 is again in position 15 , the input BLOD is energized, whereby the transmission in RM ¹ I for the page of a character is blocked. In addition, the line switches

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247 the electronic relays 243 and 245. Register 236 is empty and register 237 contains the entire second line in Fig. 3. Source 239 supplies the first synchronization signal 15 of the third line to register 236, counter 214 advances and the characters of the third line in Fig. 2 are in 236 saved while 237 through 245, 246, 261 and 262 after 11 unloads. The mediations, stores and transfers are then continued without changing the state of the circle in Fig. 13.

Consider now the memory and then the transmission of the last frame in Fig. 3.

In terms of memory, this frame is stored, e.g. in 236 up to the eleventh character as before; i.e., the first character is a synchronization character 15 and the following eleven are message characters, output LERU is energized and ERPU is no longer energized, causing flip-flop 249 to go to the 1 state and flip-flop 256 as well the 1 state. Gate 254 is closed and circle 257 contains position data from 242 before RELU was energized and is ready to output a self-correcting synchronization character of the value 11 at its output, source sends padding characters to 236 with the value 15, the first of which is the character FP.

When the counter 242 has reached its value 15, gate 25O is open, the source 240 is connected to 244, thus a synchronization character 0 can enter 237, but gate 259 is closed. The result is ^ the gate 246 through In verter 260 is closed and gate 258 is opened,

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so that the output of 257 through 258, 261 and 262 with line 11 is connected. This way, the sync sign becomes with the value 15, which was stored in 236, is not transmitted, but it is replaced by the synchronization character with the value 11, whereby the location of the message stop character FP is displayed. As soon When counter 242 leaves position 15, gates 258 and 246 return to their previous conditions and the The remainder of the last frame in Fig. 3 is transmitted as usual. When counter 242 is back at position 1, Flip-flop 256 changes to the 0 state and the circles to Fig. 13 go back to their original state, as at the beginning of the description of the operation, the outgoing Management.

The above description has shown how a message with reference to FIGS. 4 to 13 in the transmission system according to the invention a switching stage in the network goes through, with reference to Figure 2 and Figure 3, how a message is formed and based on Fig.l, how a network can be constructed.

It was assumed that in Fig.l the terminals of the system only include telephone and telegraph equipment, but it is obvious that other terminals are conceivable, in particular data processing units of the known. Electronic Telephone Operator Type · A way of working a system with such a processing unit could then look like this? picking up the receiver at the calling station, the transmission of a call message to the terminal causes the processing unit,

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which assumes that the terminal has the message head in the Contains memory, bringing a message to a processing facility can be transferred. The message can then take on a special value that includes the character CH (see Fig. 2) and indicates that the device is calling and the identifier of the called device follows, The processing system sees the receipt of the call message on the basis of this identifier, a head with an incorrect request to the calling device. The calling device then sends a dial message to the processing system, which is looking for a route to the status of the called device to consider, as well as two routes that are in one direction and the other between calling and called device is used. If the called party is not free, the system sends an express message to the calling device. If the called device is free and answers, then the system sends the head to both devices, which must be used for the entire duration of the call. The processing of the message in the terminals can be determined by the different values of the character CH during the signaling exchange. The conversation is released in a similar way. The hang-up on a device transmits a hang-up signal to the processing system, which then sends the request to the other device to hang up or as usual Busy signal.

It should be noted that, in some cases, the calls are direct between two devices without the involvement of the processing plant be built up when two devices with end devices

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are equipped that have stored the necessary head to reach the other device. It should be noted that in very large capacity systems there are various processing facilities can be used, which can then exchange service to messages with one another, for example DP then has the value 1, as is generally the case for all signaling messages.

The number of inputs and outputs of a switching stage can be varied to any concentrations or to allow extensions, as well as any number of elementary registers per input, output and Buffers, as well as any number of buffers determined by the traffic.

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Claims (10)

J.H. Dejean - 23 Claims ί / System for the switching and transmission of digital messages over a tiered switching network connected by digital channels, at; which the messages are combined into message blocks, which are preceded by a message header and each message block is forwarded from an input to an output channel when passing through a switching stage, characterized in that the message header contains as many selection characters as verification stages (C) must be passed through, whereby each individual selection character belongs to a single switching stage (C) to be passed through and contains an address (S) which corresponds to the output channel to be passed through, so that each switching stage (C) contains a selection circuit (J) that corresponds to its own switching stage (C) The associated selection character recognizes that means are provided which route the message block to the output channel according to the address (S) in the recognized selection character, 2. System according to claim 1, characterized in that the selection characters are accommodated in the order of the switching stages (C) to be passed through in the message header together with a switching stage ordinal count. (CS), which initially has a predetermined value which indicates the position of the first selection character in the message header corresponding to the first switching stage (C) to be passed through and whose value is increased by one counting unit when passing through each switching stage (C), 509811/1018 J.H. Dejean - 23 3. System according to claim 1, characterized in that in each switching stage (C) each incoming channel is connected to an input (E) of an input memory (ME) and each outgoing channel is connected to an output (S) of an output memory (14S) that a pre se lek t ionskoppe 1 field (23) is provided, through which each selection circle (J) with all or part of the outputs, the inputs Selection r output memory (ME) can be connected, as well as a switching matrix (27), through which each selection circuit (J) is connected to all inputs of the output memory (MS) can that each selection area (J) contains a preselection control area (CCP), which via the preselection coupling * * field (23) the free selection circle (J) with a ready-to-transmit Input memory (ME) can connect that a control device for the transmission.between the Input memory (ME) and the Selektioriskreis (J) provided is that selection means (CCS) are provided which, if suitable selection characters have been recognized, via the selection switching matrix (27) with the free output memory (MS) of the output channel identified by the selection symbol, with an input priority circle Double connections between selection circuit (J) and input storage (ME) and an output priority circle, double connections between selection circles (J) and output memories (MS) prevents 4. System according to claim 3, characterized in that the input and output memories are elementary memories of the same type, each of which has both an input (MEE) and an output circuit (14ES), the former having access to the inputs and the latter to the outputs of the 509811/1018,. J.H. Dejean - 23 Input (ME) and output memory (MS) and that each calling input circuit (i-IEE) with empty elementary memory and each calling output circuit (MES) with message blocks entering the elementary memory a specific one Position attains that an input control circuit of the input or output memory for selecting and connecting a calling input circuit (MEE) with the input of the input or output memory and an output control circuit of the input or output viewer is provided to a calling Select the output circuit (MES) and add it to the output of the input or output memory Has position circle, each of which has arrived in an elementary memory message block in the specific position can bring 5. System according to claim 4, characterized in that the elementary memories from the position circuit are clock-controlled shift registers and that a first bit entered into the shift register (eg 137) has been brought into the specific position when it has assumed the last position in the shift register, 6. System according to claim 3, 4, or 5, characterized in that each selection circuit (J) has an elementary memory functioning as a buffer (MT), the input of which is connected to the selection circuit (J) and the output of which is connected to the preselection switching network (23) is when matching header characters have been recognized and the selection circle (J) is not connected to the corresponding output memory (MS) after a specified time interval. 509811/1018 J.H. Dejean - 23 7. System according to claim 3, 4, 5 or 6, characterized in that the message header in front of the switching stage order counter (CS) contains a message class character (DD) and a number ^ which indicates the number of buffer passes, the selection circle ( J) analyzes the message class character (DD) and compares it with the number of intermediate storage passes and has a decision circuit which can modify the header and increases the counting character by one in an adder stage (205, 209) after each buffer pass, 8. System according to claim 7, characterized in that the message class character (DP) can assume four discrete values, the first value of which prevents the selection circuit (J) from dropping a message block to the buffer, the second value of which is the comparison of the analyzed message class. Character (DP) with the counting character prevents the third value of which, when the selection circuit (J) is connected to the selected output memory (MS), transfers the counting characters to a predetermined position corresponding to the selection level (J) and the fourth value of which is the highest permissible Counting character, whereupon the message block is canceled. 9. System according to claim 8, characterized in that message blocks with the message class character (DP) of the third value are of the type of official message blocks whose successive selection characters are separated by two instead of one character and their switching level ordinal count characters (CS) and at each Passing through a switching stage in an adding stage (208) increased by two counting units is written into a free space between two selection characters, 509811/1018 J.H. Dejean - 23 10. System according to one of the preceding claims, characterized in that a plurality of terminals (2,3,6,7; telephones, teleprinters and data processing systems) is provided, wherein- "an off-hook" with a calling device a call message to a predetermined one Terminal of the processing system is transmitted that the calling terminal (e.g. 2) inserts a message header, which belongs to the called terminal and which contains its own identifier (I), in front of the call message, that the processing system is essentially like a central telephone computer works (dial request, dialing character reception, possible start of a call with a processing system serving the called terminal device (e.g. 3), waiting for availability of the called terminal device (e.g. 3), etc., which searches for a route to the called device as soon as the called device (e.g. 3) is lifted, the message header of the called device (e.g. 3) to the calling device (e.g.2) and the message header of the calling device to called device. 50981 1/1018