DE2420663B2 - REGENERATING AND EVALUATING CIRCUIT AND PROCESS FOR THEIR PRODUCTION - Google Patents
REGENERATING AND EVALUATING CIRCUIT AND PROCESS FOR THEIR PRODUCTIONInfo
- Publication number
- DE2420663B2 DE2420663B2 DE19742420663 DE2420663A DE2420663B2 DE 2420663 B2 DE2420663 B2 DE 2420663B2 DE 19742420663 DE19742420663 DE 19742420663 DE 2420663 A DE2420663 A DE 2420663A DE 2420663 B2 DE2420663 B2 DE 2420663B2
- Authority
- DE
- Germany
- Prior art keywords
- transistors
- regeneration
- evaluation circuit
- transistor
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
- H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356086—Bistable circuits with additional means for controlling the main nodes
- H03K3/356095—Bistable circuits with additional means for controlling the main nodes with synchronous operation
Description
<t<t
Mit dem Knoten 1 ist die Bitleitung 11 und mit dem Knoten 2 die Bitleitung 21 verbunden.With the node 1 is the bit line 11 and with the Node 2 the bit line 21 connected.
'n der aus der Figur ersichtlichen Weise ist beispielsweise das Ein-Transistor-Speicherelement 3 mit der Bitleitung 21 verbunden. Das Speicherelement 3 besteht aus dem Speicherkondensator 31 und dem über die Wortleitung 33 ansteuerbaren Transistor 30, der vorzugsweise ein MOS-Transistor ist'n as shown in the figure for example, the one-transistor memory element 3 is connected to the bit line 21. The memory element 3 consists of the storage capacitor 31 and the transistor 30 controllable via the word line 33, the is preferably a MOS transistor
Zum Vorbereiten auf das Auslesen (Precharge) w;rd der Quertransistor 6 über den Anschluß 8 leitend geschaltet Dies bedeutet, daß bei abgeschalteten Lasttransistoren 44 und SS sich die Spannungen Vi und V2 der Knoten 1 und 2 einander angleichen und, wie dies in der älteren Patentanmeldung P 23 07 323.6 (VPA 73/7018) in der Rg. 2 dargestellt ist, den Wert Vr erreichea Dieses Referenzpotential VV ist dabei identisch mit der Einsatzspannung der Schalttransistoren 4 und 5 und weicht von dem günstigsten Mittelwert Um=OJS (Um+ Um) ab. Dabei bedeutet Um ias an den Bitleitungen 11 bzw. 21 anliegende Potential bei einer aus dem Speicherelement 3 ausgelesenen »0« und Um das an den Bitleitungen U bzw. 21 anliegende Potential bei einer aus dem Speicherelement 3 ausgelesenen »1«.To prepare for readout (precharge) w ; rd the transverse transistor 6 is switched on via the terminal 8. This means that when the load transistors 44 and SS are switched off, the voltages Vi and V 2 of the nodes 1 and 2 equalize and, as described in the earlier patent application P 23 07 323.6 (VPA 73 / 7018) is shown in Rg. 2, the value Vr reaches a This reference potential VV is identical to the threshold voltage of the switching transistors 4 and 5 and deviates from the most favorable mean value Um = OJS (Um + Um) . Um ias means the potential applied to the bit lines 11 or 21 when a “0” is read from the memory element 3 and Um means the potential applied to the bit lines U or 21 when a “1” is read from the memory element 3.
Gemäß dem Merkmal der Erfindung wird nun die Einsatzspannung der Schalttransistoren so erhöht, daß das Referenzpotential dem günstigsten Mittelwert LZm=O1S · (Ubo+ Um) entspricht Dadurch wird vorteilhafterweise erreicht, daß bei Auswahl eines Speicherelementes unabhängig von der Art der gespeicherten Information der Absolutbetrag der Spannungsänderuag an der Bitleitung gleich groß istAccording to the feature of the invention, the threshold voltage of the switching transistors is increased so that the reference potential corresponds to the most favorable mean value LZm = O 1 S · (Ubo + Um) the voltage change on the bit line is the same
Die Einsatzspannung der Schalttransistoren kann beispielsweise durch die Erhöhung der Dotierung des Substrates unterhalb der Gateelektrode der Schalttransistoren erreicht werden. Beispielsweise kann die Dotierung durch einen Ionenimplantationsschritt bewerkstelligt werden. Ein solcher Schritt erfordert nur eine zusätzliche Maske. Beispielsweise errechnet sich bei einer Ionenimplantationsdosis von z. B. 1 · 1012/cm2, einer Oxiddicke von DOx=60nm und einer Substratvorspannung von UaA= -8 V für einen n-Kanal-Feldeffekt-Transistor die Einsatzspannung zu VV= 5 V.The threshold voltage of the switching transistors can be achieved, for example, by increasing the doping of the substrate below the gate electrode of the switching transistors. For example, the doping can be accomplished by an ion implantation step. Such a step only requires an additional mask. For example, with an ion implantation dose of e.g. B. 1 · 10 12 / cm 2 , an oxide thickness of D O x = 60 nm and a substrate bias voltage of UaA = -8 V for an n-channel field effect transistor, the threshold voltage to VV = 5 V.
Weiterhin kann eine Erhöhung der Einsatzspannung der Schalttransistoren dadurch erreicht werden, daß fürFurthermore, an increase in the threshold voltage of the switching transistors can be achieved in that for die Schalttransistoren und für die Lasttransistoren verschiedene GatemateriaHea verwendet werden. Beispielsweise kann für die Lasttransistoren Silizium und für die Schalttransistoren Aluminium Verwendung finden. Die Differenz der Austrittsarbeiten zwischen dem Gatematerial und dem Substrat geht dabei additiv in die Formel zur Berechnung der Einsatzspannung Ut ein. Da diese Differenz bei Al—Silizium um ca. 1,1 V höher ist als bei Si-Si, ist mit eine.* Erhöhung der Einsatzspannung um diesen Betrag bei Al-Gate-Transistoren zu rechnen.the switching transistors and different GatemateriaHea are used for the load transistors. For example, silicon can be used for the load transistors and aluminum can be used for the switching transistors. The difference in the work functions between the gate material and the substrate is added to the formula for calculating the threshold voltage Ut . Since this difference is approx. 1.1 V higher with Al-silicon than with Si-Si, an increase in the threshold voltage by this amount is to be expected with Al-gate transistors.
Eine weitere Möglichkeit für die Erhöhung der Einsatzspannung der Schalttransistoren ergibt sich durch die Erhöhung der Gateoxiddicke. Die z. B. bei R. H. Crawford (»MOSFET in Circuit Design«, McCraw-HM 1967, S. 39) erwähnte Formel zur Berechnung der Einsatzspannung eines MOS-Feldeffekt-Transistors hat folgende Gestalt:Another possibility for increasing the threshold voltage of the switching transistors results by increasing the gate oxide thickness. The z. B. at R. H. Crawford ("MOSFET in Circuit Design", McCraw-HM 1967, p. 39) mentioned formula for calculating the threshold voltage of a MOS field effect transistor has the following form:
UT = U T =
tox die Dicke des Gateisolators, Box die Dielektrizitätskonstante des Gateisolators, tox the thickness of the gate insulator, box the dielectric constant of the gate insulator,
es die Dielektrizitätskonstante des Substrates, q die Elementarladung, N die Dotierung des Substrates, Φ F das Fermipotential, YBG die Substratvorspannung, Vss das Oberflächenpotential, VFB die Flachbandspannung. e s the dielectric constant of the substrate, q the elementary charge, N the doping of the substrate, Φ F the Fermi potential, YBG the substrate bias, Vss the surface potential, VFB the flat band voltage.
Für Standardwerte, wie sie z. B. bei R. H. Crawford angegeben werden, erhält man bei einer Erhöhung der Dicke tox von 60 nm auf 120 nm eine Änderung der Einsatzspannung von t/r= + 2 V auf Ur= +4 V, wenn eine Substratvorspannung von Vbg=-8 V und eine Substratdotierung N= 6 · 1015 angenommen wird.For standard values such as B. specified by RH Crawford, an increase in the thickness t ox from 60 nm to 120 nm results in a change in the threshold voltage from t / r = + 2 V to Ur = +4 V when a substrate bias of Vbg = -8 V and a substrate doping N = 6 · 10 15 is assumed.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19742420663 DE2420663B2 (en) | 1974-04-29 | 1974-04-29 | REGENERATING AND EVALUATING CIRCUIT AND PROCESS FOR THEIR PRODUCTION |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19742420663 DE2420663B2 (en) | 1974-04-29 | 1974-04-29 | REGENERATING AND EVALUATING CIRCUIT AND PROCESS FOR THEIR PRODUCTION |
Publications (2)
Publication Number | Publication Date |
---|---|
DE2420663A1 DE2420663A1 (en) | 1975-11-13 |
DE2420663B2 true DE2420663B2 (en) | 1977-02-10 |
Family
ID=5914223
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19742420663 Granted DE2420663B2 (en) | 1974-04-29 | 1974-04-29 | REGENERATING AND EVALUATING CIRCUIT AND PROCESS FOR THEIR PRODUCTION |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE2420663B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2838817A1 (en) * | 1978-09-06 | 1980-03-20 | Ibm Deutschland | TTL COMPATIBLE ADDRESS LOCKING CIRCUIT WITH FIELD EFFECT TRANSISTORS AND CORRESPONDING OPERATING METHOD |
-
1974
- 1974-04-29 DE DE19742420663 patent/DE2420663B2/en active Granted
Also Published As
Publication number | Publication date |
---|---|
DE2420663A1 (en) | 1975-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE2312414C2 (en) | Process for the manufacture of integrated MOSFET circuits | |
DE2324965A1 (en) | CIRCUIT ARRANGEMENT FOR READING A CAPACITIVE DATA MEMORY | |
DE2552644C2 (en) | Integrated semiconductor read-only memory and process for its manufacture | |
DE3206507C2 (en) | ||
EP0483537A2 (en) | Current source circuit | |
DE3329820A1 (en) | CIRCUIT ARRANGEMENT WITH A COUNTERACTIVE VALUE ELEMENT | |
DE2550107A1 (en) | CIRCUIT ARRANGEMENT WITH FIELD EFFECT TRANSISTORS | |
DE3633591C2 (en) | Internal full differential operational amplifier for integrated CMOS circuits | |
DE2557165C3 (en) | Decoder circuit and its arrangement for integration on a semiconductor module | |
DE2622307C2 (en) | Integrated semiconductor memory device | |
DE3240189A1 (en) | FIELD EFFECT TRANSISTORS WITH INSULATED GATE (IGFET) CIRCUIT | |
DE1953975B2 (en) | High speed polyphase gate | |
DE3243674C2 (en) | Reference voltage circuit | |
WO1996042050A1 (en) | Circuit for comparing two electrical quantities provided by a first neuron mos field effect transistor and a reference source | |
DE3430972C2 (en) | Integrated circuit | |
DE2431079C3 (en) | Dynamic semiconductor memory with two-transistor memory elements | |
DE2519323C3 (en) | Static three-transistor memory element | |
DE2523683A1 (en) | CABLE FOR TRANSPORTING A CHARGE, IN PARTICULAR CABLE FOR STORAGE ELEMENTS THAT FORM A STORAGE FIELD | |
DE2433077A1 (en) | DYNAMIC STORAGE DEVICE | |
DE2420663B2 (en) | REGENERATING AND EVALUATING CIRCUIT AND PROCESS FOR THEIR PRODUCTION | |
DE2836948A1 (en) | MOS ANALOG / DIGITAL CONVERTER | |
DE2839459A1 (en) | CIRCUIT ARRANGEMENT FOR SIGNAL LEVEL CONVERSION | |
DE2748571B2 (en) | ||
EP0045403A1 (en) | Method of producing a device to reduce the influence of radiation on MOS memory cells | |
DE2441385C3 (en) | Method for increasing the read signal in a one-transistor memory element |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C3 | Grant after two publication steps (3rd publication) | ||
E77 | Valid patent as to the heymanns-index 1977 | ||
8339 | Ceased/non-payment of the annual fee |