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DE2363262A1 - Serienaddierer - Google Patents

Serienaddierer

Info

Publication number
DE2363262A1
DE2363262A1 DE19732363262 DE2363262A DE2363262A1 DE 2363262 A1 DE2363262 A1 DE 2363262A1 DE 19732363262 DE19732363262 DE 19732363262 DE 2363262 A DE2363262 A DE 2363262A DE 2363262 A1 DE2363262 A1 DE 2363262A1
Authority
DE
Grant status
Application
Patent type
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19732363262
Other languages
English (en)
Inventor
Jean Rabasse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/504Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G06F7/5045Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other for multiple operands
DE19732363262 1972-12-29 1973-12-19 Serienaddierer Withdrawn DE2363262A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7247029A FR2212952A5 (de) 1972-12-29 1972-12-29

Publications (1)

Publication Number Publication Date
DE2363262A1 true true DE2363262A1 (de) 1974-07-04

Family

ID=9109547

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732363262 Withdrawn DE2363262A1 (de) 1972-12-29 1973-12-19 Serienaddierer

Country Status (8)

Country Link
US (1) US3941990A (de)
BE (1) BE808706A (de)
DE (1) DE2363262A1 (de)
DK (1) DK140612C (de)
FR (1) FR2212952A5 (de)
GB (1) GB1451974A (de)
LU (1) LU69036A1 (de)
NL (1) NL7400047A (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5760660B2 (de) * 1978-10-25 1982-12-21 Hitachi Ltd
FR2454136B1 (fr) * 1979-04-12 1985-12-06 Materiel Telephonique Additionneur sequentiel rapide
US4368993A (en) * 1981-04-30 1983-01-18 Centronics Data Computer Corporation Replaceable assembly for multicolor printing
GB8707493D0 (en) * 1987-03-28 1987-08-05 Stonefield Systems Plc Cellular array processing
US5105379A (en) * 1990-04-05 1992-04-14 Vlsi Technology, Inc. Incrementing subtractive circuits
EP0489952B1 (de) * 1990-12-11 1998-08-19 Siemens Aktiengesellschaft Schaltungsanordnung zur digitalen Bit-seriellen Signalverarbeitung
CA2135857A1 (en) * 1994-01-03 1995-07-04 Shay-Ping Thomas Wang Neural network utilizing logarithmic function and method of using same
US5958001A (en) * 1994-03-31 1999-09-28 Motorola, Inc. Output-processing circuit for a neural network and method of using same
US5685008A (en) * 1995-03-13 1997-11-04 Motorola, Inc. Computer Processor utilizing logarithmic conversion and method of use thereof
US5644520A (en) * 1995-05-31 1997-07-01 Pan; Shao Wei Accumulator circuit and method of use thereof
US5771391A (en) * 1995-08-28 1998-06-23 Motorola Inc. Computer processor having a pipelined architecture and method of using same
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US6385634B1 (en) 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
US6230257B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
CN104202053B (zh) * 2014-07-17 2017-04-19 南京航空航天大学 一种快速n位原码到补码的转换装置和转换方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3264458A (en) * 1963-04-04 1966-08-02 Burroughs Corp Serial binary adder

Also Published As

Publication number Publication date Type
DK140612C (de) 1980-02-25 grant
BE808706A (fr) 1974-06-17 grant
NL7400047A (de) 1974-07-02 application
DK140612B (da) 1979-10-08 grant
US3941990A (en) 1976-03-02 grant
BE808706A1 (de) grant
GB1451974A (de) 1976-10-06 application
LU69036A1 (de) 1974-07-05 application
FR2212952A5 (de) 1974-07-26 application

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Legal Events

Date Code Title Description
8141 Disposal/no request for examination