DE2257216A1 - SEMICONDUCTOR COMPONENT WITH A LAYER OF SILICON DIOXYDE - Google Patents
SEMICONDUCTOR COMPONENT WITH A LAYER OF SILICON DIOXYDEInfo
- Publication number
- DE2257216A1 DE2257216A1 DE2257216A DE2257216A DE2257216A1 DE 2257216 A1 DE2257216 A1 DE 2257216A1 DE 2257216 A DE2257216 A DE 2257216A DE 2257216 A DE2257216 A DE 2257216A DE 2257216 A1 DE2257216 A1 DE 2257216A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- semiconductor
- semiconductor component
- semiconductor substrate
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 229910052710 silicon Inorganic materials 0.000 title claims description 7
- 239000010703 silicon Substances 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000000737 periodic effect Effects 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 230000005669 field effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 1
- -1 aluminum compound Chemical class 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
- H01L21/02145—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing aluminium, e.g. AlSiOx
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Deutsche ITT Industries GmbH R.A.H. Heinecke -German ITT Industries GmbH R.A.H. Heinecke -
78 Freiburg, Hans-Bunte-Str. 19 . Go/ra78 Freiburg, Hans-Bunte-Str. 19th Go / ra
20. November 1972November 20, 1972
DEUTSCHE ITT INDUSTRIES GESELLSCHAFT MIT BESCHRÄNKTER HAFTUNGDEUTSCHE ITT INDUSTRIES GESELLSCHAFT LIMITED LIABILITY
FREIBURG I. BR.FREIBURG I. BR.
Halbleiterbauelement mit einer Schicht aus SiliciumdioxydSemiconductor component with a layer of silicon dioxide
Die Priorität der Anmeldung Nr. 55 960/71 vom 2. 12. 1971 in Großbritannien wird beansprucht.The priority of application no. 55 960/71 dated December 2, 1971 in Great Britain is claimed.
Siliciumdioxyd ist ein weit und breit verwendetes Material für die Isolierschicht auf planaren Halbleiterbauelementen. Die positive Raumladung in Dielektrika aus SiO„ erzeugt jedoch an der Halbleiteroberfläche eine Elektronenschicht. Aufgrund der Potentialdifferenz zwischen SiO2 und Si ist dieser Effekt bei halbleitendem Material aus Silicium besonders ausgeprägt. Der Effekt wird gar noch mehr durch positiv vorgespannte Zwischenverbindungs-Leiterzüge auf der Schicht aus SiO? gefördert und es kann im Falle eines p-leitenden Halbleitersubstrats eine Inversion, d. h.- eine Wandlung vom p-Leitfähigkeitstyp in den n-Leitfähigkeitstyp im Oberflächenbereich, auftreten.Silica is a widely used material for the insulating layer on planar semiconductor devices. However, the positive space charge in dielectrics made of SiO “creates an electron layer on the semiconductor surface. Because of the potential difference between SiO 2 and Si, this effect is particularly pronounced in the case of semiconducting material made of silicon. The effect is made even more by the positively prestressed interconnection conductor tracks on the SiO layer ? promoted and in the case of a p-conducting semiconductor substrate, an inversion, ie a conversion from the p-conductivity type to the n-conductivity type in the surface region, can occur.
Enthält ein Halbleiterbauelement eine Anzahl von η-Kanal-MOS-Elemente mit benachbarten η-leitenden Zonen von funktibnsmäßigIf a semiconductor component contains a number of η-channel MOS elements with neighboring η-conductive zones of functional terms
30982/·/0793 . " 2 "30982 / · / 0793. " 2 "
Fl 735 R.A.H. Hexnecke - 4Fl 735 R.A.H. Hexnecke - 4
getrennten Elementen, welche gegeneinander durch p-leitendes Halbleitermaterial isoliert sind, das von einer einen positiv vorgespannten Zwischenverbindungs-Leiterzug tragenden SiO„-Schicht bedeckt ist, wie es bei n-Kanal-MOS-Bauelementen des Anreicherungstyps der Fall ist, so kann die gebildete Elektronenschicht sehr wohl diese benachbarten η-leitenden Zonen durch Bildung eines n-Leitkanals zwischen ihnen kurzschließen.separated elements, which are mutually opposed by p-type Semiconductor material are isolated by a positively biased interconnect trace carrying SiO "layer is covered, as is the case with n-channel MOS components Enrichment type is the case, so the electron layer formed can very well short-circuit these neighboring η-conductive zones by forming an n-conductive channel between them.
Aufgabe der Erfindung ist die Verhütung eines derartigen Kurzschlusses. The object of the invention is to prevent such a short circuit.
Die Erfindung betrifft somit ein Halbleiterbauelement mit einer Schicht aus Siliciumdioxyd auf einem p-leitenden Halbleitersubstrat. Ein Kurzschluß der oben erwähnten Art wird erfindungsgemäß dadurch verhindert, daß die Schicht aus Siliciumdioxyd an der Zwischenfläche zwischen dem Halbleitersubstrat und der Schicht mit Atomen der Metalle aus der II. oder III. Gruppe des periodischen Systems dotiert ist.The invention thus relates to a semiconductor component with a layer of silicon dioxide on a p-conducting semiconductor substrate. A short circuit of the type mentioned above is prevented according to the invention in that the layer of silicon dioxide on the Interface between the semiconductor substrate and the layer with atoms of the metals from II. Or III. Group of periodic System is endowed.
Vorzugsweise ist diese dotierte Schicht aus Silicium auf dem p-leitenden Halbleitersubstrat zwischen zwei funktionsmäßig getrennten η-leitenden Zonen angeordnet. This doped layer of silicon is preferably arranged on the p-conducting semiconductor substrate between two functionally separate η-conducting zones.
Ein bevorzugtes Ausführungsbeispiel der Erfindung wird im folgenden anhand der Figur der Zeichnung erläutert, welche zwei benachbarte n-Kanal-MOS-Elemente zeigt.A preferred embodiment of the invention is described below explained with reference to the figure of the drawing, which shows two adjacent n-channel MOS elements.
Das p-leitende Halbleitersubstrat 1 aus Silicium enthält zwei MOS-Feldeffekttransistorelemente (MOSFETs) 2 und 3, von denen jedes eine η-leitende Emitterzone 4, eine η-leitende Kollektorzone 5, eine Oxydschicht 6 und eine Gatt-Elektrode 7 aufweist. Zwischen der Emitterzone 4 des MOS-Feldeffekttransistors 3 und der Kollektorzone 5 des MOS-Feldeffekttransistors 2 ist eine Schicht 8 ausThe p-type silicon semiconductor substrate 1 includes two MOS Field Effect Transistor Elements (MOSFETs) 2 and 3, each of which an η-conducting emitter zone 4, an η-conducting collector zone 5, has an oxide layer 6 and a Gatt electrode 7. Between the emitter zone 4 of the MOS field effect transistor 3 and the collector zone 5 of the MOS field effect transistor 2 is a layer 8 made of
30982/4/07930982/4/079
735 R.A.H. Heinecke - 4735 R.A.H. Heinecke - 4th
Siiiciumdioxyd angeordnet, welche an der Zwischenf-läche 9 mit dem p-leitenden Halbleitersubstrat 1 aus Silicium mit Aluminiumatomen dotiert ist und die eine Metallisierungsschicht 10 unter Bildung eines Zwischenverbindungs-Leiterzuges zwischen der Emitterzone und der Kollektorzone der beiden MOS-Feldeffekttransistoren trägt. Dieser Zwischenverbindungs-Leiterzug überquert die Unterführungsdiffusionszone 11, welche zur Verbindung zwischen einem Element vor und einem Element hinter der Zeichnungsebenen dient. Eine entstandene Elektronenschicht würde die Feldeffekttransistoren 2 und 3 mit den über die Unterführungsdiffusionszone geschalteten Elementen verbinden (kurzschließen).Siiiciumdioxyd arranged, which on the intermediate surface 9 with the p-type semiconductor substrate 1 made of silicon with aluminum atoms is doped and the one metallization layer 10 with the formation of an interconnection conductor line between the emitter zone and the collector zone of the two MOS field effect transistors wearing. This interconnect trace traverses the underpass diffusion zone 11, which is used to connect an element in front of and an element behind the drawing levels. A resulting electron layer would be the field effect transistors 2 and 3 connected to the underpass diffusion zone Connect elements (short-circuit).
Die Zwischenflächendotierung mit Aluminium oder mit irgendeinem anderen geeignet gewählten Metall aus der II. oder III. Gruppe des periodischen Systems, beispielsweise Beryllium, bewirkt, daß die Dotierungsatome in der SiO„-Molekularstruktur eine feste Lage einnehmen, indem das Dotierungsatom an die Stelle des Si-Atoms tritt. Dies verursacht das Entstehen einer negativen Raumladung, die sich als ausreichend groß erwies, um allen positiven Beiträgen einschließlich derjenigen der Leiterzüge bis zu Vorspannungen auf einem Niveau von mehr als + 30 V entgegenzuwirken, d. h. mehr als es bei MOS-Festkörperschaltungen erforderlich ist.The interfacial doping with aluminum or with any one other suitably selected metal from II. or III. Group of the periodic table, for example beryllium, causes the Doping atoms occupy a fixed position in the SiO "molecular structure, in that the doping atom takes the place of the Si atom. This causes the creation of a negative space charge, which was found to be large enough to contain all positive contributions to counteract those of the conductor tracks up to bias voltages at a level of more than + 30 V, d. H. more than it is required in solid-state MOS circuits.
Die an der Zwischenfläche 9 dotierte Schicht aus Siiiciumdioxyd kann dadurch ausgebildet werden, daß zunächst auf dem p-leitandem Halbleitersubstrat eine Aluminiumschicht mit einer Dicke von etwaThe layer of silicon dioxide doped at the interface 9 can be formed in that first on the p-lead tandem Semiconductor substrate an aluminum layer with a thickness of about
ο
50 A, dann auf dem Aluminium durch einen IDampfphasenabscheidungs- ο
50 A, then on the aluminum by an IDapor phase deposition
prozeß Siiiciumdioxyd abgeschieden wird und danach eine Erhitzung auf 800° C während 10 bis 20 Minuten erfolgt.Process Siiiciumdioxid is deposited and then heating to 800 ° C for 10 to 20 minutes takes place.
Alternativ dazu kann das Aluminium und das Siiiciumdioxyd auch gleichzeitig durch einen Dampfphasenabscheidungsproze'ß aufgebracht werden, indem beispielsweise eine eine Aluminiumverbindung,Alternatively, the aluminum and the silicon dioxide can also be applied simultaneously by a vapor phase deposition process by, for example, an aluminum compound,
_ 4 _ 309824/0793_ 4 _ 309824/0793
Fl 735 R.Λ.H. Heinecke - 4Fl 735 R.Λ.H. Heinecke - 4th
wie Aluminiumtrichlorid, und eine Siliciumverbindung, wie Silan oder Siliciumtetrachlorid , enthaltende oxydierende Atmosphäre vorwendet wird. Dabei wird bei einer Temperatur von etwa 7OO C abgeschieden. Schließlich wird das Bauelement in einer trockenen Atmosphäre auf eine Temperatur oberhalb von 900 C erhitzt.such as aluminum trichloride, and a silicon compound such as Oxidizing atmosphere containing silane or silicon tetrachloride is used. It is deposited at a temperature of about 700 C. Finally, the component is in a heated dry atmosphere to a temperature above 900 C.
30982 W079330982 W0793
Claims (10)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5596071A GB1357210A (en) | 1971-12-02 | 1971-12-02 | Method of manufacturing semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
DE2257216A1 true DE2257216A1 (en) | 1973-06-14 |
Family
ID=10475341
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2257216A Pending DE2257216A1 (en) | 1971-12-02 | 1972-11-22 | SEMICONDUCTOR COMPONENT WITH A LAYER OF SILICON DIOXYDE |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE2257216A1 (en) |
FR (1) | FR2162039B1 (en) |
GB (1) | GB1357210A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4048350A (en) * | 1975-09-19 | 1977-09-13 | International Business Machines Corporation | Semiconductor device having reduced surface leakage and methods of manufacture |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3360695A (en) * | 1965-08-02 | 1967-12-26 | Sprague Electric Co | Induced region semiconductor device |
US3607469A (en) * | 1969-03-27 | 1971-09-21 | Nat Semiconductor Corp | Method of obtaining low concentration impurity predeposition on a semiconductive wafer |
-
1971
- 1971-12-02 GB GB5596071A patent/GB1357210A/en not_active Expired
-
1972
- 1972-11-22 DE DE2257216A patent/DE2257216A1/en active Pending
- 1972-11-29 FR FR7242338A patent/FR2162039B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB1357210A (en) | 1974-06-19 |
FR2162039A1 (en) | 1973-07-13 |
FR2162039B1 (en) | 1976-04-23 |
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