DE2245688B2 - Transistor, suitable for digital electrical memory circuits, method for operating such a transistor and application in a circuit consisting of a memory matrix and decoders - Google Patents

Description

The invention relates to a transistor suitable for digital electrical memory circuits, with a channel and with a layered gate insulator, the transistor, its threshold voltage depends on the stored electrical charge in the gate insulator, in a star on fe Substrate lying at potential is arranged, whereby the storage of the electrical charge or the deletion of a stored electrical charge by applying electrical voltages between Gate electrode and the substrate takes place.

The invention also relates to methods of operating such a transistor.

In Component Technology, Vol. 4, No. 5, October 1970, pp. 17-21, there is one Memory arrangement containing such transistors described. The matrix of this memory arrangement consists of MNOS transistors.

In U.S. Patent 3,04,988 is a transistor described with a layered gate insulator. This gate insulator consists of a silicon dioxide layer and a zinc sulfide layer.

However, such known arrangements have

so cons. For switching the transistors when writing information or for reading and erasing of information namely tensions of different signs with respect to the Semiconductor substrate required. In the case of memory arrangements using single-channel technology, the memory matrix and the associated decoders are built on substrates that are separate from one another.

Single-channel semiconductor technology is understood to mean a technology in which either only p-channel MOS field effect transistors or only n-channel MOS field effect transistors are used. As a rule, only a diffusion in the semiconductor substrate is required for this.
A memory arrangement has also become known from US Pat. No. 3,651,490 in which transistors with a layered gate insulator made of a silicon dioxide layer and an aluminum oxide layer (Al ₂ O ₃ ) are used. In the

Arrangement of these memory transistors in a matrix, as shown in FIGS. 6 to 9, for writing information or for reading and erasing also different voltages Polarities required,

From this United States patent there is also one 3-dimensional memory arrangement has become known in which, as shown in FIGS. 1 and 12 shown, for writing information or for reading and erasing only voltages of one polarity are used. In FIG. 10 is the memory matrix this memory arrangement shown. However, each point in this matrix consists of one Storage transistor with a layered gate insulator and made up of a transistor that is not storing Possesses properties.

An object of the invention is to provide a transistor with a laminated gate insulator for electrical Specify memory circuits in which, depending on the stored in the gate insulator electrical charge, the threshold voltage with only one polarity between the gate, source and drain electrodes on the one hand and the common substrate on the other hand can be changed.

This object is achieved by a transistor as described at the outset, which according to the invention characterized in that both for storing and for erasing the in the gate insulator layer stored electrical charge voltages of the same sign between the gate electrode and the common substrate or between the source and drain electrodes and the common Substrate are applied and that the channel length of the transistor is shorter than double when Storage or barrier layer thickness that occurs when deleting.

Such transistors are preferably MNOS transistors which are applied to a common 10 ohm cm η-conductive silicon substrate. The gate insulator of the transistors consists of an approximately 2 nm thick SiO ₂ layer and an approximately 55 nm thick Si ₃ N ₄ layer applied to it. The Karal length of the transistors is advantageously 1 to 5 (im, and the voltages used for writing, reading and erasing information are preferably 0 or -40VoIt.

In terms of process technology, the object is achieved in accordance with claims 5 or 7.

An advantage of a memory arrangement with inventions Transistors according to the invention result from the fact that it is not necessary, as is the case with the specified State of the art is the case, the common substrate by diffused areas, as they are in the Complementary channel MOS technology or the bipolar Technology are usually divided into electrically separate sections.

This advantage is particularly evident when using the transistor according to claim 4.

Further explanations of the invention can be found in the description and the figures of preferred exemplary embodiments the invention and its further developments.

F i g. 1 shows a schematic representation of an MNOS transistor;

Fig. 2 shows a ^ thematic representation Memory matrix made of MNOS transistors; in

F i g. 3 are the storage characteristics of an inventive MNOS transistor shown with a short channel length;

Fig, 4 shows a schematic representation Memory arrangement with transistors according to the invention,

In FIG. 1, the substrate of the p-channel transistor, which is preferably a 10-ohm cra substrate made of η-conductive silicon, is denoted by 1. The p-conducting source region has the reference number 2 and the p-conducting drain region has the reference number 3. These regions are preferably diffused into the substrate 1. The gate insulator of the transistor is layered. It preferably consists of a 2 mm thick SiO., Layer 4 and a 55 nm thick SiN ₄ layer 5 applied to it. The electrode of the source region is marked with 22, the electrode of the drain region with 33, the The connection electrode of the substrate is denoted by 11 and the electrode of the gate is denoted by 55.

The channel length 8 of the MNOS transistors according to the invention is shorter than double Is the barrier layer thickness during writing or deleting. The channel length is preferably with one as indicated above and in FIG. 1 shown MNOS transistor 1 to 5μΐη. Under The barrier layer thickness is the thickness of the space charge zone in the substrate around the source or drain region understood as a function of the voltage applied to the source or drain electrode.

At the boundary layer between the SiO ₂ layer 4 and the Si ₃ N ₄ layer 5 there is a large number of terms 9 (traps) which are charged or discharged by different voltages of the same sign at the source, drain or gate. As a result, the transistor has either a high or a low threshold voltage. The threshold voltage is understood to be the voltage at the gate at which the transistor becomes conductive. These two states can be used to store the information "0" and "1".

In FIG. 3 shows the storage characteristics of a transistor according to the invention as described above with a channel length of 3 μτη. With 6 the working line when writing the state “1”, with 7 the working line when preventing the writing of a “1” and with 10 the working line when reading out. 19 represents the working line for erasing, ie for writing the state “0” in an MNOS transistor with a large channel length. Curve 18 is the working characteristic for erasing in an MNOS transistor according to the invention with a short channel length. As can be seen from lines 19 and 18, MNOS transistors with short channel lengths have an influence of the drain and source voltage on the gate voltage.

To write a “0” into transistors according to the invention, the gate is set to 0 volts and the source and drain placed at -40 volts. When writing a "1", the source and drain are at 0 volts, whereas -40 volts can be applied between electrode 11 of the substrate to the gate. Deleting Information written into a transistor is done by setting the state "0". Of the The readout process corresponds to the write process. However, that applied to the gate electrode 55 is Reading voltage preferably -10 volts.

Using a memory matrix with 2X2 transistor

2 2413 688 ξ

S 6

ren should now the functionality of an MNOS output of the decoding gate optionally with the help Storage matrix are explained. In Fig.2 a pulse is to be inverted. The decoder legs such matrix shown. The consists of the stands of the transistors 41, 42, 43, 44, which the Transistors 14, 15, 16 and 17. Form decoding gates before starting operation. The gate is "selected", a »0« is first written into all transistors 5 if they are written on transistors 41, 42 and 43, d. that is, the entire memory is erased. Address to be used, as shown in the figure, the for this purpose, gate lines 555 on gate line 422 are selected with transistor 421. 0 volts, the source lines 222 and the drain line In this case, the potential of the point 53 is present lines 333 - 40 volts applied. the exit of the gate. This output of the gate

Then line by line in the matrix io ters leads to an exclusive OR, which is written by the, including transistors 7 * ₄₅ , T ₄₈ , T ₄₇ , T ₄₈ and T ₄₉ in certain transistors, a line that has »0 «To a» 1 «- if you look at the selected gate and write it. If, for example, a "1" is to be written into the Transi-OVoIt at the input 54 of the exclusive OR disruptor 15, an is on, so since the transistor 46 is conductive, the transe is a gate line and also to the gate line 15 transistors 48 and 410 blocked, that is, applied to the input of transistor 14, the potential -40 volts. 56 and the transistor 411 is the write voltage. The supply voltage is applied to the drain line 333 and is connected to the selected gate line 422, which has the voltage V _D , which is preferably approximately −20 volts. Gate of transistor 421 is connected to. The source lines 222 cannot be connected to ground via the switches, gate lines not selected, no 12 and 13 can be connected to ground. In order to apply the ao write voltage, since these are then short-circuited by the conductive writing of a "1" in transistor 14, transistors 410,
the corresponding switch 12 in the transistor 419 is used to write the in-source line is left open. Thus, the information lies. If a “1” is to be written, the sion layer of the transistor 14 is at the potential of the source line of the relevant memory supply voltage V _n . The gate voltage at the as column is connected to ground. If a “0” is to be retained. Line 555 of transistor 14 is not sufficient to switch the source line of the corresponding transistor 14 to the “1” state. He interrupted the storage column. This transistor remains in the "0" state. Switch 13 in source 419 corresponds to switches 12 and 13 in FIG. 2.
Line 222 of transistor 15 is closed; Between the read process corresponds to the write process, see the gate and the substrate Hests the full 30 Here, however, the read voltage, preferably the gate voltage. The transistor 15 is switched to about -10 volts via the transistor 412 to stand "1". The selected gate line is thus placed in transistor 15. During the selectively a "1" is written, whereas in all read-on operations, the transistor 420 remains in its "0" state via the other transistors, and passage 57 is made conductive. Then they all lie

To read out the information, one is attached to the relevant source lines of the individual transistors

fende gate line to the read voltage, preferably storage column to ground. The transistor 414 is

the voltage -10 volts applied. The source line is found during the reading process via the

device is controlled during the reading process to 0 volts and the input 58, even in the conductive state, see above

Drain line placed at preferably -20 volts. that depending on whether the memory transistor

The transistors in the "0" state are then conductive, 4 ° 421 is in the "0" or "1" state, where the output

the transistors in the "1" state are blocked. output 59 the output voltage 0 volts or the voltage

For storage with high capacity it is necessary to use point 60, preferably -10 volts,

dig, in front of the individual gate lines that the gate represents.

Connect the electrodes of a row of the memory matrix. During the erasure process, a pulse is applied

to put a decoder so that the number of terminals 45 at input 51 of transistor 417 is made conductive,

Closing lines n ^ drig can be kept. In d. i.e., the source and drain lines of the Tr. nsisto-

a matrix with a decoder, the gate lines of a matrix column are short-circuited. the

gen to diffused areas and form with the erase voltage is via the transistor 418, the

Substrate a pn junction. In the case of single-channel technology, it is controlled via input 52, to the source

in solid silicon, d. H. if only p- or n-channel 50 and drain lines are applied. The transistor 414

Transistors arranged on a chip can remain blocked so that the high erase voltage does not occur

With respect to the substrate, only one voltage occurs at the output 59. The transistors 419 and

Polarity must be applied, otherwise the pn junctions 420 remain blocked, so that the erase voltage does not

were polarized in the forward direction. is short-circuited to ground. At the same time will

In a memory arrangement with the invention, the address line is selected. At the entrance 54

With MNOS transistors of short channel length, a voltage is applied and the transi-

the writing of information in the memory disturb 411 a write-

with a voltage of a predetermined potential applied voltage. In the exclusive OR that

and only a given polarity on the gate belonging to the selected gate, conduct the transi-

while 49 and 48 interfere with the gate on 60 when erasing the information, the write voltage is short-circuited

0 volts ground potential is held and source and closed, and the gate line is practically aul

Drain to a correspondingly high potential of the same 0 volts. In the unselected Gatc manager

the polarity. on the other hand, the transistors 49 and 410 remain ge

In the Fig.4 is a memory arrangement, which blocks off, the high write voltage is on all gate

MNOS transistors constructed with short channel lengths, 65 lines are effective. This is due to the memory

and from the memory matrix, decoding gates and ex-transistors of these lines source, drain and gate

inclusive OR is shown. The exclusive on the same potential. The condition of this egg

OR has the task of not changing the logical state of the mente.

1 sheet of drawings

Claims (8)

Patent claims: 1. transistor, suitable for digital electrical Memory circuits, with one channel and with a layered gate insulator, the transistor, its threshold voltage from the electrical charge stored in the gate insulator depends changeably and is arranged in a substrate lying at a fixed potential, wherein the storage of the electrical charge or the deletion of a stored electrical charge takes place by applying electrical voltages between the gate electrode and the substrate, characterized in that both for storing and for erasing the electrical stored in the gate insulator layer Charge voltages of the same sign between the gate electrode and the common Substrate or between the source and drain electrodes and the common substrate and that the channel length of the transistor is shorter than double when storing or the thickness of the barrier layer occurring during erasure. 2. Transistor according to claim ί, characterized in that the layered gate insulator consists of a Si0 _o layer and a Si ₃ N ₄ layer applied thereon, the SiO., - Layer is arranged on the substrate. 3. Transistor according to claim 2, characterized in that the transistor is applied to a 10-Ohmcm-Siliziuni-Subslrat that its channel length is 1 to 5 μν and that the layered gate insulator consists of an approximately 2 nm thick SiO ₂ layer with an approximately 55 nm thick Si ₃ N ₄ layer applied thereon. 4. Use of a transistor according to one of claims 1 to 3 in an electrical circuit in single-channel technology, which essentially consists of a memory matrix and decoding! consists, the individual gate electrodes of the transistors in a row of the matrix having a common Gate lines are connected together and where the source electrodes of a column the matrix via a common source line and the drain electrodes of the individual transistors of a column are connected to one another via a common drain line, with one each Decoder is assigned to a gate line. 5. A method for operating a transistor or an electrical circuit according to one of the Claims 1 to 4, characterized in that the state "1" is written into a transistor when its source electrode is about substrate potential, its drain electrode is on any potential and its gate electrode when using a p-conductive substrate a relatively large positive potential compared to the substrate potential and when in use an η-conductive substrate to a relatively large negative compared to the substrate potential Potential are placed, with all potentials having the same sign. 6. The method according to claim 5, characterized in that that the substrate electrode and the source electrode are connected to 0 volts and that the gate electrode is applied to a potential which is <-30 Vol't, the substrate is an η-conductive substrate. 7, Method of operating a transistor or an electrical circuit according to one of Claims 1 to 4, characterized in that to write the status »0« in an MNOS transistor or to delete the status "1" of a MNOS transistor in the memory matrix puts the gate electrode at about substrate potential is held and the bource and drain electrodes of the transistor on one in comparison relatively large positive potential can be applied to the substrate potential when the substrate is a p-substrate, and that the source and drain electrodes of the transistor are on one opposite the substrate potential can be placed relatively large negative potential when the substrate is an η substrate. 8. The method according to claim 7, characterized in that the substrate electrode and the The gate electrode is connected to 0 volts and that the source electrode and the drain electrode are connected a potential which is <-30 volts, can be applied, wherein the substrate is an η-conductive substrate.