DE2233448A1 - CIRCUIT ARRANGEMENT FOR OBTAINING THE VOLTAGE-TIME FUNCTION OF PERIODIC SIGNALS BY STOCHASTIC SENSING - Google Patents

Description

PHILIPS PATEIiTVERWALTUIiG GMBH, HAMBURG 1, STEINDAMM 94,

Circuit arrangement for obtaining the voltage-time function of periodic signals by stochastic sampling

The invention relates to a circuit arrangement for. Extraction the voltage-time function of periodic signals.

For storing and / or displaying the voltage-time curve periodic oscillations are known scanning methods which are synchronized with the frequency of the oscillation Sampling of the signal voltage are based. An example of this is the sampling oscillograph, see the article by L. Starke: "The sampling oscillograph" Magazine. "Elektronik", 1961, pp. 117-120; or the essay by H.W. Fricke: "The sampling oscilloscope", Electronics, 1967, pages 361-364.

Unfortunately, these known arrangements are relatively narrow-band, and they also require frequency-selective means, such as filters and synchronous oscillators.

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3Q98S4 / Q79G

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The object of the present invention is to create a circuit arrangement of the type mentioned at the outset which is not only an extreme Has broadband, but also does not require any frequency-selective means.

Such a circuit arrangement according to the invention is characterized in that the signal at the first input of an analog Iores whose output is connected to the inputs of an amplitude detector and an edge detector, their outputs at two inputs of an addressing and writing circuit lie, which have a memory and a read circuit

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to a first, direct exit and via an arithmetic unit

a second output that the arithmetic unit with another Input of the addressing and writing circuit is connected, and that a control circuit is provided which is connected to the addressing and writing circuit, the reading circuit, the arithmetic unit and connected to the analog gate via a random pulse generator is.

The circuit arrangement according to the invention is based on the drawing described in more detail. Show in it:

Fig. 1 is a block diagram of the proposed circuit arrangement and
Pig. 2 as an example a voltage-time function with a sinusoidal

shaped and a linear plank with the associated . Probability density distributions.

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The signal to be examined is fed to an input "1" of an analog gate 2 supplied. The output of the analog lores 2 is each with an input of an amplitude detector 4 and a plane detector 5 connected, the outputs of which with two first inputs an addressing and viewing circuit 6 are connected. To this Circuit 6 is followed by a memory 7 and a read circuit 8. This reading circuit 8 has a first output 11 and a second output which leads to a second output 12 via an arithmetic unit 9. Another output of the arithmetic unit is connected to another input of the addressing and writing circuit 6 '. · ^. .

Furthermore, a control circuit 10 is provided, which is connected to both the addressing and writing circuit 6 and the reading circuit 8 as well as with the arithmetic unit 9 and a random pulse generator 3 is connected. This random pulse generator 3 also controls the Analog-5Dor 2 via its output.

A periodic signal to analyze is in the analog port 2 sampled in stochastically fluctuating time intervals. This analog Ior is controlled by the random pulse generator 3. The 'signal samples faded out by the analog gate 2 thus have amplitude values whose probability density ever division corresponds to that of the scanned input signal. The signal samples are sent to an amplitude detector

from, the task of which is to send to one of the outputs indicate in which voltage interval the respective entoramene Signal sample lies. The possible signal span is

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voltage range u ^ to u _{χ divided} into η voltage _{intervals ^ 1} j AUp, ... au .... & u. It is also determined whether the signal sample was taken from a positive or negative going edge of the signal. This position can be taken by the amplitude detector 4 or another suitable circuit arrangement. Further signal parameters not described in detail here can also be detected.

The number of markings arriving in the course of a certain period of time by amplitudes falling into an interval & u. fall is accumulated in a downstream binary value memory 7. There are a total of 2 η binary value storage spaces, namely η memory locations S ^ for the positive going planks and η memory locations S ^ for the negative going planks. The accumulation time is chosen to be so large that the relative distribution of the binary values on the memory locations no longer changes significantly and thus represents an exact image of the probability density distribution ρ (i = f- (u)) of the signal voltage u (t).

It can now be shown that between ρ imd u (t) there is a relative simple functional relationship exists when the stress-time puncture u (t) over a period of two planks with a clear Sense of slope, i.e. without reverse loops, composed is, however, zero incline points in the course of the planks are permissible.

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This relationship is:

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This results in "2 η support points for obtaining" Function value pairs the calculation rule ".

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The corresponding summation of the individual Binary value stores accumulated measures for the probability density the individual signal voltage values are used one after the other for "both planks of the voltage-time function carried out and there are thus 2 η fourth pairs of each i or, the assigned u and t *

Fig. 2 shows / by way of illustration a voltage-time function as an example with a sinusoidal and a linear plank with the associated probability density distributions P (u) f and ρ (u) J. The integration provides the reverse function t (u) is the voltage-time function u (t).

The restriction made in the above description that the Stress-time function u (t) per period must be composed of two planks with a clear sense of slope, can be avoid through increased circuit complexity. For this it is necessary that the oscillation period corresponds to the An-Zf3hl of the sections it contains with jev / eilo more positive or negative gradient one after the other in η sections

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is split. Instead of the edge detector 5, which only. jev / eils have to recognize one of two possible flanks is then a detection circuit is required, which marks in which from m sections the signal sample taken is located. Accordingly, instead of 2 η mn there are binary storage locations necessary. The integration to the function t (u) then takes place per section v / i ed er um according to, the aforementioned summation rule. Such a circuit arrangement naturally only works properly as long as the number the polarity change of the derivative ^ du / dt actually occurring per oscillation period is less than the number m of Sections is.

The memory 7 can be, for example, a ferrite core memory. The following arithmetic unit 9 determines via the reading circuit 8, when one of the memory locations is the first to reach the maximum count. This information is sent to the control circuit 10 communicated, in turn 'the sampling process by suitable control of the random pulse generator 3 interrupts. After the sampling process, the computing process for determining the signal-voltage-time function begins the storage data, in which only the computer part shown in the right part of the figure is involved. The one from the control circuit 10 initiated computer steps can be, for example, the following be:

a) Removal of the binary value B. of the i-th memory location in the arithmetic unit, which is assigned to the lowest voltage level is.

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b *) removing the binary value _"1 .. B of the (i + 1) th-Speieher- assigned space, v / hich the next higher signal voltage level. '.

c) Addition B ₁ + B _{1 + 1} = t _±

t. then corresponds to the time increment between the two Voltage values that are assigned to the "two binary values B. and B: ^ are. . .

d) From storage of t ^. , ■ '.

e) Removal of B. “from £ i + 2) ~ th storage space in the arithmetic unit . ·

f) Addition: • fc _i + B _{i + 2} = t _{i + 1} "·

g) Storage of t. * · · · "·

etc., ■ ' ^x '

After all binary values have been processed, one edge will be the binary values of the other plank are processed accordingly one after the other. After completing the integration process described there are 2 ή binary values in the memory as dimensions for the individual between the adjacent amplitude values applicable time intervals.

The ones for the described accumulation and calculation process Required assemblies can be known and not detailed

circuit techniques described be constructed.

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If the circuit is to be able to also process periodic signals with a sense of slope more than once within a period changes to identify properly, the plan detector 5 must be able to recognize which of the 'm section te of the oscillation period the respective sampled value was taken. This increases the capacity of the memory by the factor m / 2. The structure and mode of operation of the circuit do not change in principle compared to the illustration above.

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Claims: ~ 9 -.

Claims (6)

Claims:. 1.J) Circuit arrangement for obtaining the voltage-time Function of periodic signals, since ^ urglb._ j ^ elc indicates _} that the signal is a first. Input of an analog gate - (2), whose output is connected to the inputs of an amplitude detector (4) and a plank detector (5), the outputs of which are connected to. two inputs of an addressing and writing circuit. (6), which via a memory (7) and a read circuit (8) to a first direct output (11) and via a computing ■ * plant (9) leads to a two output (12) that the Arithmetic unit (9) with another input of the addressing and write circuit (6) is connected and that a control circuit (10) is provided which is connected to the addressing and write circuit (6), the read circuit (8), the arithmetic unit (9) and a random pulse generator (3) is connected to the Analog-Cor (2). . 2.) Circuit arrangement according to claim 1, characterized in that that the amplitude detector (4) for each to be detected Voltage interval has an output on v / e. 3.) Circuit arrangement according to claim 1 or 2, characterized in that that means for distinguishing positive and negative going signal edges are provided. 4.) Circuit arrangement according to claim 3 »characterized in that that the differentiating means of the amplitude detector (4) lsi 309884/0790 - 10 - ~ ¹⁰ ~ 2233Λ48 5.) Circuit arrangement according to one of claims 1 to 4, characterized in that the memory (7) is one of the . contains the number of binary value storage locations corresponding to twice the number of voltage intervals. 6.) Circuit arrangement according to one of claims 1 "to 5, characterized in that the memory (7) is a ferrite core memory is. t ■ 309884/0790 Blank page